1 //===-- RISCVInstrInfo.h - RISCV Instruction Information --------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file contains the RISCV implementation of the TargetInstrInfo class. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #ifndef LLVM_LIB_TARGET_RISCV_RISCVINSTRINFO_H 14 #define LLVM_LIB_TARGET_RISCV_RISCVINSTRINFO_H 15 16 #include "RISCVRegisterInfo.h" 17 #include "llvm/CodeGen/TargetInstrInfo.h" 18 #include "llvm/IR/DiagnosticInfo.h" 19 20 #define GET_INSTRINFO_HEADER 21 #define GET_INSTRINFO_OPERAND_ENUM 22 #include "RISCVGenInstrInfo.inc" 23 24 namespace llvm { 25 26 class RISCVSubtarget; 27 28 namespace RISCVCC { 29 30 enum CondCode { 31 COND_EQ, 32 COND_NE, 33 COND_LT, 34 COND_GE, 35 COND_LTU, 36 COND_GEU, 37 COND_INVALID 38 }; 39 40 CondCode getOppositeBranchCondition(CondCode); 41 42 } // end of namespace RISCVCC 43 44 class RISCVInstrInfo : public RISCVGenInstrInfo { 45 46 public: 47 explicit RISCVInstrInfo(RISCVSubtarget &STI); 48 49 MCInst getNop() const override; 50 const MCInstrDesc &getBrCond(RISCVCC::CondCode CC) const; 51 52 unsigned isLoadFromStackSlot(const MachineInstr &MI, 53 int &FrameIndex) const override; 54 unsigned isStoreToStackSlot(const MachineInstr &MI, 55 int &FrameIndex) const override; 56 57 void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, 58 const DebugLoc &DL, MCRegister DstReg, MCRegister SrcReg, 59 bool KillSrc) const override; 60 61 void storeRegToStackSlot(MachineBasicBlock &MBB, 62 MachineBasicBlock::iterator MBBI, Register SrcReg, 63 bool IsKill, int FrameIndex, 64 const TargetRegisterClass *RC, 65 const TargetRegisterInfo *TRI) const override; 66 67 void loadRegFromStackSlot(MachineBasicBlock &MBB, 68 MachineBasicBlock::iterator MBBI, Register DstReg, 69 int FrameIndex, const TargetRegisterClass *RC, 70 const TargetRegisterInfo *TRI) const override; 71 72 using TargetInstrInfo::foldMemoryOperandImpl; 73 MachineInstr *foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI, 74 ArrayRef<unsigned> Ops, 75 MachineBasicBlock::iterator InsertPt, 76 int FrameIndex, 77 LiveIntervals *LIS = nullptr, 78 VirtRegMap *VRM = nullptr) const override; 79 80 // Materializes the given integer Val into DstReg. 81 void movImm(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, 82 const DebugLoc &DL, Register DstReg, uint64_t Val, 83 MachineInstr::MIFlag Flag = MachineInstr::NoFlags) const; 84 85 unsigned getInstSizeInBytes(const MachineInstr &MI) const override; 86 87 bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 88 MachineBasicBlock *&FBB, 89 SmallVectorImpl<MachineOperand> &Cond, 90 bool AllowModify) const override; 91 92 unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 93 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond, 94 const DebugLoc &dl, 95 int *BytesAdded = nullptr) const override; 96 97 void insertIndirectBranch(MachineBasicBlock &MBB, 98 MachineBasicBlock &NewDestBB, 99 MachineBasicBlock &RestoreBB, const DebugLoc &DL, 100 int64_t BrOffset, RegScavenger *RS) const override; 101 102 unsigned removeBranch(MachineBasicBlock &MBB, 103 int *BytesRemoved = nullptr) const override; 104 105 bool 106 reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override; 107 108 MachineBasicBlock *getBranchDestBlock(const MachineInstr &MI) const override; 109 110 bool isBranchOffsetInRange(unsigned BranchOpc, 111 int64_t BrOffset) const override; 112 113 bool isAsCheapAsAMove(const MachineInstr &MI) const override; 114 115 Optional<DestSourcePair> 116 isCopyInstrImpl(const MachineInstr &MI) const override; 117 118 bool verifyInstruction(const MachineInstr &MI, 119 StringRef &ErrInfo) const override; 120 121 bool getMemOperandWithOffsetWidth(const MachineInstr &LdSt, 122 const MachineOperand *&BaseOp, 123 int64_t &Offset, unsigned &Width, 124 const TargetRegisterInfo *TRI) const; 125 126 bool areMemAccessesTriviallyDisjoint(const MachineInstr &MIa, 127 const MachineInstr &MIb) const override; 128 129 130 std::pair<unsigned, unsigned> 131 decomposeMachineOperandsTargetFlags(unsigned TF) const override; 132 133 ArrayRef<std::pair<unsigned, const char *>> 134 getSerializableDirectMachineOperandTargetFlags() const override; 135 136 // Return true if the function can safely be outlined from. 137 virtual bool 138 isFunctionSafeToOutlineFrom(MachineFunction &MF, 139 bool OutlineFromLinkOnceODRs) const override; 140 141 // Return true if MBB is safe to outline from, and return any target-specific 142 // information in Flags. 143 virtual bool isMBBSafeToOutlineFrom(MachineBasicBlock &MBB, 144 unsigned &Flags) const override; 145 146 bool shouldOutlineFromFunctionByDefault(MachineFunction &MF) const override; 147 148 // Calculate target-specific information for a set of outlining candidates. 149 outliner::OutlinedFunction getOutliningCandidateInfo( 150 std::vector<outliner::Candidate> &RepeatedSequenceLocs) const override; 151 152 // Return if/how a given MachineInstr should be outlined. 153 virtual outliner::InstrType 154 getOutliningType(MachineBasicBlock::iterator &MBBI, 155 unsigned Flags) const override; 156 157 // Insert a custom frame for outlined functions. 158 virtual void 159 buildOutlinedFrame(MachineBasicBlock &MBB, MachineFunction &MF, 160 const outliner::OutlinedFunction &OF) const override; 161 162 // Insert a call to an outlined function into a given basic block. 163 virtual MachineBasicBlock::iterator 164 insertOutlinedCall(Module &M, MachineBasicBlock &MBB, 165 MachineBasicBlock::iterator &It, MachineFunction &MF, 166 outliner::Candidate &C) const override; 167 168 bool findCommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx1, 169 unsigned &SrcOpIdx2) const override; 170 MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI, 171 unsigned OpIdx1, 172 unsigned OpIdx2) const override; 173 174 MachineInstr *convertToThreeAddress(MachineInstr &MI, LiveVariables *LV, 175 LiveIntervals *LIS) const override; 176 177 // MIR printer helper function to annotate Operands with a comment. 178 std::string 179 createMIROperandComment(const MachineInstr &MI, const MachineOperand &Op, 180 unsigned OpIdx, 181 const TargetRegisterInfo *TRI) const override; 182 183 Register getVLENFactoredAmount( 184 MachineFunction &MF, MachineBasicBlock &MBB, 185 MachineBasicBlock::iterator II, const DebugLoc &DL, int64_t Amount, 186 MachineInstr::MIFlag Flag = MachineInstr::NoFlags) const; 187 188 protected: 189 const RISCVSubtarget &STI; 190 }; 191 192 namespace RISCV { 193 194 // Returns true if this is the sext.w pattern, addiw rd, rs1, 0. 195 bool isSEXT_W(const MachineInstr &MI); 196 197 // Returns true if the given MI is an RVV instruction opcode for which we may 198 // expect to see a FrameIndex operand. 199 bool isRVVSpill(const MachineInstr &MI); 200 201 Optional<std::pair<unsigned, unsigned>> isRVVSpillForZvlsseg(unsigned Opcode); 202 203 bool isFaultFirstLoad(const MachineInstr &MI); 204 205 // Implemented in RISCVGenInstrInfo.inc 206 int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIndex); 207 208 // Special immediate for AVL operand of V pseudo instructions to indicate VLMax. 209 static constexpr int64_t VLMaxSentinel = -1LL; 210 } // namespace RISCV 211 212 namespace RISCVVPseudosTable { 213 214 struct PseudoInfo { 215 uint16_t Pseudo; 216 uint16_t BaseInstr; 217 }; 218 219 #define GET_RISCVVPseudosTable_DECL 220 #include "RISCVGenSearchableTables.inc" 221 222 } // end namespace RISCVVPseudosTable 223 224 } // end namespace llvm 225 #endif 226