1 //===-- RISCVInstrInfo.cpp - RISCV Instruction Information ------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the RISCV implementation of the TargetInstrInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "RISCVInstrInfo.h"
14 #include "MCTargetDesc/RISCVMatInt.h"
15 #include "RISCV.h"
16 #include "RISCVMachineFunctionInfo.h"
17 #include "RISCVSubtarget.h"
18 #include "RISCVTargetMachine.h"
19 #include "llvm/ADT/STLExtras.h"
20 #include "llvm/ADT/SmallVector.h"
21 #include "llvm/Analysis/MemoryLocation.h"
22 #include "llvm/CodeGen/MachineFunctionPass.h"
23 #include "llvm/CodeGen/MachineInstrBuilder.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/CodeGen/RegisterScavenging.h"
26 #include "llvm/MC/MCInstBuilder.h"
27 #include "llvm/Support/ErrorHandling.h"
28 #include "llvm/Support/TargetRegistry.h"
29 
30 using namespace llvm;
31 
32 #define GEN_CHECK_COMPRESS_INSTR
33 #include "RISCVGenCompressInstEmitter.inc"
34 
35 #define GET_INSTRINFO_CTOR_DTOR
36 #include "RISCVGenInstrInfo.inc"
37 
38 namespace llvm {
39 namespace RISCVVPseudosTable {
40 
41 using namespace RISCV;
42 
43 #define GET_RISCVVPseudosTable_IMPL
44 #include "RISCVGenSearchableTables.inc"
45 
46 } // namespace RISCVVPseudosTable
47 } // namespace llvm
48 
49 RISCVInstrInfo::RISCVInstrInfo(RISCVSubtarget &STI)
50     : RISCVGenInstrInfo(RISCV::ADJCALLSTACKDOWN, RISCV::ADJCALLSTACKUP),
51       STI(STI) {}
52 
53 MCInst RISCVInstrInfo::getNop() const {
54   if (STI.getFeatureBits()[RISCV::FeatureStdExtC])
55     return MCInstBuilder(RISCV::C_NOP);
56   return MCInstBuilder(RISCV::ADDI)
57       .addReg(RISCV::X0)
58       .addReg(RISCV::X0)
59       .addImm(0);
60 }
61 
62 unsigned RISCVInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
63                                              int &FrameIndex) const {
64   switch (MI.getOpcode()) {
65   default:
66     return 0;
67   case RISCV::LB:
68   case RISCV::LBU:
69   case RISCV::LH:
70   case RISCV::LHU:
71   case RISCV::FLH:
72   case RISCV::LW:
73   case RISCV::FLW:
74   case RISCV::LWU:
75   case RISCV::LD:
76   case RISCV::FLD:
77     break;
78   }
79 
80   if (MI.getOperand(1).isFI() && MI.getOperand(2).isImm() &&
81       MI.getOperand(2).getImm() == 0) {
82     FrameIndex = MI.getOperand(1).getIndex();
83     return MI.getOperand(0).getReg();
84   }
85 
86   return 0;
87 }
88 
89 unsigned RISCVInstrInfo::isStoreToStackSlot(const MachineInstr &MI,
90                                             int &FrameIndex) const {
91   switch (MI.getOpcode()) {
92   default:
93     return 0;
94   case RISCV::SB:
95   case RISCV::SH:
96   case RISCV::SW:
97   case RISCV::FSH:
98   case RISCV::FSW:
99   case RISCV::SD:
100   case RISCV::FSD:
101     break;
102   }
103 
104   if (MI.getOperand(1).isFI() && MI.getOperand(2).isImm() &&
105       MI.getOperand(2).getImm() == 0) {
106     FrameIndex = MI.getOperand(1).getIndex();
107     return MI.getOperand(0).getReg();
108   }
109 
110   return 0;
111 }
112 
113 void RISCVInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
114                                  MachineBasicBlock::iterator MBBI,
115                                  const DebugLoc &DL, MCRegister DstReg,
116                                  MCRegister SrcReg, bool KillSrc) const {
117   if (RISCV::GPRRegClass.contains(DstReg, SrcReg)) {
118     BuildMI(MBB, MBBI, DL, get(RISCV::ADDI), DstReg)
119         .addReg(SrcReg, getKillRegState(KillSrc))
120         .addImm(0);
121     return;
122   }
123 
124   // FPR->FPR copies and VR->VR copies.
125   unsigned Opc;
126   bool IsScalableVector = false;
127   if (RISCV::FPR16RegClass.contains(DstReg, SrcReg))
128     Opc = RISCV::FSGNJ_H;
129   else if (RISCV::FPR32RegClass.contains(DstReg, SrcReg))
130     Opc = RISCV::FSGNJ_S;
131   else if (RISCV::FPR64RegClass.contains(DstReg, SrcReg))
132     Opc = RISCV::FSGNJ_D;
133   else if (RISCV::VRRegClass.contains(DstReg, SrcReg)) {
134     Opc = RISCV::PseudoVMV1R_V;
135     IsScalableVector = true;
136   } else if (RISCV::VRM2RegClass.contains(DstReg, SrcReg)) {
137     Opc = RISCV::PseudoVMV2R_V;
138     IsScalableVector = true;
139   } else if (RISCV::VRM4RegClass.contains(DstReg, SrcReg)) {
140     Opc = RISCV::PseudoVMV4R_V;
141     IsScalableVector = true;
142   } else if (RISCV::VRM8RegClass.contains(DstReg, SrcReg)) {
143     Opc = RISCV::PseudoVMV8R_V;
144     IsScalableVector = true;
145   } else
146     llvm_unreachable("Impossible reg-to-reg copy");
147 
148   if (IsScalableVector)
149     BuildMI(MBB, MBBI, DL, get(Opc), DstReg)
150         .addReg(SrcReg, getKillRegState(KillSrc));
151   else
152     BuildMI(MBB, MBBI, DL, get(Opc), DstReg)
153         .addReg(SrcReg, getKillRegState(KillSrc))
154         .addReg(SrcReg, getKillRegState(KillSrc));
155 }
156 
157 void RISCVInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
158                                          MachineBasicBlock::iterator I,
159                                          Register SrcReg, bool IsKill, int FI,
160                                          const TargetRegisterClass *RC,
161                                          const TargetRegisterInfo *TRI) const {
162   DebugLoc DL;
163   if (I != MBB.end())
164     DL = I->getDebugLoc();
165 
166   MachineFunction *MF = MBB.getParent();
167   MachineFrameInfo &MFI = MF->getFrameInfo();
168 
169   unsigned Opcode;
170   bool IsScalableVector = true;
171   bool IsZvlsseg = true;
172   if (RISCV::GPRRegClass.hasSubClassEq(RC)) {
173     Opcode = TRI->getRegSizeInBits(RISCV::GPRRegClass) == 32 ?
174              RISCV::SW : RISCV::SD;
175     IsScalableVector = false;
176   } else if (RISCV::FPR16RegClass.hasSubClassEq(RC)) {
177     Opcode = RISCV::FSH;
178     IsScalableVector = false;
179   } else if (RISCV::FPR32RegClass.hasSubClassEq(RC)) {
180     Opcode = RISCV::FSW;
181     IsScalableVector = false;
182   } else if (RISCV::FPR64RegClass.hasSubClassEq(RC)) {
183     Opcode = RISCV::FSD;
184     IsScalableVector = false;
185   } else if (RISCV::VRRegClass.hasSubClassEq(RC)) {
186     Opcode = RISCV::PseudoVSPILL_M1;
187     IsZvlsseg = false;
188   } else if (RISCV::VRM2RegClass.hasSubClassEq(RC)) {
189     Opcode = RISCV::PseudoVSPILL_M2;
190     IsZvlsseg = false;
191   } else if (RISCV::VRM4RegClass.hasSubClassEq(RC)) {
192     Opcode = RISCV::PseudoVSPILL_M4;
193     IsZvlsseg = false;
194   } else if (RISCV::VRM8RegClass.hasSubClassEq(RC)) {
195     Opcode = RISCV::PseudoVSPILL_M8;
196     IsZvlsseg = false;
197   } else if (RISCV::VRN2M1RegClass.hasSubClassEq(RC))
198     Opcode = RISCV::PseudoVSPILL2_M1;
199   else if (RISCV::VRN2M2RegClass.hasSubClassEq(RC))
200     Opcode = RISCV::PseudoVSPILL2_M2;
201   else if (RISCV::VRN2M4RegClass.hasSubClassEq(RC))
202     Opcode = RISCV::PseudoVSPILL2_M4;
203   else if (RISCV::VRN3M1RegClass.hasSubClassEq(RC))
204     Opcode = RISCV::PseudoVSPILL3_M1;
205   else if (RISCV::VRN3M2RegClass.hasSubClassEq(RC))
206     Opcode = RISCV::PseudoVSPILL3_M2;
207   else if (RISCV::VRN4M1RegClass.hasSubClassEq(RC))
208     Opcode = RISCV::PseudoVSPILL4_M1;
209   else if (RISCV::VRN4M2RegClass.hasSubClassEq(RC))
210     Opcode = RISCV::PseudoVSPILL4_M2;
211   else if (RISCV::VRN5M1RegClass.hasSubClassEq(RC))
212     Opcode = RISCV::PseudoVSPILL5_M1;
213   else if (RISCV::VRN6M1RegClass.hasSubClassEq(RC))
214     Opcode = RISCV::PseudoVSPILL6_M1;
215   else if (RISCV::VRN7M1RegClass.hasSubClassEq(RC))
216     Opcode = RISCV::PseudoVSPILL7_M1;
217   else if (RISCV::VRN8M1RegClass.hasSubClassEq(RC))
218     Opcode = RISCV::PseudoVSPILL8_M1;
219   else
220     llvm_unreachable("Can't store this register to stack slot");
221 
222   if (IsScalableVector) {
223     MachineMemOperand *MMO = MF->getMachineMemOperand(
224         MachinePointerInfo::getFixedStack(*MF, FI), MachineMemOperand::MOStore,
225         MemoryLocation::UnknownSize, MFI.getObjectAlign(FI));
226 
227     MFI.setStackID(FI, TargetStackID::ScalableVector);
228     auto MIB = BuildMI(MBB, I, DL, get(Opcode))
229                    .addReg(SrcReg, getKillRegState(IsKill))
230                    .addFrameIndex(FI)
231                    .addMemOperand(MMO);
232     if (IsZvlsseg) {
233       // For spilling/reloading Zvlsseg registers, append the dummy field for
234       // the scaled vector length. The argument will be used when expanding
235       // these pseudo instructions.
236       MIB.addReg(RISCV::X0);
237     }
238   } else {
239     MachineMemOperand *MMO = MF->getMachineMemOperand(
240         MachinePointerInfo::getFixedStack(*MF, FI), MachineMemOperand::MOStore,
241         MFI.getObjectSize(FI), MFI.getObjectAlign(FI));
242 
243     BuildMI(MBB, I, DL, get(Opcode))
244         .addReg(SrcReg, getKillRegState(IsKill))
245         .addFrameIndex(FI)
246         .addImm(0)
247         .addMemOperand(MMO);
248   }
249 }
250 
251 void RISCVInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
252                                           MachineBasicBlock::iterator I,
253                                           Register DstReg, int FI,
254                                           const TargetRegisterClass *RC,
255                                           const TargetRegisterInfo *TRI) const {
256   DebugLoc DL;
257   if (I != MBB.end())
258     DL = I->getDebugLoc();
259 
260   MachineFunction *MF = MBB.getParent();
261   MachineFrameInfo &MFI = MF->getFrameInfo();
262 
263   unsigned Opcode;
264   bool IsScalableVector = true;
265   bool IsZvlsseg = true;
266   if (RISCV::GPRRegClass.hasSubClassEq(RC)) {
267     Opcode = TRI->getRegSizeInBits(RISCV::GPRRegClass) == 32 ?
268              RISCV::LW : RISCV::LD;
269     IsScalableVector = false;
270   } else if (RISCV::FPR16RegClass.hasSubClassEq(RC)) {
271     Opcode = RISCV::FLH;
272     IsScalableVector = false;
273   } else if (RISCV::FPR32RegClass.hasSubClassEq(RC)) {
274     Opcode = RISCV::FLW;
275     IsScalableVector = false;
276   } else if (RISCV::FPR64RegClass.hasSubClassEq(RC)) {
277     Opcode = RISCV::FLD;
278     IsScalableVector = false;
279   } else if (RISCV::VRRegClass.hasSubClassEq(RC)) {
280     Opcode = RISCV::PseudoVRELOAD_M1;
281     IsZvlsseg = false;
282   } else if (RISCV::VRM2RegClass.hasSubClassEq(RC)) {
283     Opcode = RISCV::PseudoVRELOAD_M2;
284     IsZvlsseg = false;
285   } else if (RISCV::VRM4RegClass.hasSubClassEq(RC)) {
286     Opcode = RISCV::PseudoVRELOAD_M4;
287     IsZvlsseg = false;
288   } else if (RISCV::VRM8RegClass.hasSubClassEq(RC)) {
289     Opcode = RISCV::PseudoVRELOAD_M8;
290     IsZvlsseg = false;
291   } else if (RISCV::VRN2M1RegClass.hasSubClassEq(RC))
292     Opcode = RISCV::PseudoVRELOAD2_M1;
293   else if (RISCV::VRN2M2RegClass.hasSubClassEq(RC))
294     Opcode = RISCV::PseudoVRELOAD2_M2;
295   else if (RISCV::VRN2M4RegClass.hasSubClassEq(RC))
296     Opcode = RISCV::PseudoVRELOAD2_M4;
297   else if (RISCV::VRN3M1RegClass.hasSubClassEq(RC))
298     Opcode = RISCV::PseudoVRELOAD3_M1;
299   else if (RISCV::VRN3M2RegClass.hasSubClassEq(RC))
300     Opcode = RISCV::PseudoVRELOAD3_M2;
301   else if (RISCV::VRN4M1RegClass.hasSubClassEq(RC))
302     Opcode = RISCV::PseudoVRELOAD4_M1;
303   else if (RISCV::VRN4M2RegClass.hasSubClassEq(RC))
304     Opcode = RISCV::PseudoVRELOAD4_M2;
305   else if (RISCV::VRN5M1RegClass.hasSubClassEq(RC))
306     Opcode = RISCV::PseudoVRELOAD5_M1;
307   else if (RISCV::VRN6M1RegClass.hasSubClassEq(RC))
308     Opcode = RISCV::PseudoVRELOAD6_M1;
309   else if (RISCV::VRN7M1RegClass.hasSubClassEq(RC))
310     Opcode = RISCV::PseudoVRELOAD7_M1;
311   else if (RISCV::VRN8M1RegClass.hasSubClassEq(RC))
312     Opcode = RISCV::PseudoVRELOAD8_M1;
313   else
314     llvm_unreachable("Can't load this register from stack slot");
315 
316   if (IsScalableVector) {
317     MachineMemOperand *MMO = MF->getMachineMemOperand(
318         MachinePointerInfo::getFixedStack(*MF, FI), MachineMemOperand::MOLoad,
319         MemoryLocation::UnknownSize, MFI.getObjectAlign(FI));
320 
321     MFI.setStackID(FI, TargetStackID::ScalableVector);
322     auto MIB = BuildMI(MBB, I, DL, get(Opcode), DstReg)
323                    .addFrameIndex(FI)
324                    .addMemOperand(MMO);
325     if (IsZvlsseg) {
326       // For spilling/reloading Zvlsseg registers, append the dummy field for
327       // the scaled vector length. The argument will be used when expanding
328       // these pseudo instructions.
329       MIB.addReg(RISCV::X0);
330     }
331   } else {
332     MachineMemOperand *MMO = MF->getMachineMemOperand(
333         MachinePointerInfo::getFixedStack(*MF, FI), MachineMemOperand::MOLoad,
334         MFI.getObjectSize(FI), MFI.getObjectAlign(FI));
335 
336     BuildMI(MBB, I, DL, get(Opcode), DstReg)
337         .addFrameIndex(FI)
338         .addImm(0)
339         .addMemOperand(MMO);
340   }
341 }
342 
343 void RISCVInstrInfo::movImm(MachineBasicBlock &MBB,
344                             MachineBasicBlock::iterator MBBI,
345                             const DebugLoc &DL, Register DstReg, uint64_t Val,
346                             MachineInstr::MIFlag Flag) const {
347   MachineFunction *MF = MBB.getParent();
348   MachineRegisterInfo &MRI = MF->getRegInfo();
349   bool IsRV64 = MF->getSubtarget<RISCVSubtarget>().is64Bit();
350   Register SrcReg = RISCV::X0;
351   Register Result = MRI.createVirtualRegister(&RISCV::GPRRegClass);
352   unsigned Num = 0;
353 
354   if (!IsRV64 && !isInt<32>(Val))
355     report_fatal_error("Should only materialize 32-bit constants for RV32");
356 
357   RISCVMatInt::InstSeq Seq;
358   RISCVMatInt::generateInstSeq(Val, IsRV64, Seq);
359   assert(Seq.size() > 0);
360 
361   for (RISCVMatInt::Inst &Inst : Seq) {
362     // Write the final result to DstReg if it's the last instruction in the Seq.
363     // Otherwise, write the result to the temp register.
364     if (++Num == Seq.size())
365       Result = DstReg;
366 
367     if (Inst.Opc == RISCV::LUI) {
368       BuildMI(MBB, MBBI, DL, get(RISCV::LUI), Result)
369           .addImm(Inst.Imm)
370           .setMIFlag(Flag);
371     } else {
372       BuildMI(MBB, MBBI, DL, get(Inst.Opc), Result)
373           .addReg(SrcReg, RegState::Kill)
374           .addImm(Inst.Imm)
375           .setMIFlag(Flag);
376     }
377     // Only the first instruction has X0 as its source.
378     SrcReg = Result;
379   }
380 }
381 
382 // The contents of values added to Cond are not examined outside of
383 // RISCVInstrInfo, giving us flexibility in what to push to it. For RISCV, we
384 // push BranchOpcode, Reg1, Reg2.
385 static void parseCondBranch(MachineInstr &LastInst, MachineBasicBlock *&Target,
386                             SmallVectorImpl<MachineOperand> &Cond) {
387   // Block ends with fall-through condbranch.
388   assert(LastInst.getDesc().isConditionalBranch() &&
389          "Unknown conditional branch");
390   Target = LastInst.getOperand(2).getMBB();
391   Cond.push_back(MachineOperand::CreateImm(LastInst.getOpcode()));
392   Cond.push_back(LastInst.getOperand(0));
393   Cond.push_back(LastInst.getOperand(1));
394 }
395 
396 static unsigned getOppositeBranchOpcode(int Opc) {
397   switch (Opc) {
398   default:
399     llvm_unreachable("Unrecognized conditional branch");
400   case RISCV::BEQ:
401     return RISCV::BNE;
402   case RISCV::BNE:
403     return RISCV::BEQ;
404   case RISCV::BLT:
405     return RISCV::BGE;
406   case RISCV::BGE:
407     return RISCV::BLT;
408   case RISCV::BLTU:
409     return RISCV::BGEU;
410   case RISCV::BGEU:
411     return RISCV::BLTU;
412   }
413 }
414 
415 bool RISCVInstrInfo::analyzeBranch(MachineBasicBlock &MBB,
416                                    MachineBasicBlock *&TBB,
417                                    MachineBasicBlock *&FBB,
418                                    SmallVectorImpl<MachineOperand> &Cond,
419                                    bool AllowModify) const {
420   TBB = FBB = nullptr;
421   Cond.clear();
422 
423   // If the block has no terminators, it just falls into the block after it.
424   MachineBasicBlock::iterator I = MBB.getLastNonDebugInstr();
425   if (I == MBB.end() || !isUnpredicatedTerminator(*I))
426     return false;
427 
428   // Count the number of terminators and find the first unconditional or
429   // indirect branch.
430   MachineBasicBlock::iterator FirstUncondOrIndirectBr = MBB.end();
431   int NumTerminators = 0;
432   for (auto J = I.getReverse(); J != MBB.rend() && isUnpredicatedTerminator(*J);
433        J++) {
434     NumTerminators++;
435     if (J->getDesc().isUnconditionalBranch() ||
436         J->getDesc().isIndirectBranch()) {
437       FirstUncondOrIndirectBr = J.getReverse();
438     }
439   }
440 
441   // If AllowModify is true, we can erase any terminators after
442   // FirstUncondOrIndirectBR.
443   if (AllowModify && FirstUncondOrIndirectBr != MBB.end()) {
444     while (std::next(FirstUncondOrIndirectBr) != MBB.end()) {
445       std::next(FirstUncondOrIndirectBr)->eraseFromParent();
446       NumTerminators--;
447     }
448     I = FirstUncondOrIndirectBr;
449   }
450 
451   // We can't handle blocks that end in an indirect branch.
452   if (I->getDesc().isIndirectBranch())
453     return true;
454 
455   // We can't handle blocks with more than 2 terminators.
456   if (NumTerminators > 2)
457     return true;
458 
459   // Handle a single unconditional branch.
460   if (NumTerminators == 1 && I->getDesc().isUnconditionalBranch()) {
461     TBB = getBranchDestBlock(*I);
462     return false;
463   }
464 
465   // Handle a single conditional branch.
466   if (NumTerminators == 1 && I->getDesc().isConditionalBranch()) {
467     parseCondBranch(*I, TBB, Cond);
468     return false;
469   }
470 
471   // Handle a conditional branch followed by an unconditional branch.
472   if (NumTerminators == 2 && std::prev(I)->getDesc().isConditionalBranch() &&
473       I->getDesc().isUnconditionalBranch()) {
474     parseCondBranch(*std::prev(I), TBB, Cond);
475     FBB = getBranchDestBlock(*I);
476     return false;
477   }
478 
479   // Otherwise, we can't handle this.
480   return true;
481 }
482 
483 unsigned RISCVInstrInfo::removeBranch(MachineBasicBlock &MBB,
484                                       int *BytesRemoved) const {
485   if (BytesRemoved)
486     *BytesRemoved = 0;
487   MachineBasicBlock::iterator I = MBB.getLastNonDebugInstr();
488   if (I == MBB.end())
489     return 0;
490 
491   if (!I->getDesc().isUnconditionalBranch() &&
492       !I->getDesc().isConditionalBranch())
493     return 0;
494 
495   // Remove the branch.
496   if (BytesRemoved)
497     *BytesRemoved += getInstSizeInBytes(*I);
498   I->eraseFromParent();
499 
500   I = MBB.end();
501 
502   if (I == MBB.begin())
503     return 1;
504   --I;
505   if (!I->getDesc().isConditionalBranch())
506     return 1;
507 
508   // Remove the branch.
509   if (BytesRemoved)
510     *BytesRemoved += getInstSizeInBytes(*I);
511   I->eraseFromParent();
512   return 2;
513 }
514 
515 // Inserts a branch into the end of the specific MachineBasicBlock, returning
516 // the number of instructions inserted.
517 unsigned RISCVInstrInfo::insertBranch(
518     MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB,
519     ArrayRef<MachineOperand> Cond, const DebugLoc &DL, int *BytesAdded) const {
520   if (BytesAdded)
521     *BytesAdded = 0;
522 
523   // Shouldn't be a fall through.
524   assert(TBB && "insertBranch must not be told to insert a fallthrough");
525   assert((Cond.size() == 3 || Cond.size() == 0) &&
526          "RISCV branch conditions have two components!");
527 
528   // Unconditional branch.
529   if (Cond.empty()) {
530     MachineInstr &MI = *BuildMI(&MBB, DL, get(RISCV::PseudoBR)).addMBB(TBB);
531     if (BytesAdded)
532       *BytesAdded += getInstSizeInBytes(MI);
533     return 1;
534   }
535 
536   // Either a one or two-way conditional branch.
537   unsigned Opc = Cond[0].getImm();
538   MachineInstr &CondMI =
539       *BuildMI(&MBB, DL, get(Opc)).add(Cond[1]).add(Cond[2]).addMBB(TBB);
540   if (BytesAdded)
541     *BytesAdded += getInstSizeInBytes(CondMI);
542 
543   // One-way conditional branch.
544   if (!FBB)
545     return 1;
546 
547   // Two-way conditional branch.
548   MachineInstr &MI = *BuildMI(&MBB, DL, get(RISCV::PseudoBR)).addMBB(FBB);
549   if (BytesAdded)
550     *BytesAdded += getInstSizeInBytes(MI);
551   return 2;
552 }
553 
554 unsigned RISCVInstrInfo::insertIndirectBranch(MachineBasicBlock &MBB,
555                                               MachineBasicBlock &DestBB,
556                                               const DebugLoc &DL,
557                                               int64_t BrOffset,
558                                               RegScavenger *RS) const {
559   assert(RS && "RegScavenger required for long branching");
560   assert(MBB.empty() &&
561          "new block should be inserted for expanding unconditional branch");
562   assert(MBB.pred_size() == 1);
563 
564   MachineFunction *MF = MBB.getParent();
565   MachineRegisterInfo &MRI = MF->getRegInfo();
566 
567   if (!isInt<32>(BrOffset))
568     report_fatal_error(
569         "Branch offsets outside of the signed 32-bit range not supported");
570 
571   // FIXME: A virtual register must be used initially, as the register
572   // scavenger won't work with empty blocks (SIInstrInfo::insertIndirectBranch
573   // uses the same workaround).
574   Register ScratchReg = MRI.createVirtualRegister(&RISCV::GPRRegClass);
575   auto II = MBB.end();
576 
577   MachineInstr &MI = *BuildMI(MBB, II, DL, get(RISCV::PseudoJump))
578                           .addReg(ScratchReg, RegState::Define | RegState::Dead)
579                           .addMBB(&DestBB, RISCVII::MO_CALL);
580 
581   RS->enterBasicBlockEnd(MBB);
582   unsigned Scav = RS->scavengeRegisterBackwards(RISCV::GPRRegClass,
583                                                 MI.getIterator(), false, 0);
584   MRI.replaceRegWith(ScratchReg, Scav);
585   MRI.clearVirtRegs();
586   RS->setRegUsed(Scav);
587   return 8;
588 }
589 
590 bool RISCVInstrInfo::reverseBranchCondition(
591     SmallVectorImpl<MachineOperand> &Cond) const {
592   assert((Cond.size() == 3) && "Invalid branch condition!");
593   Cond[0].setImm(getOppositeBranchOpcode(Cond[0].getImm()));
594   return false;
595 }
596 
597 MachineBasicBlock *
598 RISCVInstrInfo::getBranchDestBlock(const MachineInstr &MI) const {
599   assert(MI.getDesc().isBranch() && "Unexpected opcode!");
600   // The branch target is always the last operand.
601   int NumOp = MI.getNumExplicitOperands();
602   return MI.getOperand(NumOp - 1).getMBB();
603 }
604 
605 bool RISCVInstrInfo::isBranchOffsetInRange(unsigned BranchOp,
606                                            int64_t BrOffset) const {
607   unsigned XLen = STI.getXLen();
608   // Ideally we could determine the supported branch offset from the
609   // RISCVII::FormMask, but this can't be used for Pseudo instructions like
610   // PseudoBR.
611   switch (BranchOp) {
612   default:
613     llvm_unreachable("Unexpected opcode!");
614   case RISCV::BEQ:
615   case RISCV::BNE:
616   case RISCV::BLT:
617   case RISCV::BGE:
618   case RISCV::BLTU:
619   case RISCV::BGEU:
620     return isIntN(13, BrOffset);
621   case RISCV::JAL:
622   case RISCV::PseudoBR:
623     return isIntN(21, BrOffset);
624   case RISCV::PseudoJump:
625     return isIntN(32, SignExtend64(BrOffset + 0x800, XLen));
626   }
627 }
628 
629 unsigned RISCVInstrInfo::getInstSizeInBytes(const MachineInstr &MI) const {
630   unsigned Opcode = MI.getOpcode();
631 
632   switch (Opcode) {
633   default: {
634     if (MI.getParent() && MI.getParent()->getParent()) {
635       const auto MF = MI.getMF();
636       const auto &TM = static_cast<const RISCVTargetMachine &>(MF->getTarget());
637       const MCRegisterInfo &MRI = *TM.getMCRegisterInfo();
638       const MCSubtargetInfo &STI = *TM.getMCSubtargetInfo();
639       const RISCVSubtarget &ST = MF->getSubtarget<RISCVSubtarget>();
640       if (isCompressibleInst(MI, &ST, MRI, STI))
641         return 2;
642     }
643     return get(Opcode).getSize();
644   }
645   case TargetOpcode::EH_LABEL:
646   case TargetOpcode::IMPLICIT_DEF:
647   case TargetOpcode::KILL:
648   case TargetOpcode::DBG_VALUE:
649     return 0;
650   // These values are determined based on RISCVExpandAtomicPseudoInsts,
651   // RISCVExpandPseudoInsts and RISCVMCCodeEmitter, depending on where the
652   // pseudos are expanded.
653   case RISCV::PseudoCALLReg:
654   case RISCV::PseudoCALL:
655   case RISCV::PseudoJump:
656   case RISCV::PseudoTAIL:
657   case RISCV::PseudoLLA:
658   case RISCV::PseudoLA:
659   case RISCV::PseudoLA_TLS_IE:
660   case RISCV::PseudoLA_TLS_GD:
661     return 8;
662   case RISCV::PseudoAtomicLoadNand32:
663   case RISCV::PseudoAtomicLoadNand64:
664     return 20;
665   case RISCV::PseudoMaskedAtomicSwap32:
666   case RISCV::PseudoMaskedAtomicLoadAdd32:
667   case RISCV::PseudoMaskedAtomicLoadSub32:
668     return 28;
669   case RISCV::PseudoMaskedAtomicLoadNand32:
670     return 32;
671   case RISCV::PseudoMaskedAtomicLoadMax32:
672   case RISCV::PseudoMaskedAtomicLoadMin32:
673     return 44;
674   case RISCV::PseudoMaskedAtomicLoadUMax32:
675   case RISCV::PseudoMaskedAtomicLoadUMin32:
676     return 36;
677   case RISCV::PseudoCmpXchg32:
678   case RISCV::PseudoCmpXchg64:
679     return 16;
680   case RISCV::PseudoMaskedCmpXchg32:
681     return 32;
682   case TargetOpcode::INLINEASM:
683   case TargetOpcode::INLINEASM_BR: {
684     const MachineFunction &MF = *MI.getParent()->getParent();
685     const auto &TM = static_cast<const RISCVTargetMachine &>(MF.getTarget());
686     return getInlineAsmLength(MI.getOperand(0).getSymbolName(),
687                               *TM.getMCAsmInfo());
688   }
689   }
690 }
691 
692 bool RISCVInstrInfo::isAsCheapAsAMove(const MachineInstr &MI) const {
693   const unsigned Opcode = MI.getOpcode();
694   switch (Opcode) {
695   default:
696     break;
697   case RISCV::FSGNJ_D:
698   case RISCV::FSGNJ_S:
699     // The canonical floating-point move is fsgnj rd, rs, rs.
700     return MI.getOperand(1).isReg() && MI.getOperand(2).isReg() &&
701            MI.getOperand(1).getReg() == MI.getOperand(2).getReg();
702   case RISCV::ADDI:
703   case RISCV::ORI:
704   case RISCV::XORI:
705     return (MI.getOperand(1).isReg() &&
706             MI.getOperand(1).getReg() == RISCV::X0) ||
707            (MI.getOperand(2).isImm() && MI.getOperand(2).getImm() == 0);
708   }
709   return MI.isAsCheapAsAMove();
710 }
711 
712 Optional<DestSourcePair>
713 RISCVInstrInfo::isCopyInstrImpl(const MachineInstr &MI) const {
714   if (MI.isMoveReg())
715     return DestSourcePair{MI.getOperand(0), MI.getOperand(1)};
716   switch (MI.getOpcode()) {
717   default:
718     break;
719   case RISCV::ADDI:
720     // Operand 1 can be a frameindex but callers expect registers
721     if (MI.getOperand(1).isReg() && MI.getOperand(2).isImm() &&
722         MI.getOperand(2).getImm() == 0)
723       return DestSourcePair{MI.getOperand(0), MI.getOperand(1)};
724     break;
725   case RISCV::FSGNJ_D:
726   case RISCV::FSGNJ_S:
727     // The canonical floating-point move is fsgnj rd, rs, rs.
728     if (MI.getOperand(1).isReg() && MI.getOperand(2).isReg() &&
729         MI.getOperand(1).getReg() == MI.getOperand(2).getReg())
730       return DestSourcePair{MI.getOperand(0), MI.getOperand(1)};
731     break;
732   }
733   return None;
734 }
735 
736 bool RISCVInstrInfo::verifyInstruction(const MachineInstr &MI,
737                                        StringRef &ErrInfo) const {
738   const MCInstrInfo *MCII = STI.getInstrInfo();
739   MCInstrDesc const &Desc = MCII->get(MI.getOpcode());
740 
741   for (auto &OI : enumerate(Desc.operands())) {
742     unsigned OpType = OI.value().OperandType;
743     if (OpType >= RISCVOp::OPERAND_FIRST_RISCV_IMM &&
744         OpType <= RISCVOp::OPERAND_LAST_RISCV_IMM) {
745       const MachineOperand &MO = MI.getOperand(OI.index());
746       if (MO.isImm()) {
747         int64_t Imm = MO.getImm();
748         bool Ok;
749         switch (OpType) {
750         default:
751           llvm_unreachable("Unexpected operand type");
752         case RISCVOp::OPERAND_UIMM4:
753           Ok = isUInt<4>(Imm);
754           break;
755         case RISCVOp::OPERAND_UIMM5:
756           Ok = isUInt<5>(Imm);
757           break;
758         case RISCVOp::OPERAND_UIMM12:
759           Ok = isUInt<12>(Imm);
760           break;
761         case RISCVOp::OPERAND_SIMM12:
762           Ok = isInt<12>(Imm);
763           break;
764         case RISCVOp::OPERAND_UIMM20:
765           Ok = isUInt<20>(Imm);
766           break;
767         case RISCVOp::OPERAND_UIMMLOG2XLEN:
768           if (STI.getTargetTriple().isArch64Bit())
769             Ok = isUInt<6>(Imm);
770           else
771             Ok = isUInt<5>(Imm);
772           break;
773         }
774         if (!Ok) {
775           ErrInfo = "Invalid immediate";
776           return false;
777         }
778       }
779     }
780   }
781 
782   return true;
783 }
784 
785 // Return true if get the base operand, byte offset of an instruction and the
786 // memory width. Width is the size of memory that is being loaded/stored.
787 bool RISCVInstrInfo::getMemOperandWithOffsetWidth(
788     const MachineInstr &LdSt, const MachineOperand *&BaseReg, int64_t &Offset,
789     unsigned &Width, const TargetRegisterInfo *TRI) const {
790   if (!LdSt.mayLoadOrStore())
791     return false;
792 
793   // Here we assume the standard RISC-V ISA, which uses a base+offset
794   // addressing mode. You'll need to relax these conditions to support custom
795   // load/stores instructions.
796   if (LdSt.getNumExplicitOperands() != 3)
797     return false;
798   if (!LdSt.getOperand(1).isReg() || !LdSt.getOperand(2).isImm())
799     return false;
800 
801   if (!LdSt.hasOneMemOperand())
802     return false;
803 
804   Width = (*LdSt.memoperands_begin())->getSize();
805   BaseReg = &LdSt.getOperand(1);
806   Offset = LdSt.getOperand(2).getImm();
807   return true;
808 }
809 
810 bool RISCVInstrInfo::areMemAccessesTriviallyDisjoint(
811     const MachineInstr &MIa, const MachineInstr &MIb) const {
812   assert(MIa.mayLoadOrStore() && "MIa must be a load or store.");
813   assert(MIb.mayLoadOrStore() && "MIb must be a load or store.");
814 
815   if (MIa.hasUnmodeledSideEffects() || MIb.hasUnmodeledSideEffects() ||
816       MIa.hasOrderedMemoryRef() || MIb.hasOrderedMemoryRef())
817     return false;
818 
819   // Retrieve the base register, offset from the base register and width. Width
820   // is the size of memory that is being loaded/stored (e.g. 1, 2, 4).  If
821   // base registers are identical, and the offset of a lower memory access +
822   // the width doesn't overlap the offset of a higher memory access,
823   // then the memory accesses are different.
824   const TargetRegisterInfo *TRI = STI.getRegisterInfo();
825   const MachineOperand *BaseOpA = nullptr, *BaseOpB = nullptr;
826   int64_t OffsetA = 0, OffsetB = 0;
827   unsigned int WidthA = 0, WidthB = 0;
828   if (getMemOperandWithOffsetWidth(MIa, BaseOpA, OffsetA, WidthA, TRI) &&
829       getMemOperandWithOffsetWidth(MIb, BaseOpB, OffsetB, WidthB, TRI)) {
830     if (BaseOpA->isIdenticalTo(*BaseOpB)) {
831       int LowOffset = std::min(OffsetA, OffsetB);
832       int HighOffset = std::max(OffsetA, OffsetB);
833       int LowWidth = (LowOffset == OffsetA) ? WidthA : WidthB;
834       if (LowOffset + LowWidth <= HighOffset)
835         return true;
836     }
837   }
838   return false;
839 }
840 
841 std::pair<unsigned, unsigned>
842 RISCVInstrInfo::decomposeMachineOperandsTargetFlags(unsigned TF) const {
843   const unsigned Mask = RISCVII::MO_DIRECT_FLAG_MASK;
844   return std::make_pair(TF & Mask, TF & ~Mask);
845 }
846 
847 ArrayRef<std::pair<unsigned, const char *>>
848 RISCVInstrInfo::getSerializableDirectMachineOperandTargetFlags() const {
849   using namespace RISCVII;
850   static const std::pair<unsigned, const char *> TargetFlags[] = {
851       {MO_CALL, "riscv-call"},
852       {MO_PLT, "riscv-plt"},
853       {MO_LO, "riscv-lo"},
854       {MO_HI, "riscv-hi"},
855       {MO_PCREL_LO, "riscv-pcrel-lo"},
856       {MO_PCREL_HI, "riscv-pcrel-hi"},
857       {MO_GOT_HI, "riscv-got-hi"},
858       {MO_TPREL_LO, "riscv-tprel-lo"},
859       {MO_TPREL_HI, "riscv-tprel-hi"},
860       {MO_TPREL_ADD, "riscv-tprel-add"},
861       {MO_TLS_GOT_HI, "riscv-tls-got-hi"},
862       {MO_TLS_GD_HI, "riscv-tls-gd-hi"}};
863   return makeArrayRef(TargetFlags);
864 }
865 bool RISCVInstrInfo::isFunctionSafeToOutlineFrom(
866     MachineFunction &MF, bool OutlineFromLinkOnceODRs) const {
867   const Function &F = MF.getFunction();
868 
869   // Can F be deduplicated by the linker? If it can, don't outline from it.
870   if (!OutlineFromLinkOnceODRs && F.hasLinkOnceODRLinkage())
871     return false;
872 
873   // Don't outline from functions with section markings; the program could
874   // expect that all the code is in the named section.
875   if (F.hasSection())
876     return false;
877 
878   // It's safe to outline from MF.
879   return true;
880 }
881 
882 bool RISCVInstrInfo::isMBBSafeToOutlineFrom(MachineBasicBlock &MBB,
883                                             unsigned &Flags) const {
884   // More accurate safety checking is done in getOutliningCandidateInfo.
885   return true;
886 }
887 
888 // Enum values indicating how an outlined call should be constructed.
889 enum MachineOutlinerConstructionID {
890   MachineOutlinerDefault
891 };
892 
893 outliner::OutlinedFunction RISCVInstrInfo::getOutliningCandidateInfo(
894     std::vector<outliner::Candidate> &RepeatedSequenceLocs) const {
895 
896   // First we need to filter out candidates where the X5 register (IE t0) can't
897   // be used to setup the function call.
898   auto CannotInsertCall = [](outliner::Candidate &C) {
899     const TargetRegisterInfo *TRI = C.getMF()->getSubtarget().getRegisterInfo();
900 
901     C.initLRU(*TRI);
902     LiveRegUnits LRU = C.LRU;
903     return !LRU.available(RISCV::X5);
904   };
905 
906   llvm::erase_if(RepeatedSequenceLocs, CannotInsertCall);
907 
908   // If the sequence doesn't have enough candidates left, then we're done.
909   if (RepeatedSequenceLocs.size() < 2)
910     return outliner::OutlinedFunction();
911 
912   unsigned SequenceSize = 0;
913 
914   auto I = RepeatedSequenceLocs[0].front();
915   auto E = std::next(RepeatedSequenceLocs[0].back());
916   for (; I != E; ++I)
917     SequenceSize += getInstSizeInBytes(*I);
918 
919   // call t0, function = 8 bytes.
920   unsigned CallOverhead = 8;
921   for (auto &C : RepeatedSequenceLocs)
922     C.setCallInfo(MachineOutlinerDefault, CallOverhead);
923 
924   // jr t0 = 4 bytes, 2 bytes if compressed instructions are enabled.
925   unsigned FrameOverhead = 4;
926   if (RepeatedSequenceLocs[0].getMF()->getSubtarget()
927           .getFeatureBits()[RISCV::FeatureStdExtC])
928     FrameOverhead = 2;
929 
930   return outliner::OutlinedFunction(RepeatedSequenceLocs, SequenceSize,
931                                     FrameOverhead, MachineOutlinerDefault);
932 }
933 
934 outliner::InstrType
935 RISCVInstrInfo::getOutliningType(MachineBasicBlock::iterator &MBBI,
936                                  unsigned Flags) const {
937   MachineInstr &MI = *MBBI;
938   MachineBasicBlock *MBB = MI.getParent();
939   const TargetRegisterInfo *TRI =
940       MBB->getParent()->getSubtarget().getRegisterInfo();
941 
942   // Positions generally can't safely be outlined.
943   if (MI.isPosition()) {
944     // We can manually strip out CFI instructions later.
945     if (MI.isCFIInstruction())
946       return outliner::InstrType::Invisible;
947 
948     return outliner::InstrType::Illegal;
949   }
950 
951   // Don't trust the user to write safe inline assembly.
952   if (MI.isInlineAsm())
953     return outliner::InstrType::Illegal;
954 
955   // We can't outline branches to other basic blocks.
956   if (MI.isTerminator() && !MBB->succ_empty())
957     return outliner::InstrType::Illegal;
958 
959   // We need support for tail calls to outlined functions before return
960   // statements can be allowed.
961   if (MI.isReturn())
962     return outliner::InstrType::Illegal;
963 
964   // Don't allow modifying the X5 register which we use for return addresses for
965   // these outlined functions.
966   if (MI.modifiesRegister(RISCV::X5, TRI) ||
967       MI.getDesc().hasImplicitDefOfPhysReg(RISCV::X5))
968     return outliner::InstrType::Illegal;
969 
970   // Make sure the operands don't reference something unsafe.
971   for (const auto &MO : MI.operands())
972     if (MO.isMBB() || MO.isBlockAddress() || MO.isCPI())
973       return outliner::InstrType::Illegal;
974 
975   // Don't allow instructions which won't be materialized to impact outlining
976   // analysis.
977   if (MI.isMetaInstruction())
978     return outliner::InstrType::Invisible;
979 
980   return outliner::InstrType::Legal;
981 }
982 
983 void RISCVInstrInfo::buildOutlinedFrame(
984     MachineBasicBlock &MBB, MachineFunction &MF,
985     const outliner::OutlinedFunction &OF) const {
986 
987   // Strip out any CFI instructions
988   bool Changed = true;
989   while (Changed) {
990     Changed = false;
991     auto I = MBB.begin();
992     auto E = MBB.end();
993     for (; I != E; ++I) {
994       if (I->isCFIInstruction()) {
995         I->removeFromParent();
996         Changed = true;
997         break;
998       }
999     }
1000   }
1001 
1002   MBB.addLiveIn(RISCV::X5);
1003 
1004   // Add in a return instruction to the end of the outlined frame.
1005   MBB.insert(MBB.end(), BuildMI(MF, DebugLoc(), get(RISCV::JALR))
1006       .addReg(RISCV::X0, RegState::Define)
1007       .addReg(RISCV::X5)
1008       .addImm(0));
1009 }
1010 
1011 MachineBasicBlock::iterator RISCVInstrInfo::insertOutlinedCall(
1012     Module &M, MachineBasicBlock &MBB, MachineBasicBlock::iterator &It,
1013     MachineFunction &MF, const outliner::Candidate &C) const {
1014 
1015   // Add in a call instruction to the outlined function at the given location.
1016   It = MBB.insert(It,
1017                   BuildMI(MF, DebugLoc(), get(RISCV::PseudoCALLReg), RISCV::X5)
1018                       .addGlobalAddress(M.getNamedValue(MF.getName()), 0,
1019                                         RISCVII::MO_CALL));
1020   return It;
1021 }
1022 
1023 // clang-format off
1024 #define CASE_VFMA_OPCODE_COMMON(OP, TYPE, LMUL)                                \
1025   RISCV::PseudoV##OP##_##TYPE##_##LMUL##_COMMUTABLE
1026 
1027 #define CASE_VFMA_OPCODE_LMULS(OP, TYPE)                                       \
1028   CASE_VFMA_OPCODE_COMMON(OP, TYPE, MF8):                                      \
1029   case CASE_VFMA_OPCODE_COMMON(OP, TYPE, MF4):                                 \
1030   case CASE_VFMA_OPCODE_COMMON(OP, TYPE, MF2):                                 \
1031   case CASE_VFMA_OPCODE_COMMON(OP, TYPE, M1):                                  \
1032   case CASE_VFMA_OPCODE_COMMON(OP, TYPE, M2):                                  \
1033   case CASE_VFMA_OPCODE_COMMON(OP, TYPE, M4):                                  \
1034   case CASE_VFMA_OPCODE_COMMON(OP, TYPE, M8)
1035 
1036 #define CASE_VFMA_SPLATS(OP)                                                   \
1037   CASE_VFMA_OPCODE_LMULS(OP, VF16):                                            \
1038   case CASE_VFMA_OPCODE_LMULS(OP, VF32):                                       \
1039   case CASE_VFMA_OPCODE_LMULS(OP, VF64)
1040 // clang-format on
1041 
1042 bool RISCVInstrInfo::findCommutedOpIndices(const MachineInstr &MI,
1043                                            unsigned &SrcOpIdx1,
1044                                            unsigned &SrcOpIdx2) const {
1045   const MCInstrDesc &Desc = MI.getDesc();
1046   if (!Desc.isCommutable())
1047     return false;
1048 
1049   switch (MI.getOpcode()) {
1050   case CASE_VFMA_SPLATS(FMADD):
1051   case CASE_VFMA_SPLATS(FMSUB):
1052   case CASE_VFMA_SPLATS(FMACC):
1053   case CASE_VFMA_SPLATS(FMSAC):
1054   case CASE_VFMA_SPLATS(FNMADD):
1055   case CASE_VFMA_SPLATS(FNMSUB):
1056   case CASE_VFMA_SPLATS(FNMACC):
1057   case CASE_VFMA_SPLATS(FNMSAC):
1058   case CASE_VFMA_OPCODE_LMULS(FMACC, VV):
1059   case CASE_VFMA_OPCODE_LMULS(FMSAC, VV):
1060   case CASE_VFMA_OPCODE_LMULS(FNMACC, VV):
1061   case CASE_VFMA_OPCODE_LMULS(FNMSAC, VV): {
1062     // For these instructions we can only swap operand 1 and operand 3 by
1063     // changing the opcode.
1064     unsigned CommutableOpIdx1 = 1;
1065     unsigned CommutableOpIdx2 = 3;
1066     if (!fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2, CommutableOpIdx1,
1067                               CommutableOpIdx2))
1068       return false;
1069     return true;
1070   }
1071   case CASE_VFMA_OPCODE_LMULS(FMADD, VV):
1072   case CASE_VFMA_OPCODE_LMULS(FMSUB, VV):
1073   case CASE_VFMA_OPCODE_LMULS(FNMADD, VV):
1074   case CASE_VFMA_OPCODE_LMULS(FNMSUB, VV): {
1075     // For these instructions we have more freedom. We can commute with the
1076     // other multiplicand or with the addend/subtrahend/minuend.
1077 
1078     // Any fixed operand must be from source 1, 2 or 3.
1079     if (SrcOpIdx1 != CommuteAnyOperandIndex && SrcOpIdx1 > 3)
1080       return false;
1081     if (SrcOpIdx2 != CommuteAnyOperandIndex && SrcOpIdx2 > 3)
1082       return false;
1083 
1084     // It both ops are fixed one must be the tied source.
1085     if (SrcOpIdx1 != CommuteAnyOperandIndex &&
1086         SrcOpIdx2 != CommuteAnyOperandIndex && SrcOpIdx1 != 1 && SrcOpIdx2 != 1)
1087       return false;
1088 
1089     // Look for two different register operands assumed to be commutable
1090     // regardless of the FMA opcode. The FMA opcode is adjusted later if
1091     // needed.
1092     if (SrcOpIdx1 == CommuteAnyOperandIndex ||
1093         SrcOpIdx2 == CommuteAnyOperandIndex) {
1094       // At least one of operands to be commuted is not specified and
1095       // this method is free to choose appropriate commutable operands.
1096       unsigned CommutableOpIdx1 = SrcOpIdx1;
1097       if (SrcOpIdx1 == SrcOpIdx2) {
1098         // Both of operands are not fixed. Set one of commutable
1099         // operands to the tied source.
1100         CommutableOpIdx1 = 1;
1101       } else if (SrcOpIdx1 == CommutableOpIdx1) {
1102         // Only one of the operands is not fixed.
1103         CommutableOpIdx1 = SrcOpIdx2;
1104       }
1105 
1106       // CommutableOpIdx1 is well defined now. Let's choose another commutable
1107       // operand and assign its index to CommutableOpIdx2.
1108       unsigned CommutableOpIdx2;
1109       if (CommutableOpIdx1 != 1) {
1110         // If we haven't already used the tied source, we must use it now.
1111         CommutableOpIdx2 = 1;
1112       } else {
1113         Register Op1Reg = MI.getOperand(CommutableOpIdx1).getReg();
1114 
1115         // The commuted operands should have different registers.
1116         // Otherwise, the commute transformation does not change anything and
1117         // is useless. We use this as a hint to make our decision.
1118         if (Op1Reg != MI.getOperand(2).getReg())
1119           CommutableOpIdx2 = 2;
1120         else
1121           CommutableOpIdx2 = 3;
1122       }
1123 
1124       // Assign the found pair of commutable indices to SrcOpIdx1 and
1125       // SrcOpIdx2 to return those values.
1126       if (!fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2, CommutableOpIdx1,
1127                                 CommutableOpIdx2))
1128         return false;
1129     }
1130 
1131     return true;
1132   }
1133   }
1134 
1135   return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
1136 }
1137 
1138 #define CASE_VFMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, LMUL)               \
1139   case RISCV::PseudoV##OLDOP##_##TYPE##_##LMUL##_COMMUTABLE:                   \
1140     Opc = RISCV::PseudoV##NEWOP##_##TYPE##_##LMUL##_COMMUTABLE;                \
1141     break;
1142 
1143 #define CASE_VFMA_CHANGE_OPCODE_LMULS(OLDOP, NEWOP, TYPE)                      \
1144   CASE_VFMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, MF8)                      \
1145   CASE_VFMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, MF4)                      \
1146   CASE_VFMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, MF2)                      \
1147   CASE_VFMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, M1)                       \
1148   CASE_VFMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, M2)                       \
1149   CASE_VFMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, M4)                       \
1150   CASE_VFMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, M8)
1151 
1152 #define CASE_VFMA_CHANGE_OPCODE_SPLATS(OLDOP, NEWOP)                           \
1153   CASE_VFMA_CHANGE_OPCODE_LMULS(OLDOP, NEWOP, VF16)                            \
1154   CASE_VFMA_CHANGE_OPCODE_LMULS(OLDOP, NEWOP, VF32)                            \
1155   CASE_VFMA_CHANGE_OPCODE_LMULS(OLDOP, NEWOP, VF64)
1156 
1157 MachineInstr *RISCVInstrInfo::commuteInstructionImpl(MachineInstr &MI,
1158                                                      bool NewMI,
1159                                                      unsigned OpIdx1,
1160                                                      unsigned OpIdx2) const {
1161   auto cloneIfNew = [NewMI](MachineInstr &MI) -> MachineInstr & {
1162     if (NewMI)
1163       return *MI.getParent()->getParent()->CloneMachineInstr(&MI);
1164     return MI;
1165   };
1166 
1167   switch (MI.getOpcode()) {
1168   case CASE_VFMA_SPLATS(FMACC):
1169   case CASE_VFMA_SPLATS(FMADD):
1170   case CASE_VFMA_SPLATS(FMSAC):
1171   case CASE_VFMA_SPLATS(FMSUB):
1172   case CASE_VFMA_SPLATS(FNMACC):
1173   case CASE_VFMA_SPLATS(FNMADD):
1174   case CASE_VFMA_SPLATS(FNMSAC):
1175   case CASE_VFMA_SPLATS(FNMSUB):
1176   case CASE_VFMA_OPCODE_LMULS(FMACC, VV):
1177   case CASE_VFMA_OPCODE_LMULS(FMSAC, VV):
1178   case CASE_VFMA_OPCODE_LMULS(FNMACC, VV):
1179   case CASE_VFMA_OPCODE_LMULS(FNMSAC, VV): {
1180     // It only make sense to toggle these between clobbering the
1181     // addend/subtrahend/minuend one of the multiplicands.
1182     assert((OpIdx1 == 1 || OpIdx2 == 1) && "Unexpected opcode index");
1183     assert((OpIdx1 == 3 || OpIdx2 == 3) && "Unexpected opcode index");
1184     unsigned Opc;
1185     switch (MI.getOpcode()) {
1186       default:
1187         llvm_unreachable("Unexpected opcode");
1188       CASE_VFMA_CHANGE_OPCODE_SPLATS(FMACC, FMADD)
1189       CASE_VFMA_CHANGE_OPCODE_SPLATS(FMADD, FMACC)
1190       CASE_VFMA_CHANGE_OPCODE_SPLATS(FMSAC, FMSUB)
1191       CASE_VFMA_CHANGE_OPCODE_SPLATS(FMSUB, FMSAC)
1192       CASE_VFMA_CHANGE_OPCODE_SPLATS(FNMACC, FNMADD)
1193       CASE_VFMA_CHANGE_OPCODE_SPLATS(FNMADD, FNMACC)
1194       CASE_VFMA_CHANGE_OPCODE_SPLATS(FNMSAC, FNMSUB)
1195       CASE_VFMA_CHANGE_OPCODE_SPLATS(FNMSUB, FNMSAC)
1196       CASE_VFMA_CHANGE_OPCODE_LMULS(FMACC, FMADD, VV)
1197       CASE_VFMA_CHANGE_OPCODE_LMULS(FMSAC, FMSUB, VV)
1198       CASE_VFMA_CHANGE_OPCODE_LMULS(FNMACC, FNMADD, VV)
1199       CASE_VFMA_CHANGE_OPCODE_LMULS(FNMSAC, FNMSUB, VV)
1200     }
1201 
1202     auto &WorkingMI = cloneIfNew(MI);
1203     WorkingMI.setDesc(get(Opc));
1204     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
1205                                                    OpIdx1, OpIdx2);
1206   }
1207   case CASE_VFMA_OPCODE_LMULS(FMADD, VV):
1208   case CASE_VFMA_OPCODE_LMULS(FMSUB, VV):
1209   case CASE_VFMA_OPCODE_LMULS(FNMADD, VV):
1210   case CASE_VFMA_OPCODE_LMULS(FNMSUB, VV): {
1211     assert((OpIdx1 == 1 || OpIdx2 == 1) && "Unexpected opcode index");
1212     // If one of the operands, is the addend we need to change opcode.
1213     // Otherwise we're just swapping 2 of the multiplicands.
1214     if (OpIdx1 == 3 || OpIdx2 == 3) {
1215       unsigned Opc;
1216       switch (MI.getOpcode()) {
1217         default:
1218           llvm_unreachable("Unexpected opcode");
1219         CASE_VFMA_CHANGE_OPCODE_LMULS(FMADD, FMACC, VV)
1220         CASE_VFMA_CHANGE_OPCODE_LMULS(FMSUB, FMSAC, VV)
1221         CASE_VFMA_CHANGE_OPCODE_LMULS(FNMADD, FNMACC, VV)
1222         CASE_VFMA_CHANGE_OPCODE_LMULS(FNMSUB, FNMSAC, VV)
1223       }
1224 
1225       auto &WorkingMI = cloneIfNew(MI);
1226       WorkingMI.setDesc(get(Opc));
1227       return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
1228                                                      OpIdx1, OpIdx2);
1229     }
1230     // Let the default code handle it.
1231     break;
1232   }
1233   }
1234 
1235   return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
1236 }
1237 
1238 #undef CASE_VFMA_CHANGE_OPCODE_SPLATS
1239 #undef CASE_VFMA_CHANGE_OPCODE_LMULS
1240 #undef CASE_VFMA_CHANGE_OPCODE_COMMON
1241 #undef CASE_VFMA_SPLATS
1242 #undef CASE_VFMA_OPCODE_LMULS
1243 #undef CASE_VFMA_OPCODE_COMMON
1244 
1245 Register RISCVInstrInfo::getVLENFactoredAmount(MachineFunction &MF,
1246                                                MachineBasicBlock &MBB,
1247                                                MachineBasicBlock::iterator II,
1248                                                int64_t Amount) const {
1249   assert(Amount > 0 && "There is no need to get VLEN scaled value.");
1250   assert(Amount % 8 == 0 &&
1251          "Reserve the stack by the multiple of one vector size.");
1252 
1253   MachineRegisterInfo &MRI = MF.getRegInfo();
1254   const RISCVInstrInfo *TII = MF.getSubtarget<RISCVSubtarget>().getInstrInfo();
1255   DebugLoc DL = II->getDebugLoc();
1256   int64_t NumOfVReg = Amount / 8;
1257 
1258   Register SizeOfVector = MRI.createVirtualRegister(&RISCV::GPRRegClass);
1259   BuildMI(MBB, II, DL, TII->get(RISCV::PseudoReadVLENB), SizeOfVector);
1260   Register FactorRegister = MRI.createVirtualRegister(&RISCV::GPRRegClass);
1261   assert(isInt<12>(NumOfVReg) &&
1262          "Expect the number of vector registers within 12-bits.");
1263   if (isPowerOf2_32(NumOfVReg)) {
1264     uint32_t ShiftAmount = Log2_32(NumOfVReg);
1265     if (ShiftAmount == 0)
1266       return SizeOfVector;
1267     BuildMI(MBB, II, DL, TII->get(RISCV::SLLI), FactorRegister)
1268         .addReg(SizeOfVector, RegState::Kill)
1269         .addImm(ShiftAmount);
1270   } else {
1271     Register VN = MRI.createVirtualRegister(&RISCV::GPRRegClass);
1272     BuildMI(MBB, II, DL, TII->get(RISCV::ADDI), VN)
1273         .addReg(RISCV::X0)
1274         .addImm(NumOfVReg);
1275     if (!MF.getSubtarget<RISCVSubtarget>().hasStdExtM())
1276       MF.getFunction().getContext().diagnose(DiagnosticInfoUnsupported{
1277           MF.getFunction(),
1278           "M-extension must be enabled to calculate the vscaled size/offset."});
1279     BuildMI(MBB, II, DL, TII->get(RISCV::MUL), FactorRegister)
1280         .addReg(SizeOfVector, RegState::Kill)
1281         .addReg(VN, RegState::Kill);
1282   }
1283 
1284   return FactorRegister;
1285 }
1286 
1287 Optional<std::pair<unsigned, unsigned>>
1288 RISCVInstrInfo::isRVVSpillForZvlsseg(unsigned Opcode) const {
1289   switch (Opcode) {
1290   default:
1291     return None;
1292   case RISCV::PseudoVSPILL2_M1:
1293   case RISCV::PseudoVRELOAD2_M1:
1294     return std::make_pair(2u, 1u);
1295   case RISCV::PseudoVSPILL2_M2:
1296   case RISCV::PseudoVRELOAD2_M2:
1297     return std::make_pair(2u, 2u);
1298   case RISCV::PseudoVSPILL2_M4:
1299   case RISCV::PseudoVRELOAD2_M4:
1300     return std::make_pair(2u, 4u);
1301   case RISCV::PseudoVSPILL3_M1:
1302   case RISCV::PseudoVRELOAD3_M1:
1303     return std::make_pair(3u, 1u);
1304   case RISCV::PseudoVSPILL3_M2:
1305   case RISCV::PseudoVRELOAD3_M2:
1306     return std::make_pair(3u, 2u);
1307   case RISCV::PseudoVSPILL4_M1:
1308   case RISCV::PseudoVRELOAD4_M1:
1309     return std::make_pair(4u, 1u);
1310   case RISCV::PseudoVSPILL4_M2:
1311   case RISCV::PseudoVRELOAD4_M2:
1312     return std::make_pair(4u, 2u);
1313   case RISCV::PseudoVSPILL5_M1:
1314   case RISCV::PseudoVRELOAD5_M1:
1315     return std::make_pair(5u, 1u);
1316   case RISCV::PseudoVSPILL6_M1:
1317   case RISCV::PseudoVRELOAD6_M1:
1318     return std::make_pair(6u, 1u);
1319   case RISCV::PseudoVSPILL7_M1:
1320   case RISCV::PseudoVRELOAD7_M1:
1321     return std::make_pair(7u, 1u);
1322   case RISCV::PseudoVSPILL8_M1:
1323   case RISCV::PseudoVRELOAD8_M1:
1324     return std::make_pair(8u, 1u);
1325   }
1326 }
1327