1 //===-- RISCVInstrInfo.cpp - RISCV Instruction Information ------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the RISCV implementation of the TargetInstrInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "RISCVInstrInfo.h"
14 #include "RISCV.h"
15 #include "RISCVSubtarget.h"
16 #include "RISCVTargetMachine.h"
17 #include "Utils/RISCVMatInt.h"
18 #include "llvm/ADT/STLExtras.h"
19 #include "llvm/ADT/SmallVector.h"
20 #include "llvm/CodeGen/MachineFunctionPass.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/CodeGen/RegisterScavenging.h"
24 #include "llvm/Support/ErrorHandling.h"
25 #include "llvm/Support/TargetRegistry.h"
26 
27 using namespace llvm;
28 
29 #define GEN_CHECK_COMPRESS_INSTR
30 #include "RISCVGenCompressInstEmitter.inc"
31 
32 #define GET_INSTRINFO_CTOR_DTOR
33 #include "RISCVGenInstrInfo.inc"
34 
35 RISCVInstrInfo::RISCVInstrInfo(RISCVSubtarget &STI)
36     : RISCVGenInstrInfo(RISCV::ADJCALLSTACKDOWN, RISCV::ADJCALLSTACKUP),
37       STI(STI) {}
38 
39 unsigned RISCVInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
40                                              int &FrameIndex) const {
41   switch (MI.getOpcode()) {
42   default:
43     return 0;
44   case RISCV::LB:
45   case RISCV::LBU:
46   case RISCV::LH:
47   case RISCV::LHU:
48   case RISCV::FLH:
49   case RISCV::LW:
50   case RISCV::FLW:
51   case RISCV::LWU:
52   case RISCV::LD:
53   case RISCV::FLD:
54     break;
55   }
56 
57   if (MI.getOperand(1).isFI() && MI.getOperand(2).isImm() &&
58       MI.getOperand(2).getImm() == 0) {
59     FrameIndex = MI.getOperand(1).getIndex();
60     return MI.getOperand(0).getReg();
61   }
62 
63   return 0;
64 }
65 
66 unsigned RISCVInstrInfo::isStoreToStackSlot(const MachineInstr &MI,
67                                             int &FrameIndex) const {
68   switch (MI.getOpcode()) {
69   default:
70     return 0;
71   case RISCV::SB:
72   case RISCV::SH:
73   case RISCV::SW:
74   case RISCV::FSH:
75   case RISCV::FSW:
76   case RISCV::SD:
77   case RISCV::FSD:
78     break;
79   }
80 
81   if (MI.getOperand(1).isFI() && MI.getOperand(2).isImm() &&
82       MI.getOperand(2).getImm() == 0) {
83     FrameIndex = MI.getOperand(1).getIndex();
84     return MI.getOperand(0).getReg();
85   }
86 
87   return 0;
88 }
89 
90 void RISCVInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
91                                  MachineBasicBlock::iterator MBBI,
92                                  const DebugLoc &DL, MCRegister DstReg,
93                                  MCRegister SrcReg, bool KillSrc) const {
94   if (RISCV::GPRRegClass.contains(DstReg, SrcReg)) {
95     BuildMI(MBB, MBBI, DL, get(RISCV::ADDI), DstReg)
96         .addReg(SrcReg, getKillRegState(KillSrc))
97         .addImm(0);
98     return;
99   }
100 
101   // FPR->FPR copies
102   unsigned Opc;
103   if (RISCV::FPR16RegClass.contains(DstReg, SrcReg))
104     Opc = RISCV::FSGNJ_H;
105   else if (RISCV::FPR32RegClass.contains(DstReg, SrcReg))
106     Opc = RISCV::FSGNJ_S;
107   else if (RISCV::FPR64RegClass.contains(DstReg, SrcReg))
108     Opc = RISCV::FSGNJ_D;
109   else
110     llvm_unreachable("Impossible reg-to-reg copy");
111 
112   BuildMI(MBB, MBBI, DL, get(Opc), DstReg)
113       .addReg(SrcReg, getKillRegState(KillSrc))
114       .addReg(SrcReg, getKillRegState(KillSrc));
115 }
116 
117 void RISCVInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
118                                          MachineBasicBlock::iterator I,
119                                          Register SrcReg, bool IsKill, int FI,
120                                          const TargetRegisterClass *RC,
121                                          const TargetRegisterInfo *TRI) const {
122   DebugLoc DL;
123   if (I != MBB.end())
124     DL = I->getDebugLoc();
125 
126   MachineFunction *MF = MBB.getParent();
127   const MachineFrameInfo &MFI = MF->getFrameInfo();
128   MachineMemOperand *MMO = MF->getMachineMemOperand(
129       MachinePointerInfo::getFixedStack(*MF, FI), MachineMemOperand::MOStore,
130       MFI.getObjectSize(FI), MFI.getObjectAlign(FI));
131 
132   unsigned Opcode;
133   if (RISCV::GPRRegClass.hasSubClassEq(RC))
134     Opcode = TRI->getRegSizeInBits(RISCV::GPRRegClass) == 32 ?
135              RISCV::SW : RISCV::SD;
136   else if (RISCV::FPR16RegClass.hasSubClassEq(RC))
137     Opcode = RISCV::FSH;
138   else if (RISCV::FPR32RegClass.hasSubClassEq(RC))
139     Opcode = RISCV::FSW;
140   else if (RISCV::FPR64RegClass.hasSubClassEq(RC))
141     Opcode = RISCV::FSD;
142   else
143     llvm_unreachable("Can't store this register to stack slot");
144 
145   BuildMI(MBB, I, DL, get(Opcode))
146       .addReg(SrcReg, getKillRegState(IsKill))
147       .addFrameIndex(FI)
148       .addImm(0)
149       .addMemOperand(MMO);
150 }
151 
152 void RISCVInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
153                                           MachineBasicBlock::iterator I,
154                                           Register DstReg, int FI,
155                                           const TargetRegisterClass *RC,
156                                           const TargetRegisterInfo *TRI) const {
157   DebugLoc DL;
158   if (I != MBB.end())
159     DL = I->getDebugLoc();
160 
161   MachineFunction *MF = MBB.getParent();
162   const MachineFrameInfo &MFI = MF->getFrameInfo();
163   MachineMemOperand *MMO = MF->getMachineMemOperand(
164       MachinePointerInfo::getFixedStack(*MF, FI), MachineMemOperand::MOLoad,
165       MFI.getObjectSize(FI), MFI.getObjectAlign(FI));
166 
167   unsigned Opcode;
168   if (RISCV::GPRRegClass.hasSubClassEq(RC))
169     Opcode = TRI->getRegSizeInBits(RISCV::GPRRegClass) == 32 ?
170              RISCV::LW : RISCV::LD;
171   else if (RISCV::FPR16RegClass.hasSubClassEq(RC))
172     Opcode = RISCV::FLH;
173   else if (RISCV::FPR32RegClass.hasSubClassEq(RC))
174     Opcode = RISCV::FLW;
175   else if (RISCV::FPR64RegClass.hasSubClassEq(RC))
176     Opcode = RISCV::FLD;
177   else
178     llvm_unreachable("Can't load this register from stack slot");
179 
180   BuildMI(MBB, I, DL, get(Opcode), DstReg)
181     .addFrameIndex(FI)
182     .addImm(0)
183     .addMemOperand(MMO);
184 }
185 
186 void RISCVInstrInfo::movImm(MachineBasicBlock &MBB,
187                             MachineBasicBlock::iterator MBBI,
188                             const DebugLoc &DL, Register DstReg, uint64_t Val,
189                             MachineInstr::MIFlag Flag) const {
190   MachineFunction *MF = MBB.getParent();
191   MachineRegisterInfo &MRI = MF->getRegInfo();
192   bool IsRV64 = MF->getSubtarget<RISCVSubtarget>().is64Bit();
193   Register SrcReg = RISCV::X0;
194   Register Result = MRI.createVirtualRegister(&RISCV::GPRRegClass);
195   unsigned Num = 0;
196 
197   if (!IsRV64 && !isInt<32>(Val))
198     report_fatal_error("Should only materialize 32-bit constants for RV32");
199 
200   RISCVMatInt::InstSeq Seq;
201   RISCVMatInt::generateInstSeq(Val, IsRV64, Seq);
202   assert(Seq.size() > 0);
203 
204   for (RISCVMatInt::Inst &Inst : Seq) {
205     // Write the final result to DstReg if it's the last instruction in the Seq.
206     // Otherwise, write the result to the temp register.
207     if (++Num == Seq.size())
208       Result = DstReg;
209 
210     if (Inst.Opc == RISCV::LUI) {
211       BuildMI(MBB, MBBI, DL, get(RISCV::LUI), Result)
212           .addImm(Inst.Imm)
213           .setMIFlag(Flag);
214     } else {
215       BuildMI(MBB, MBBI, DL, get(Inst.Opc), Result)
216           .addReg(SrcReg, RegState::Kill)
217           .addImm(Inst.Imm)
218           .setMIFlag(Flag);
219     }
220     // Only the first instruction has X0 as its source.
221     SrcReg = Result;
222   }
223 }
224 
225 // The contents of values added to Cond are not examined outside of
226 // RISCVInstrInfo, giving us flexibility in what to push to it. For RISCV, we
227 // push BranchOpcode, Reg1, Reg2.
228 static void parseCondBranch(MachineInstr &LastInst, MachineBasicBlock *&Target,
229                             SmallVectorImpl<MachineOperand> &Cond) {
230   // Block ends with fall-through condbranch.
231   assert(LastInst.getDesc().isConditionalBranch() &&
232          "Unknown conditional branch");
233   Target = LastInst.getOperand(2).getMBB();
234   Cond.push_back(MachineOperand::CreateImm(LastInst.getOpcode()));
235   Cond.push_back(LastInst.getOperand(0));
236   Cond.push_back(LastInst.getOperand(1));
237 }
238 
239 static unsigned getOppositeBranchOpcode(int Opc) {
240   switch (Opc) {
241   default:
242     llvm_unreachable("Unrecognized conditional branch");
243   case RISCV::BEQ:
244     return RISCV::BNE;
245   case RISCV::BNE:
246     return RISCV::BEQ;
247   case RISCV::BLT:
248     return RISCV::BGE;
249   case RISCV::BGE:
250     return RISCV::BLT;
251   case RISCV::BLTU:
252     return RISCV::BGEU;
253   case RISCV::BGEU:
254     return RISCV::BLTU;
255   }
256 }
257 
258 bool RISCVInstrInfo::analyzeBranch(MachineBasicBlock &MBB,
259                                    MachineBasicBlock *&TBB,
260                                    MachineBasicBlock *&FBB,
261                                    SmallVectorImpl<MachineOperand> &Cond,
262                                    bool AllowModify) const {
263   TBB = FBB = nullptr;
264   Cond.clear();
265 
266   // If the block has no terminators, it just falls into the block after it.
267   MachineBasicBlock::iterator I = MBB.getLastNonDebugInstr();
268   if (I == MBB.end() || !isUnpredicatedTerminator(*I))
269     return false;
270 
271   // Count the number of terminators and find the first unconditional or
272   // indirect branch.
273   MachineBasicBlock::iterator FirstUncondOrIndirectBr = MBB.end();
274   int NumTerminators = 0;
275   for (auto J = I.getReverse(); J != MBB.rend() && isUnpredicatedTerminator(*J);
276        J++) {
277     NumTerminators++;
278     if (J->getDesc().isUnconditionalBranch() ||
279         J->getDesc().isIndirectBranch()) {
280       FirstUncondOrIndirectBr = J.getReverse();
281     }
282   }
283 
284   // If AllowModify is true, we can erase any terminators after
285   // FirstUncondOrIndirectBR.
286   if (AllowModify && FirstUncondOrIndirectBr != MBB.end()) {
287     while (std::next(FirstUncondOrIndirectBr) != MBB.end()) {
288       std::next(FirstUncondOrIndirectBr)->eraseFromParent();
289       NumTerminators--;
290     }
291     I = FirstUncondOrIndirectBr;
292   }
293 
294   // We can't handle blocks that end in an indirect branch.
295   if (I->getDesc().isIndirectBranch())
296     return true;
297 
298   // We can't handle blocks with more than 2 terminators.
299   if (NumTerminators > 2)
300     return true;
301 
302   // Handle a single unconditional branch.
303   if (NumTerminators == 1 && I->getDesc().isUnconditionalBranch()) {
304     TBB = getBranchDestBlock(*I);
305     return false;
306   }
307 
308   // Handle a single conditional branch.
309   if (NumTerminators == 1 && I->getDesc().isConditionalBranch()) {
310     parseCondBranch(*I, TBB, Cond);
311     return false;
312   }
313 
314   // Handle a conditional branch followed by an unconditional branch.
315   if (NumTerminators == 2 && std::prev(I)->getDesc().isConditionalBranch() &&
316       I->getDesc().isUnconditionalBranch()) {
317     parseCondBranch(*std::prev(I), TBB, Cond);
318     FBB = getBranchDestBlock(*I);
319     return false;
320   }
321 
322   // Otherwise, we can't handle this.
323   return true;
324 }
325 
326 unsigned RISCVInstrInfo::removeBranch(MachineBasicBlock &MBB,
327                                       int *BytesRemoved) const {
328   if (BytesRemoved)
329     *BytesRemoved = 0;
330   MachineBasicBlock::iterator I = MBB.getLastNonDebugInstr();
331   if (I == MBB.end())
332     return 0;
333 
334   if (!I->getDesc().isUnconditionalBranch() &&
335       !I->getDesc().isConditionalBranch())
336     return 0;
337 
338   // Remove the branch.
339   if (BytesRemoved)
340     *BytesRemoved += getInstSizeInBytes(*I);
341   I->eraseFromParent();
342 
343   I = MBB.end();
344 
345   if (I == MBB.begin())
346     return 1;
347   --I;
348   if (!I->getDesc().isConditionalBranch())
349     return 1;
350 
351   // Remove the branch.
352   if (BytesRemoved)
353     *BytesRemoved += getInstSizeInBytes(*I);
354   I->eraseFromParent();
355   return 2;
356 }
357 
358 // Inserts a branch into the end of the specific MachineBasicBlock, returning
359 // the number of instructions inserted.
360 unsigned RISCVInstrInfo::insertBranch(
361     MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB,
362     ArrayRef<MachineOperand> Cond, const DebugLoc &DL, int *BytesAdded) const {
363   if (BytesAdded)
364     *BytesAdded = 0;
365 
366   // Shouldn't be a fall through.
367   assert(TBB && "insertBranch must not be told to insert a fallthrough");
368   assert((Cond.size() == 3 || Cond.size() == 0) &&
369          "RISCV branch conditions have two components!");
370 
371   // Unconditional branch.
372   if (Cond.empty()) {
373     MachineInstr &MI = *BuildMI(&MBB, DL, get(RISCV::PseudoBR)).addMBB(TBB);
374     if (BytesAdded)
375       *BytesAdded += getInstSizeInBytes(MI);
376     return 1;
377   }
378 
379   // Either a one or two-way conditional branch.
380   unsigned Opc = Cond[0].getImm();
381   MachineInstr &CondMI =
382       *BuildMI(&MBB, DL, get(Opc)).add(Cond[1]).add(Cond[2]).addMBB(TBB);
383   if (BytesAdded)
384     *BytesAdded += getInstSizeInBytes(CondMI);
385 
386   // One-way conditional branch.
387   if (!FBB)
388     return 1;
389 
390   // Two-way conditional branch.
391   MachineInstr &MI = *BuildMI(&MBB, DL, get(RISCV::PseudoBR)).addMBB(FBB);
392   if (BytesAdded)
393     *BytesAdded += getInstSizeInBytes(MI);
394   return 2;
395 }
396 
397 unsigned RISCVInstrInfo::insertIndirectBranch(MachineBasicBlock &MBB,
398                                               MachineBasicBlock &DestBB,
399                                               const DebugLoc &DL,
400                                               int64_t BrOffset,
401                                               RegScavenger *RS) const {
402   assert(RS && "RegScavenger required for long branching");
403   assert(MBB.empty() &&
404          "new block should be inserted for expanding unconditional branch");
405   assert(MBB.pred_size() == 1);
406 
407   MachineFunction *MF = MBB.getParent();
408   MachineRegisterInfo &MRI = MF->getRegInfo();
409 
410   if (!isInt<32>(BrOffset))
411     report_fatal_error(
412         "Branch offsets outside of the signed 32-bit range not supported");
413 
414   // FIXME: A virtual register must be used initially, as the register
415   // scavenger won't work with empty blocks (SIInstrInfo::insertIndirectBranch
416   // uses the same workaround).
417   Register ScratchReg = MRI.createVirtualRegister(&RISCV::GPRRegClass);
418   auto II = MBB.end();
419 
420   MachineInstr &MI = *BuildMI(MBB, II, DL, get(RISCV::PseudoJump))
421                           .addReg(ScratchReg, RegState::Define | RegState::Dead)
422                           .addMBB(&DestBB, RISCVII::MO_CALL);
423 
424   RS->enterBasicBlockEnd(MBB);
425   unsigned Scav = RS->scavengeRegisterBackwards(RISCV::GPRRegClass,
426                                                 MI.getIterator(), false, 0);
427   MRI.replaceRegWith(ScratchReg, Scav);
428   MRI.clearVirtRegs();
429   RS->setRegUsed(Scav);
430   return 8;
431 }
432 
433 bool RISCVInstrInfo::reverseBranchCondition(
434     SmallVectorImpl<MachineOperand> &Cond) const {
435   assert((Cond.size() == 3) && "Invalid branch condition!");
436   Cond[0].setImm(getOppositeBranchOpcode(Cond[0].getImm()));
437   return false;
438 }
439 
440 MachineBasicBlock *
441 RISCVInstrInfo::getBranchDestBlock(const MachineInstr &MI) const {
442   assert(MI.getDesc().isBranch() && "Unexpected opcode!");
443   // The branch target is always the last operand.
444   int NumOp = MI.getNumExplicitOperands();
445   return MI.getOperand(NumOp - 1).getMBB();
446 }
447 
448 bool RISCVInstrInfo::isBranchOffsetInRange(unsigned BranchOp,
449                                            int64_t BrOffset) const {
450   unsigned XLen = STI.getXLen();
451   // Ideally we could determine the supported branch offset from the
452   // RISCVII::FormMask, but this can't be used for Pseudo instructions like
453   // PseudoBR.
454   switch (BranchOp) {
455   default:
456     llvm_unreachable("Unexpected opcode!");
457   case RISCV::BEQ:
458   case RISCV::BNE:
459   case RISCV::BLT:
460   case RISCV::BGE:
461   case RISCV::BLTU:
462   case RISCV::BGEU:
463     return isIntN(13, BrOffset);
464   case RISCV::JAL:
465   case RISCV::PseudoBR:
466     return isIntN(21, BrOffset);
467   case RISCV::PseudoJump:
468     return isIntN(32, SignExtend64(BrOffset + 0x800, XLen));
469   }
470 }
471 
472 unsigned RISCVInstrInfo::getInstSizeInBytes(const MachineInstr &MI) const {
473   unsigned Opcode = MI.getOpcode();
474 
475   switch (Opcode) {
476   default: {
477     if (MI.getParent() && MI.getParent()->getParent()) {
478       const auto MF = MI.getMF();
479       const auto &TM = static_cast<const RISCVTargetMachine &>(MF->getTarget());
480       const MCRegisterInfo &MRI = *TM.getMCRegisterInfo();
481       const MCSubtargetInfo &STI = *TM.getMCSubtargetInfo();
482       const RISCVSubtarget &ST = MF->getSubtarget<RISCVSubtarget>();
483       if (isCompressibleInst(MI, &ST, MRI, STI))
484         return 2;
485     }
486     return get(Opcode).getSize();
487   }
488   case TargetOpcode::EH_LABEL:
489   case TargetOpcode::IMPLICIT_DEF:
490   case TargetOpcode::KILL:
491   case TargetOpcode::DBG_VALUE:
492     return 0;
493   // These values are determined based on RISCVExpandAtomicPseudoInsts,
494   // RISCVExpandPseudoInsts and RISCVMCCodeEmitter, depending on where the
495   // pseudos are expanded.
496   case RISCV::PseudoCALLReg:
497   case RISCV::PseudoCALL:
498   case RISCV::PseudoJump:
499   case RISCV::PseudoTAIL:
500   case RISCV::PseudoLLA:
501   case RISCV::PseudoLA:
502   case RISCV::PseudoLA_TLS_IE:
503   case RISCV::PseudoLA_TLS_GD:
504     return 8;
505   case RISCV::PseudoAtomicLoadNand32:
506   case RISCV::PseudoAtomicLoadNand64:
507     return 20;
508   case RISCV::PseudoMaskedAtomicSwap32:
509   case RISCV::PseudoMaskedAtomicLoadAdd32:
510   case RISCV::PseudoMaskedAtomicLoadSub32:
511     return 28;
512   case RISCV::PseudoMaskedAtomicLoadNand32:
513     return 32;
514   case RISCV::PseudoMaskedAtomicLoadMax32:
515   case RISCV::PseudoMaskedAtomicLoadMin32:
516     return 44;
517   case RISCV::PseudoMaskedAtomicLoadUMax32:
518   case RISCV::PseudoMaskedAtomicLoadUMin32:
519     return 36;
520   case RISCV::PseudoCmpXchg32:
521   case RISCV::PseudoCmpXchg64:
522     return 16;
523   case RISCV::PseudoMaskedCmpXchg32:
524     return 32;
525   case TargetOpcode::INLINEASM:
526   case TargetOpcode::INLINEASM_BR: {
527     const MachineFunction &MF = *MI.getParent()->getParent();
528     const auto &TM = static_cast<const RISCVTargetMachine &>(MF.getTarget());
529     return getInlineAsmLength(MI.getOperand(0).getSymbolName(),
530                               *TM.getMCAsmInfo());
531   }
532   }
533 }
534 
535 bool RISCVInstrInfo::isAsCheapAsAMove(const MachineInstr &MI) const {
536   const unsigned Opcode = MI.getOpcode();
537   switch (Opcode) {
538   default:
539     break;
540   case RISCV::FSGNJ_D:
541   case RISCV::FSGNJ_S:
542     // The canonical floating-point move is fsgnj rd, rs, rs.
543     return MI.getOperand(1).isReg() && MI.getOperand(2).isReg() &&
544            MI.getOperand(1).getReg() == MI.getOperand(2).getReg();
545   case RISCV::ADDI:
546   case RISCV::ORI:
547   case RISCV::XORI:
548     return (MI.getOperand(1).isReg() &&
549             MI.getOperand(1).getReg() == RISCV::X0) ||
550            (MI.getOperand(2).isImm() && MI.getOperand(2).getImm() == 0);
551   }
552   return MI.isAsCheapAsAMove();
553 }
554 
555 Optional<DestSourcePair>
556 RISCVInstrInfo::isCopyInstrImpl(const MachineInstr &MI) const {
557   if (MI.isMoveReg())
558     return DestSourcePair{MI.getOperand(0), MI.getOperand(1)};
559   switch (MI.getOpcode()) {
560   default:
561     break;
562   case RISCV::ADDI:
563     // Operand 1 can be a frameindex but callers expect registers
564     if (MI.getOperand(1).isReg() && MI.getOperand(2).isImm() &&
565         MI.getOperand(2).getImm() == 0)
566       return DestSourcePair{MI.getOperand(0), MI.getOperand(1)};
567     break;
568   case RISCV::FSGNJ_D:
569   case RISCV::FSGNJ_S:
570     // The canonical floating-point move is fsgnj rd, rs, rs.
571     if (MI.getOperand(1).isReg() && MI.getOperand(2).isReg() &&
572         MI.getOperand(1).getReg() == MI.getOperand(2).getReg())
573       return DestSourcePair{MI.getOperand(0), MI.getOperand(1)};
574     break;
575   }
576   return None;
577 }
578 
579 bool RISCVInstrInfo::verifyInstruction(const MachineInstr &MI,
580                                        StringRef &ErrInfo) const {
581   const MCInstrInfo *MCII = STI.getInstrInfo();
582   MCInstrDesc const &Desc = MCII->get(MI.getOpcode());
583 
584   for (auto &OI : enumerate(Desc.operands())) {
585     unsigned OpType = OI.value().OperandType;
586     if (OpType >= RISCVOp::OPERAND_FIRST_RISCV_IMM &&
587         OpType <= RISCVOp::OPERAND_LAST_RISCV_IMM) {
588       const MachineOperand &MO = MI.getOperand(OI.index());
589       if (MO.isImm()) {
590         int64_t Imm = MO.getImm();
591         bool Ok;
592         switch (OpType) {
593         default:
594           llvm_unreachable("Unexpected operand type");
595         case RISCVOp::OPERAND_UIMM4:
596           Ok = isUInt<4>(Imm);
597           break;
598         case RISCVOp::OPERAND_UIMM5:
599           Ok = isUInt<5>(Imm);
600           break;
601         case RISCVOp::OPERAND_UIMM12:
602           Ok = isUInt<12>(Imm);
603           break;
604         case RISCVOp::OPERAND_SIMM12:
605           Ok = isInt<12>(Imm);
606           break;
607         case RISCVOp::OPERAND_UIMM20:
608           Ok = isUInt<20>(Imm);
609           break;
610         case RISCVOp::OPERAND_UIMMLOG2XLEN:
611           if (STI.getTargetTriple().isArch64Bit())
612             Ok = isUInt<6>(Imm);
613           else
614             Ok = isUInt<5>(Imm);
615           break;
616         }
617         if (!Ok) {
618           ErrInfo = "Invalid immediate";
619           return false;
620         }
621       }
622     }
623   }
624 
625   return true;
626 }
627 
628 // Return true if get the base operand, byte offset of an instruction and the
629 // memory width. Width is the size of memory that is being loaded/stored.
630 bool RISCVInstrInfo::getMemOperandWithOffsetWidth(
631     const MachineInstr &LdSt, const MachineOperand *&BaseReg, int64_t &Offset,
632     unsigned &Width, const TargetRegisterInfo *TRI) const {
633   if (!LdSt.mayLoadOrStore())
634     return false;
635 
636   // Here we assume the standard RISC-V ISA, which uses a base+offset
637   // addressing mode. You'll need to relax these conditions to support custom
638   // load/stores instructions.
639   if (LdSt.getNumExplicitOperands() != 3)
640     return false;
641   if (!LdSt.getOperand(1).isReg() || !LdSt.getOperand(2).isImm())
642     return false;
643 
644   if (!LdSt.hasOneMemOperand())
645     return false;
646 
647   Width = (*LdSt.memoperands_begin())->getSize();
648   BaseReg = &LdSt.getOperand(1);
649   Offset = LdSt.getOperand(2).getImm();
650   return true;
651 }
652 
653 bool RISCVInstrInfo::areMemAccessesTriviallyDisjoint(
654     const MachineInstr &MIa, const MachineInstr &MIb) const {
655   assert(MIa.mayLoadOrStore() && "MIa must be a load or store.");
656   assert(MIb.mayLoadOrStore() && "MIb must be a load or store.");
657 
658   if (MIa.hasUnmodeledSideEffects() || MIb.hasUnmodeledSideEffects() ||
659       MIa.hasOrderedMemoryRef() || MIb.hasOrderedMemoryRef())
660     return false;
661 
662   // Retrieve the base register, offset from the base register and width. Width
663   // is the size of memory that is being loaded/stored (e.g. 1, 2, 4).  If
664   // base registers are identical, and the offset of a lower memory access +
665   // the width doesn't overlap the offset of a higher memory access,
666   // then the memory accesses are different.
667   const TargetRegisterInfo *TRI = STI.getRegisterInfo();
668   const MachineOperand *BaseOpA = nullptr, *BaseOpB = nullptr;
669   int64_t OffsetA = 0, OffsetB = 0;
670   unsigned int WidthA = 0, WidthB = 0;
671   if (getMemOperandWithOffsetWidth(MIa, BaseOpA, OffsetA, WidthA, TRI) &&
672       getMemOperandWithOffsetWidth(MIb, BaseOpB, OffsetB, WidthB, TRI)) {
673     if (BaseOpA->isIdenticalTo(*BaseOpB)) {
674       int LowOffset = std::min(OffsetA, OffsetB);
675       int HighOffset = std::max(OffsetA, OffsetB);
676       int LowWidth = (LowOffset == OffsetA) ? WidthA : WidthB;
677       if (LowOffset + LowWidth <= HighOffset)
678         return true;
679     }
680   }
681   return false;
682 }
683 
684 std::pair<unsigned, unsigned>
685 RISCVInstrInfo::decomposeMachineOperandsTargetFlags(unsigned TF) const {
686   const unsigned Mask = RISCVII::MO_DIRECT_FLAG_MASK;
687   return std::make_pair(TF & Mask, TF & ~Mask);
688 }
689 
690 ArrayRef<std::pair<unsigned, const char *>>
691 RISCVInstrInfo::getSerializableDirectMachineOperandTargetFlags() const {
692   using namespace RISCVII;
693   static const std::pair<unsigned, const char *> TargetFlags[] = {
694       {MO_CALL, "riscv-call"},
695       {MO_PLT, "riscv-plt"},
696       {MO_LO, "riscv-lo"},
697       {MO_HI, "riscv-hi"},
698       {MO_PCREL_LO, "riscv-pcrel-lo"},
699       {MO_PCREL_HI, "riscv-pcrel-hi"},
700       {MO_GOT_HI, "riscv-got-hi"},
701       {MO_TPREL_LO, "riscv-tprel-lo"},
702       {MO_TPREL_HI, "riscv-tprel-hi"},
703       {MO_TPREL_ADD, "riscv-tprel-add"},
704       {MO_TLS_GOT_HI, "riscv-tls-got-hi"},
705       {MO_TLS_GD_HI, "riscv-tls-gd-hi"}};
706   return makeArrayRef(TargetFlags);
707 }
708 bool RISCVInstrInfo::isFunctionSafeToOutlineFrom(
709     MachineFunction &MF, bool OutlineFromLinkOnceODRs) const {
710   const Function &F = MF.getFunction();
711 
712   // Can F be deduplicated by the linker? If it can, don't outline from it.
713   if (!OutlineFromLinkOnceODRs && F.hasLinkOnceODRLinkage())
714     return false;
715 
716   // Don't outline from functions with section markings; the program could
717   // expect that all the code is in the named section.
718   if (F.hasSection())
719     return false;
720 
721   // It's safe to outline from MF.
722   return true;
723 }
724 
725 bool RISCVInstrInfo::isMBBSafeToOutlineFrom(MachineBasicBlock &MBB,
726                                             unsigned &Flags) const {
727   // More accurate safety checking is done in getOutliningCandidateInfo.
728   return true;
729 }
730 
731 // Enum values indicating how an outlined call should be constructed.
732 enum MachineOutlinerConstructionID {
733   MachineOutlinerDefault
734 };
735 
736 outliner::OutlinedFunction RISCVInstrInfo::getOutliningCandidateInfo(
737     std::vector<outliner::Candidate> &RepeatedSequenceLocs) const {
738 
739   // First we need to filter out candidates where the X5 register (IE t0) can't
740   // be used to setup the function call.
741   auto CannotInsertCall = [](outliner::Candidate &C) {
742     const TargetRegisterInfo *TRI = C.getMF()->getSubtarget().getRegisterInfo();
743 
744     C.initLRU(*TRI);
745     LiveRegUnits LRU = C.LRU;
746     return !LRU.available(RISCV::X5);
747   };
748 
749   RepeatedSequenceLocs.erase(std::remove_if(RepeatedSequenceLocs.begin(),
750                                             RepeatedSequenceLocs.end(),
751                                             CannotInsertCall),
752                              RepeatedSequenceLocs.end());
753 
754   // If the sequence doesn't have enough candidates left, then we're done.
755   if (RepeatedSequenceLocs.size() < 2)
756     return outliner::OutlinedFunction();
757 
758   unsigned SequenceSize = 0;
759 
760   auto I = RepeatedSequenceLocs[0].front();
761   auto E = std::next(RepeatedSequenceLocs[0].back());
762   for (; I != E; ++I)
763     SequenceSize += getInstSizeInBytes(*I);
764 
765   // call t0, function = 8 bytes.
766   unsigned CallOverhead = 8;
767   for (auto &C : RepeatedSequenceLocs)
768     C.setCallInfo(MachineOutlinerDefault, CallOverhead);
769 
770   // jr t0 = 4 bytes, 2 bytes if compressed instructions are enabled.
771   unsigned FrameOverhead = 4;
772   if (RepeatedSequenceLocs[0].getMF()->getSubtarget()
773           .getFeatureBits()[RISCV::FeatureStdExtC])
774     FrameOverhead = 2;
775 
776   return outliner::OutlinedFunction(RepeatedSequenceLocs, SequenceSize,
777                                     FrameOverhead, MachineOutlinerDefault);
778 }
779 
780 outliner::InstrType
781 RISCVInstrInfo::getOutliningType(MachineBasicBlock::iterator &MBBI,
782                                  unsigned Flags) const {
783   MachineInstr &MI = *MBBI;
784   MachineBasicBlock *MBB = MI.getParent();
785   const TargetRegisterInfo *TRI =
786       MBB->getParent()->getSubtarget().getRegisterInfo();
787 
788   // Positions generally can't safely be outlined.
789   if (MI.isPosition()) {
790     // We can manually strip out CFI instructions later.
791     if (MI.isCFIInstruction())
792       return outliner::InstrType::Invisible;
793 
794     return outliner::InstrType::Illegal;
795   }
796 
797   // Don't trust the user to write safe inline assembly.
798   if (MI.isInlineAsm())
799     return outliner::InstrType::Illegal;
800 
801   // We can't outline branches to other basic blocks.
802   if (MI.isTerminator() && !MBB->succ_empty())
803     return outliner::InstrType::Illegal;
804 
805   // We need support for tail calls to outlined functions before return
806   // statements can be allowed.
807   if (MI.isReturn())
808     return outliner::InstrType::Illegal;
809 
810   // Don't allow modifying the X5 register which we use for return addresses for
811   // these outlined functions.
812   if (MI.modifiesRegister(RISCV::X5, TRI) ||
813       MI.getDesc().hasImplicitDefOfPhysReg(RISCV::X5))
814     return outliner::InstrType::Illegal;
815 
816   // Make sure the operands don't reference something unsafe.
817   for (const auto &MO : MI.operands())
818     if (MO.isMBB() || MO.isBlockAddress() || MO.isCPI())
819       return outliner::InstrType::Illegal;
820 
821   // Don't allow instructions which won't be materialized to impact outlining
822   // analysis.
823   if (MI.isMetaInstruction())
824     return outliner::InstrType::Invisible;
825 
826   return outliner::InstrType::Legal;
827 }
828 
829 void RISCVInstrInfo::buildOutlinedFrame(
830     MachineBasicBlock &MBB, MachineFunction &MF,
831     const outliner::OutlinedFunction &OF) const {
832 
833   // Strip out any CFI instructions
834   bool Changed = true;
835   while (Changed) {
836     Changed = false;
837     auto I = MBB.begin();
838     auto E = MBB.end();
839     for (; I != E; ++I) {
840       if (I->isCFIInstruction()) {
841         I->removeFromParent();
842         Changed = true;
843         break;
844       }
845     }
846   }
847 
848   MBB.addLiveIn(RISCV::X5);
849 
850   // Add in a return instruction to the end of the outlined frame.
851   MBB.insert(MBB.end(), BuildMI(MF, DebugLoc(), get(RISCV::JALR))
852       .addReg(RISCV::X0, RegState::Define)
853       .addReg(RISCV::X5)
854       .addImm(0));
855 }
856 
857 MachineBasicBlock::iterator RISCVInstrInfo::insertOutlinedCall(
858     Module &M, MachineBasicBlock &MBB, MachineBasicBlock::iterator &It,
859     MachineFunction &MF, const outliner::Candidate &C) const {
860 
861   // Add in a call instruction to the outlined function at the given location.
862   It = MBB.insert(It,
863                   BuildMI(MF, DebugLoc(), get(RISCV::PseudoCALLReg), RISCV::X5)
864                       .addGlobalAddress(M.getNamedValue(MF.getName()), 0,
865                                         RISCVII::MO_CALL));
866   return It;
867 }
868