1 //===-- RISCVInstrInfo.cpp - RISCV Instruction Information ------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the RISCV implementation of the TargetInstrInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "RISCVInstrInfo.h"
14 #include "MCTargetDesc/RISCVMatInt.h"
15 #include "RISCV.h"
16 #include "RISCVMachineFunctionInfo.h"
17 #include "RISCVSubtarget.h"
18 #include "RISCVTargetMachine.h"
19 #include "llvm/ADT/STLExtras.h"
20 #include "llvm/ADT/SmallVector.h"
21 #include "llvm/Analysis/MemoryLocation.h"
22 #include "llvm/CodeGen/MachineFunctionPass.h"
23 #include "llvm/CodeGen/MachineInstrBuilder.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/CodeGen/RegisterScavenging.h"
26 #include "llvm/MC/MCInstBuilder.h"
27 #include "llvm/Support/ErrorHandling.h"
28 #include "llvm/Support/TargetRegistry.h"
29 
30 using namespace llvm;
31 
32 #define GEN_CHECK_COMPRESS_INSTR
33 #include "RISCVGenCompressInstEmitter.inc"
34 
35 #define GET_INSTRINFO_CTOR_DTOR
36 #include "RISCVGenInstrInfo.inc"
37 
38 namespace llvm {
39 namespace RISCVVPseudosTable {
40 
41 using namespace RISCV;
42 
43 #define GET_RISCVVPseudosTable_IMPL
44 #include "RISCVGenSearchableTables.inc"
45 
46 } // namespace RISCVVPseudosTable
47 } // namespace llvm
48 
49 RISCVInstrInfo::RISCVInstrInfo(RISCVSubtarget &STI)
50     : RISCVGenInstrInfo(RISCV::ADJCALLSTACKDOWN, RISCV::ADJCALLSTACKUP),
51       STI(STI) {}
52 
53 MCInst RISCVInstrInfo::getNop() const {
54   if (STI.getFeatureBits()[RISCV::FeatureStdExtC])
55     return MCInstBuilder(RISCV::C_NOP);
56   return MCInstBuilder(RISCV::ADDI)
57       .addReg(RISCV::X0)
58       .addReg(RISCV::X0)
59       .addImm(0);
60 }
61 
62 unsigned RISCVInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
63                                              int &FrameIndex) const {
64   switch (MI.getOpcode()) {
65   default:
66     return 0;
67   case RISCV::LB:
68   case RISCV::LBU:
69   case RISCV::LH:
70   case RISCV::LHU:
71   case RISCV::FLH:
72   case RISCV::LW:
73   case RISCV::FLW:
74   case RISCV::LWU:
75   case RISCV::LD:
76   case RISCV::FLD:
77     break;
78   }
79 
80   if (MI.getOperand(1).isFI() && MI.getOperand(2).isImm() &&
81       MI.getOperand(2).getImm() == 0) {
82     FrameIndex = MI.getOperand(1).getIndex();
83     return MI.getOperand(0).getReg();
84   }
85 
86   return 0;
87 }
88 
89 unsigned RISCVInstrInfo::isStoreToStackSlot(const MachineInstr &MI,
90                                             int &FrameIndex) const {
91   switch (MI.getOpcode()) {
92   default:
93     return 0;
94   case RISCV::SB:
95   case RISCV::SH:
96   case RISCV::SW:
97   case RISCV::FSH:
98   case RISCV::FSW:
99   case RISCV::SD:
100   case RISCV::FSD:
101     break;
102   }
103 
104   if (MI.getOperand(1).isFI() && MI.getOperand(2).isImm() &&
105       MI.getOperand(2).getImm() == 0) {
106     FrameIndex = MI.getOperand(1).getIndex();
107     return MI.getOperand(0).getReg();
108   }
109 
110   return 0;
111 }
112 
113 void RISCVInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
114                                  MachineBasicBlock::iterator MBBI,
115                                  const DebugLoc &DL, MCRegister DstReg,
116                                  MCRegister SrcReg, bool KillSrc) const {
117   if (RISCV::GPRRegClass.contains(DstReg, SrcReg)) {
118     BuildMI(MBB, MBBI, DL, get(RISCV::ADDI), DstReg)
119         .addReg(SrcReg, getKillRegState(KillSrc))
120         .addImm(0);
121     return;
122   }
123 
124   // FPR->FPR copies and VR->VR copies.
125   unsigned Opc;
126   bool IsScalableVector = false;
127   if (RISCV::FPR16RegClass.contains(DstReg, SrcReg))
128     Opc = RISCV::FSGNJ_H;
129   else if (RISCV::FPR32RegClass.contains(DstReg, SrcReg))
130     Opc = RISCV::FSGNJ_S;
131   else if (RISCV::FPR64RegClass.contains(DstReg, SrcReg))
132     Opc = RISCV::FSGNJ_D;
133   else if (RISCV::VRRegClass.contains(DstReg, SrcReg)) {
134     Opc = RISCV::PseudoVMV1R_V;
135     IsScalableVector = true;
136   } else if (RISCV::VRM2RegClass.contains(DstReg, SrcReg)) {
137     Opc = RISCV::PseudoVMV2R_V;
138     IsScalableVector = true;
139   } else if (RISCV::VRM4RegClass.contains(DstReg, SrcReg)) {
140     Opc = RISCV::PseudoVMV4R_V;
141     IsScalableVector = true;
142   } else if (RISCV::VRM8RegClass.contains(DstReg, SrcReg)) {
143     Opc = RISCV::PseudoVMV8R_V;
144     IsScalableVector = true;
145   } else
146     llvm_unreachable("Impossible reg-to-reg copy");
147 
148   if (IsScalableVector)
149     BuildMI(MBB, MBBI, DL, get(Opc), DstReg)
150         .addReg(SrcReg, getKillRegState(KillSrc));
151   else
152     BuildMI(MBB, MBBI, DL, get(Opc), DstReg)
153         .addReg(SrcReg, getKillRegState(KillSrc))
154         .addReg(SrcReg, getKillRegState(KillSrc));
155 }
156 
157 void RISCVInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
158                                          MachineBasicBlock::iterator I,
159                                          Register SrcReg, bool IsKill, int FI,
160                                          const TargetRegisterClass *RC,
161                                          const TargetRegisterInfo *TRI) const {
162   DebugLoc DL;
163   if (I != MBB.end())
164     DL = I->getDebugLoc();
165 
166   MachineFunction *MF = MBB.getParent();
167   MachineFrameInfo &MFI = MF->getFrameInfo();
168 
169   unsigned Opcode;
170   bool IsScalableVector = true;
171   bool IsZvlsseg = true;
172   if (RISCV::GPRRegClass.hasSubClassEq(RC)) {
173     Opcode = TRI->getRegSizeInBits(RISCV::GPRRegClass) == 32 ?
174              RISCV::SW : RISCV::SD;
175     IsScalableVector = false;
176   } else if (RISCV::FPR16RegClass.hasSubClassEq(RC)) {
177     Opcode = RISCV::FSH;
178     IsScalableVector = false;
179   } else if (RISCV::FPR32RegClass.hasSubClassEq(RC)) {
180     Opcode = RISCV::FSW;
181     IsScalableVector = false;
182   } else if (RISCV::FPR64RegClass.hasSubClassEq(RC)) {
183     Opcode = RISCV::FSD;
184     IsScalableVector = false;
185   } else if (RISCV::VRRegClass.hasSubClassEq(RC)) {
186     Opcode = RISCV::PseudoVSPILL_M1;
187     IsZvlsseg = false;
188   } else if (RISCV::VRM2RegClass.hasSubClassEq(RC)) {
189     Opcode = RISCV::PseudoVSPILL_M2;
190     IsZvlsseg = false;
191   } else if (RISCV::VRM4RegClass.hasSubClassEq(RC)) {
192     Opcode = RISCV::PseudoVSPILL_M4;
193     IsZvlsseg = false;
194   } else if (RISCV::VRM8RegClass.hasSubClassEq(RC)) {
195     Opcode = RISCV::PseudoVSPILL_M8;
196     IsZvlsseg = false;
197   } else if (RISCV::VRN2M1RegClass.hasSubClassEq(RC))
198     Opcode = RISCV::PseudoVSPILL2_M1;
199   else if (RISCV::VRN2M2RegClass.hasSubClassEq(RC))
200     Opcode = RISCV::PseudoVSPILL2_M2;
201   else if (RISCV::VRN2M4RegClass.hasSubClassEq(RC))
202     Opcode = RISCV::PseudoVSPILL2_M4;
203   else if (RISCV::VRN3M1RegClass.hasSubClassEq(RC))
204     Opcode = RISCV::PseudoVSPILL3_M1;
205   else if (RISCV::VRN3M2RegClass.hasSubClassEq(RC))
206     Opcode = RISCV::PseudoVSPILL3_M2;
207   else if (RISCV::VRN4M1RegClass.hasSubClassEq(RC))
208     Opcode = RISCV::PseudoVSPILL4_M1;
209   else if (RISCV::VRN4M2RegClass.hasSubClassEq(RC))
210     Opcode = RISCV::PseudoVSPILL4_M2;
211   else if (RISCV::VRN5M1RegClass.hasSubClassEq(RC))
212     Opcode = RISCV::PseudoVSPILL5_M1;
213   else if (RISCV::VRN6M1RegClass.hasSubClassEq(RC))
214     Opcode = RISCV::PseudoVSPILL6_M1;
215   else if (RISCV::VRN7M1RegClass.hasSubClassEq(RC))
216     Opcode = RISCV::PseudoVSPILL7_M1;
217   else if (RISCV::VRN8M1RegClass.hasSubClassEq(RC))
218     Opcode = RISCV::PseudoVSPILL8_M1;
219   else
220     llvm_unreachable("Can't store this register to stack slot");
221 
222   if (IsScalableVector) {
223     MachineMemOperand *MMO = MF->getMachineMemOperand(
224         MachinePointerInfo::getFixedStack(*MF, FI), MachineMemOperand::MOStore,
225         MemoryLocation::UnknownSize, MFI.getObjectAlign(FI));
226 
227     MFI.setStackID(FI, TargetStackID::ScalableVector);
228     auto MIB = BuildMI(MBB, I, DL, get(Opcode))
229                    .addReg(SrcReg, getKillRegState(IsKill))
230                    .addFrameIndex(FI)
231                    .addMemOperand(MMO);
232     if (IsZvlsseg) {
233       // For spilling/reloading Zvlsseg registers, append the dummy field for
234       // the scaled vector length. The argument will be used when expanding
235       // these pseudo instructions.
236       MIB.addReg(RISCV::X0);
237     }
238   } else {
239     MachineMemOperand *MMO = MF->getMachineMemOperand(
240         MachinePointerInfo::getFixedStack(*MF, FI), MachineMemOperand::MOStore,
241         MFI.getObjectSize(FI), MFI.getObjectAlign(FI));
242 
243     BuildMI(MBB, I, DL, get(Opcode))
244         .addReg(SrcReg, getKillRegState(IsKill))
245         .addFrameIndex(FI)
246         .addImm(0)
247         .addMemOperand(MMO);
248   }
249 }
250 
251 void RISCVInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
252                                           MachineBasicBlock::iterator I,
253                                           Register DstReg, int FI,
254                                           const TargetRegisterClass *RC,
255                                           const TargetRegisterInfo *TRI) const {
256   DebugLoc DL;
257   if (I != MBB.end())
258     DL = I->getDebugLoc();
259 
260   MachineFunction *MF = MBB.getParent();
261   MachineFrameInfo &MFI = MF->getFrameInfo();
262 
263   unsigned Opcode;
264   bool IsScalableVector = true;
265   bool IsZvlsseg = true;
266   if (RISCV::GPRRegClass.hasSubClassEq(RC)) {
267     Opcode = TRI->getRegSizeInBits(RISCV::GPRRegClass) == 32 ?
268              RISCV::LW : RISCV::LD;
269     IsScalableVector = false;
270   } else if (RISCV::FPR16RegClass.hasSubClassEq(RC)) {
271     Opcode = RISCV::FLH;
272     IsScalableVector = false;
273   } else if (RISCV::FPR32RegClass.hasSubClassEq(RC)) {
274     Opcode = RISCV::FLW;
275     IsScalableVector = false;
276   } else if (RISCV::FPR64RegClass.hasSubClassEq(RC)) {
277     Opcode = RISCV::FLD;
278     IsScalableVector = false;
279   } else if (RISCV::VRRegClass.hasSubClassEq(RC)) {
280     Opcode = RISCV::PseudoVRELOAD_M1;
281     IsZvlsseg = false;
282   } else if (RISCV::VRM2RegClass.hasSubClassEq(RC)) {
283     Opcode = RISCV::PseudoVRELOAD_M2;
284     IsZvlsseg = false;
285   } else if (RISCV::VRM4RegClass.hasSubClassEq(RC)) {
286     Opcode = RISCV::PseudoVRELOAD_M4;
287     IsZvlsseg = false;
288   } else if (RISCV::VRM8RegClass.hasSubClassEq(RC)) {
289     Opcode = RISCV::PseudoVRELOAD_M8;
290     IsZvlsseg = false;
291   } else if (RISCV::VRN2M1RegClass.hasSubClassEq(RC))
292     Opcode = RISCV::PseudoVRELOAD2_M1;
293   else if (RISCV::VRN2M2RegClass.hasSubClassEq(RC))
294     Opcode = RISCV::PseudoVRELOAD2_M2;
295   else if (RISCV::VRN2M4RegClass.hasSubClassEq(RC))
296     Opcode = RISCV::PseudoVRELOAD2_M4;
297   else if (RISCV::VRN3M1RegClass.hasSubClassEq(RC))
298     Opcode = RISCV::PseudoVRELOAD3_M1;
299   else if (RISCV::VRN3M2RegClass.hasSubClassEq(RC))
300     Opcode = RISCV::PseudoVRELOAD3_M2;
301   else if (RISCV::VRN4M1RegClass.hasSubClassEq(RC))
302     Opcode = RISCV::PseudoVRELOAD4_M1;
303   else if (RISCV::VRN4M2RegClass.hasSubClassEq(RC))
304     Opcode = RISCV::PseudoVRELOAD4_M2;
305   else if (RISCV::VRN5M1RegClass.hasSubClassEq(RC))
306     Opcode = RISCV::PseudoVRELOAD5_M1;
307   else if (RISCV::VRN6M1RegClass.hasSubClassEq(RC))
308     Opcode = RISCV::PseudoVRELOAD6_M1;
309   else if (RISCV::VRN7M1RegClass.hasSubClassEq(RC))
310     Opcode = RISCV::PseudoVRELOAD7_M1;
311   else if (RISCV::VRN8M1RegClass.hasSubClassEq(RC))
312     Opcode = RISCV::PseudoVRELOAD8_M1;
313   else
314     llvm_unreachable("Can't load this register from stack slot");
315 
316   if (IsScalableVector) {
317     MachineMemOperand *MMO = MF->getMachineMemOperand(
318         MachinePointerInfo::getFixedStack(*MF, FI), MachineMemOperand::MOLoad,
319         MemoryLocation::UnknownSize, MFI.getObjectAlign(FI));
320 
321     MFI.setStackID(FI, TargetStackID::ScalableVector);
322     auto MIB = BuildMI(MBB, I, DL, get(Opcode), DstReg)
323                    .addFrameIndex(FI)
324                    .addMemOperand(MMO);
325     if (IsZvlsseg) {
326       // For spilling/reloading Zvlsseg registers, append the dummy field for
327       // the scaled vector length. The argument will be used when expanding
328       // these pseudo instructions.
329       MIB.addReg(RISCV::X0);
330     }
331   } else {
332     MachineMemOperand *MMO = MF->getMachineMemOperand(
333         MachinePointerInfo::getFixedStack(*MF, FI), MachineMemOperand::MOLoad,
334         MFI.getObjectSize(FI), MFI.getObjectAlign(FI));
335 
336     BuildMI(MBB, I, DL, get(Opcode), DstReg)
337         .addFrameIndex(FI)
338         .addImm(0)
339         .addMemOperand(MMO);
340   }
341 }
342 
343 void RISCVInstrInfo::movImm(MachineBasicBlock &MBB,
344                             MachineBasicBlock::iterator MBBI,
345                             const DebugLoc &DL, Register DstReg, uint64_t Val,
346                             MachineInstr::MIFlag Flag) const {
347   MachineFunction *MF = MBB.getParent();
348   MachineRegisterInfo &MRI = MF->getRegInfo();
349   bool IsRV64 = MF->getSubtarget<RISCVSubtarget>().is64Bit();
350   Register SrcReg = RISCV::X0;
351   Register Result = MRI.createVirtualRegister(&RISCV::GPRRegClass);
352   unsigned Num = 0;
353 
354   if (!IsRV64 && !isInt<32>(Val))
355     report_fatal_error("Should only materialize 32-bit constants for RV32");
356 
357   RISCVMatInt::InstSeq Seq = RISCVMatInt::generateInstSeq(Val, IsRV64);
358   assert(Seq.size() > 0);
359 
360   for (RISCVMatInt::Inst &Inst : Seq) {
361     // Write the final result to DstReg if it's the last instruction in the Seq.
362     // Otherwise, write the result to the temp register.
363     if (++Num == Seq.size())
364       Result = DstReg;
365 
366     if (Inst.Opc == RISCV::LUI) {
367       BuildMI(MBB, MBBI, DL, get(RISCV::LUI), Result)
368           .addImm(Inst.Imm)
369           .setMIFlag(Flag);
370     } else {
371       BuildMI(MBB, MBBI, DL, get(Inst.Opc), Result)
372           .addReg(SrcReg, RegState::Kill)
373           .addImm(Inst.Imm)
374           .setMIFlag(Flag);
375     }
376     // Only the first instruction has X0 as its source.
377     SrcReg = Result;
378   }
379 }
380 
381 // The contents of values added to Cond are not examined outside of
382 // RISCVInstrInfo, giving us flexibility in what to push to it. For RISCV, we
383 // push BranchOpcode, Reg1, Reg2.
384 static void parseCondBranch(MachineInstr &LastInst, MachineBasicBlock *&Target,
385                             SmallVectorImpl<MachineOperand> &Cond) {
386   // Block ends with fall-through condbranch.
387   assert(LastInst.getDesc().isConditionalBranch() &&
388          "Unknown conditional branch");
389   Target = LastInst.getOperand(2).getMBB();
390   Cond.push_back(MachineOperand::CreateImm(LastInst.getOpcode()));
391   Cond.push_back(LastInst.getOperand(0));
392   Cond.push_back(LastInst.getOperand(1));
393 }
394 
395 static unsigned getOppositeBranchOpcode(int Opc) {
396   switch (Opc) {
397   default:
398     llvm_unreachable("Unrecognized conditional branch");
399   case RISCV::BEQ:
400     return RISCV::BNE;
401   case RISCV::BNE:
402     return RISCV::BEQ;
403   case RISCV::BLT:
404     return RISCV::BGE;
405   case RISCV::BGE:
406     return RISCV::BLT;
407   case RISCV::BLTU:
408     return RISCV::BGEU;
409   case RISCV::BGEU:
410     return RISCV::BLTU;
411   }
412 }
413 
414 bool RISCVInstrInfo::analyzeBranch(MachineBasicBlock &MBB,
415                                    MachineBasicBlock *&TBB,
416                                    MachineBasicBlock *&FBB,
417                                    SmallVectorImpl<MachineOperand> &Cond,
418                                    bool AllowModify) const {
419   TBB = FBB = nullptr;
420   Cond.clear();
421 
422   // If the block has no terminators, it just falls into the block after it.
423   MachineBasicBlock::iterator I = MBB.getLastNonDebugInstr();
424   if (I == MBB.end() || !isUnpredicatedTerminator(*I))
425     return false;
426 
427   // Count the number of terminators and find the first unconditional or
428   // indirect branch.
429   MachineBasicBlock::iterator FirstUncondOrIndirectBr = MBB.end();
430   int NumTerminators = 0;
431   for (auto J = I.getReverse(); J != MBB.rend() && isUnpredicatedTerminator(*J);
432        J++) {
433     NumTerminators++;
434     if (J->getDesc().isUnconditionalBranch() ||
435         J->getDesc().isIndirectBranch()) {
436       FirstUncondOrIndirectBr = J.getReverse();
437     }
438   }
439 
440   // If AllowModify is true, we can erase any terminators after
441   // FirstUncondOrIndirectBR.
442   if (AllowModify && FirstUncondOrIndirectBr != MBB.end()) {
443     while (std::next(FirstUncondOrIndirectBr) != MBB.end()) {
444       std::next(FirstUncondOrIndirectBr)->eraseFromParent();
445       NumTerminators--;
446     }
447     I = FirstUncondOrIndirectBr;
448   }
449 
450   // We can't handle blocks that end in an indirect branch.
451   if (I->getDesc().isIndirectBranch())
452     return true;
453 
454   // We can't handle blocks with more than 2 terminators.
455   if (NumTerminators > 2)
456     return true;
457 
458   // Handle a single unconditional branch.
459   if (NumTerminators == 1 && I->getDesc().isUnconditionalBranch()) {
460     TBB = getBranchDestBlock(*I);
461     return false;
462   }
463 
464   // Handle a single conditional branch.
465   if (NumTerminators == 1 && I->getDesc().isConditionalBranch()) {
466     parseCondBranch(*I, TBB, Cond);
467     return false;
468   }
469 
470   // Handle a conditional branch followed by an unconditional branch.
471   if (NumTerminators == 2 && std::prev(I)->getDesc().isConditionalBranch() &&
472       I->getDesc().isUnconditionalBranch()) {
473     parseCondBranch(*std::prev(I), TBB, Cond);
474     FBB = getBranchDestBlock(*I);
475     return false;
476   }
477 
478   // Otherwise, we can't handle this.
479   return true;
480 }
481 
482 unsigned RISCVInstrInfo::removeBranch(MachineBasicBlock &MBB,
483                                       int *BytesRemoved) const {
484   if (BytesRemoved)
485     *BytesRemoved = 0;
486   MachineBasicBlock::iterator I = MBB.getLastNonDebugInstr();
487   if (I == MBB.end())
488     return 0;
489 
490   if (!I->getDesc().isUnconditionalBranch() &&
491       !I->getDesc().isConditionalBranch())
492     return 0;
493 
494   // Remove the branch.
495   if (BytesRemoved)
496     *BytesRemoved += getInstSizeInBytes(*I);
497   I->eraseFromParent();
498 
499   I = MBB.end();
500 
501   if (I == MBB.begin())
502     return 1;
503   --I;
504   if (!I->getDesc().isConditionalBranch())
505     return 1;
506 
507   // Remove the branch.
508   if (BytesRemoved)
509     *BytesRemoved += getInstSizeInBytes(*I);
510   I->eraseFromParent();
511   return 2;
512 }
513 
514 // Inserts a branch into the end of the specific MachineBasicBlock, returning
515 // the number of instructions inserted.
516 unsigned RISCVInstrInfo::insertBranch(
517     MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB,
518     ArrayRef<MachineOperand> Cond, const DebugLoc &DL, int *BytesAdded) const {
519   if (BytesAdded)
520     *BytesAdded = 0;
521 
522   // Shouldn't be a fall through.
523   assert(TBB && "insertBranch must not be told to insert a fallthrough");
524   assert((Cond.size() == 3 || Cond.size() == 0) &&
525          "RISCV branch conditions have two components!");
526 
527   // Unconditional branch.
528   if (Cond.empty()) {
529     MachineInstr &MI = *BuildMI(&MBB, DL, get(RISCV::PseudoBR)).addMBB(TBB);
530     if (BytesAdded)
531       *BytesAdded += getInstSizeInBytes(MI);
532     return 1;
533   }
534 
535   // Either a one or two-way conditional branch.
536   unsigned Opc = Cond[0].getImm();
537   MachineInstr &CondMI =
538       *BuildMI(&MBB, DL, get(Opc)).add(Cond[1]).add(Cond[2]).addMBB(TBB);
539   if (BytesAdded)
540     *BytesAdded += getInstSizeInBytes(CondMI);
541 
542   // One-way conditional branch.
543   if (!FBB)
544     return 1;
545 
546   // Two-way conditional branch.
547   MachineInstr &MI = *BuildMI(&MBB, DL, get(RISCV::PseudoBR)).addMBB(FBB);
548   if (BytesAdded)
549     *BytesAdded += getInstSizeInBytes(MI);
550   return 2;
551 }
552 
553 unsigned RISCVInstrInfo::insertIndirectBranch(MachineBasicBlock &MBB,
554                                               MachineBasicBlock &DestBB,
555                                               const DebugLoc &DL,
556                                               int64_t BrOffset,
557                                               RegScavenger *RS) const {
558   assert(RS && "RegScavenger required for long branching");
559   assert(MBB.empty() &&
560          "new block should be inserted for expanding unconditional branch");
561   assert(MBB.pred_size() == 1);
562 
563   MachineFunction *MF = MBB.getParent();
564   MachineRegisterInfo &MRI = MF->getRegInfo();
565 
566   if (!isInt<32>(BrOffset))
567     report_fatal_error(
568         "Branch offsets outside of the signed 32-bit range not supported");
569 
570   // FIXME: A virtual register must be used initially, as the register
571   // scavenger won't work with empty blocks (SIInstrInfo::insertIndirectBranch
572   // uses the same workaround).
573   Register ScratchReg = MRI.createVirtualRegister(&RISCV::GPRRegClass);
574   auto II = MBB.end();
575 
576   MachineInstr &MI = *BuildMI(MBB, II, DL, get(RISCV::PseudoJump))
577                           .addReg(ScratchReg, RegState::Define | RegState::Dead)
578                           .addMBB(&DestBB, RISCVII::MO_CALL);
579 
580   RS->enterBasicBlockEnd(MBB);
581   unsigned Scav = RS->scavengeRegisterBackwards(RISCV::GPRRegClass,
582                                                 MI.getIterator(), false, 0);
583   MRI.replaceRegWith(ScratchReg, Scav);
584   MRI.clearVirtRegs();
585   RS->setRegUsed(Scav);
586   return 8;
587 }
588 
589 bool RISCVInstrInfo::reverseBranchCondition(
590     SmallVectorImpl<MachineOperand> &Cond) const {
591   assert((Cond.size() == 3) && "Invalid branch condition!");
592   Cond[0].setImm(getOppositeBranchOpcode(Cond[0].getImm()));
593   return false;
594 }
595 
596 MachineBasicBlock *
597 RISCVInstrInfo::getBranchDestBlock(const MachineInstr &MI) const {
598   assert(MI.getDesc().isBranch() && "Unexpected opcode!");
599   // The branch target is always the last operand.
600   int NumOp = MI.getNumExplicitOperands();
601   return MI.getOperand(NumOp - 1).getMBB();
602 }
603 
604 bool RISCVInstrInfo::isBranchOffsetInRange(unsigned BranchOp,
605                                            int64_t BrOffset) const {
606   unsigned XLen = STI.getXLen();
607   // Ideally we could determine the supported branch offset from the
608   // RISCVII::FormMask, but this can't be used for Pseudo instructions like
609   // PseudoBR.
610   switch (BranchOp) {
611   default:
612     llvm_unreachable("Unexpected opcode!");
613   case RISCV::BEQ:
614   case RISCV::BNE:
615   case RISCV::BLT:
616   case RISCV::BGE:
617   case RISCV::BLTU:
618   case RISCV::BGEU:
619     return isIntN(13, BrOffset);
620   case RISCV::JAL:
621   case RISCV::PseudoBR:
622     return isIntN(21, BrOffset);
623   case RISCV::PseudoJump:
624     return isIntN(32, SignExtend64(BrOffset + 0x800, XLen));
625   }
626 }
627 
628 unsigned RISCVInstrInfo::getInstSizeInBytes(const MachineInstr &MI) const {
629   unsigned Opcode = MI.getOpcode();
630 
631   switch (Opcode) {
632   default: {
633     if (MI.getParent() && MI.getParent()->getParent()) {
634       const auto MF = MI.getMF();
635       const auto &TM = static_cast<const RISCVTargetMachine &>(MF->getTarget());
636       const MCRegisterInfo &MRI = *TM.getMCRegisterInfo();
637       const MCSubtargetInfo &STI = *TM.getMCSubtargetInfo();
638       const RISCVSubtarget &ST = MF->getSubtarget<RISCVSubtarget>();
639       if (isCompressibleInst(MI, &ST, MRI, STI))
640         return 2;
641     }
642     return get(Opcode).getSize();
643   }
644   case TargetOpcode::EH_LABEL:
645   case TargetOpcode::IMPLICIT_DEF:
646   case TargetOpcode::KILL:
647   case TargetOpcode::DBG_VALUE:
648     return 0;
649   // These values are determined based on RISCVExpandAtomicPseudoInsts,
650   // RISCVExpandPseudoInsts and RISCVMCCodeEmitter, depending on where the
651   // pseudos are expanded.
652   case RISCV::PseudoCALLReg:
653   case RISCV::PseudoCALL:
654   case RISCV::PseudoJump:
655   case RISCV::PseudoTAIL:
656   case RISCV::PseudoLLA:
657   case RISCV::PseudoLA:
658   case RISCV::PseudoLA_TLS_IE:
659   case RISCV::PseudoLA_TLS_GD:
660     return 8;
661   case RISCV::PseudoAtomicLoadNand32:
662   case RISCV::PseudoAtomicLoadNand64:
663     return 20;
664   case RISCV::PseudoMaskedAtomicSwap32:
665   case RISCV::PseudoMaskedAtomicLoadAdd32:
666   case RISCV::PseudoMaskedAtomicLoadSub32:
667     return 28;
668   case RISCV::PseudoMaskedAtomicLoadNand32:
669     return 32;
670   case RISCV::PseudoMaskedAtomicLoadMax32:
671   case RISCV::PseudoMaskedAtomicLoadMin32:
672     return 44;
673   case RISCV::PseudoMaskedAtomicLoadUMax32:
674   case RISCV::PseudoMaskedAtomicLoadUMin32:
675     return 36;
676   case RISCV::PseudoCmpXchg32:
677   case RISCV::PseudoCmpXchg64:
678     return 16;
679   case RISCV::PseudoMaskedCmpXchg32:
680     return 32;
681   case TargetOpcode::INLINEASM:
682   case TargetOpcode::INLINEASM_BR: {
683     const MachineFunction &MF = *MI.getParent()->getParent();
684     const auto &TM = static_cast<const RISCVTargetMachine &>(MF.getTarget());
685     return getInlineAsmLength(MI.getOperand(0).getSymbolName(),
686                               *TM.getMCAsmInfo());
687   }
688   }
689 }
690 
691 bool RISCVInstrInfo::isAsCheapAsAMove(const MachineInstr &MI) const {
692   const unsigned Opcode = MI.getOpcode();
693   switch (Opcode) {
694   default:
695     break;
696   case RISCV::FSGNJ_D:
697   case RISCV::FSGNJ_S:
698     // The canonical floating-point move is fsgnj rd, rs, rs.
699     return MI.getOperand(1).isReg() && MI.getOperand(2).isReg() &&
700            MI.getOperand(1).getReg() == MI.getOperand(2).getReg();
701   case RISCV::ADDI:
702   case RISCV::ORI:
703   case RISCV::XORI:
704     return (MI.getOperand(1).isReg() &&
705             MI.getOperand(1).getReg() == RISCV::X0) ||
706            (MI.getOperand(2).isImm() && MI.getOperand(2).getImm() == 0);
707   }
708   return MI.isAsCheapAsAMove();
709 }
710 
711 Optional<DestSourcePair>
712 RISCVInstrInfo::isCopyInstrImpl(const MachineInstr &MI) const {
713   if (MI.isMoveReg())
714     return DestSourcePair{MI.getOperand(0), MI.getOperand(1)};
715   switch (MI.getOpcode()) {
716   default:
717     break;
718   case RISCV::ADDI:
719     // Operand 1 can be a frameindex but callers expect registers
720     if (MI.getOperand(1).isReg() && MI.getOperand(2).isImm() &&
721         MI.getOperand(2).getImm() == 0)
722       return DestSourcePair{MI.getOperand(0), MI.getOperand(1)};
723     break;
724   case RISCV::FSGNJ_D:
725   case RISCV::FSGNJ_S:
726     // The canonical floating-point move is fsgnj rd, rs, rs.
727     if (MI.getOperand(1).isReg() && MI.getOperand(2).isReg() &&
728         MI.getOperand(1).getReg() == MI.getOperand(2).getReg())
729       return DestSourcePair{MI.getOperand(0), MI.getOperand(1)};
730     break;
731   }
732   return None;
733 }
734 
735 bool RISCVInstrInfo::verifyInstruction(const MachineInstr &MI,
736                                        StringRef &ErrInfo) const {
737   const MCInstrInfo *MCII = STI.getInstrInfo();
738   MCInstrDesc const &Desc = MCII->get(MI.getOpcode());
739 
740   for (auto &OI : enumerate(Desc.operands())) {
741     unsigned OpType = OI.value().OperandType;
742     if (OpType >= RISCVOp::OPERAND_FIRST_RISCV_IMM &&
743         OpType <= RISCVOp::OPERAND_LAST_RISCV_IMM) {
744       const MachineOperand &MO = MI.getOperand(OI.index());
745       if (MO.isImm()) {
746         int64_t Imm = MO.getImm();
747         bool Ok;
748         switch (OpType) {
749         default:
750           llvm_unreachable("Unexpected operand type");
751         case RISCVOp::OPERAND_UIMM4:
752           Ok = isUInt<4>(Imm);
753           break;
754         case RISCVOp::OPERAND_UIMM5:
755           Ok = isUInt<5>(Imm);
756           break;
757         case RISCVOp::OPERAND_UIMM12:
758           Ok = isUInt<12>(Imm);
759           break;
760         case RISCVOp::OPERAND_SIMM12:
761           Ok = isInt<12>(Imm);
762           break;
763         case RISCVOp::OPERAND_UIMM20:
764           Ok = isUInt<20>(Imm);
765           break;
766         case RISCVOp::OPERAND_UIMMLOG2XLEN:
767           if (STI.getTargetTriple().isArch64Bit())
768             Ok = isUInt<6>(Imm);
769           else
770             Ok = isUInt<5>(Imm);
771           break;
772         }
773         if (!Ok) {
774           ErrInfo = "Invalid immediate";
775           return false;
776         }
777       }
778     }
779   }
780 
781   return true;
782 }
783 
784 // Return true if get the base operand, byte offset of an instruction and the
785 // memory width. Width is the size of memory that is being loaded/stored.
786 bool RISCVInstrInfo::getMemOperandWithOffsetWidth(
787     const MachineInstr &LdSt, const MachineOperand *&BaseReg, int64_t &Offset,
788     unsigned &Width, const TargetRegisterInfo *TRI) const {
789   if (!LdSt.mayLoadOrStore())
790     return false;
791 
792   // Here we assume the standard RISC-V ISA, which uses a base+offset
793   // addressing mode. You'll need to relax these conditions to support custom
794   // load/stores instructions.
795   if (LdSt.getNumExplicitOperands() != 3)
796     return false;
797   if (!LdSt.getOperand(1).isReg() || !LdSt.getOperand(2).isImm())
798     return false;
799 
800   if (!LdSt.hasOneMemOperand())
801     return false;
802 
803   Width = (*LdSt.memoperands_begin())->getSize();
804   BaseReg = &LdSt.getOperand(1);
805   Offset = LdSt.getOperand(2).getImm();
806   return true;
807 }
808 
809 bool RISCVInstrInfo::areMemAccessesTriviallyDisjoint(
810     const MachineInstr &MIa, const MachineInstr &MIb) const {
811   assert(MIa.mayLoadOrStore() && "MIa must be a load or store.");
812   assert(MIb.mayLoadOrStore() && "MIb must be a load or store.");
813 
814   if (MIa.hasUnmodeledSideEffects() || MIb.hasUnmodeledSideEffects() ||
815       MIa.hasOrderedMemoryRef() || MIb.hasOrderedMemoryRef())
816     return false;
817 
818   // Retrieve the base register, offset from the base register and width. Width
819   // is the size of memory that is being loaded/stored (e.g. 1, 2, 4).  If
820   // base registers are identical, and the offset of a lower memory access +
821   // the width doesn't overlap the offset of a higher memory access,
822   // then the memory accesses are different.
823   const TargetRegisterInfo *TRI = STI.getRegisterInfo();
824   const MachineOperand *BaseOpA = nullptr, *BaseOpB = nullptr;
825   int64_t OffsetA = 0, OffsetB = 0;
826   unsigned int WidthA = 0, WidthB = 0;
827   if (getMemOperandWithOffsetWidth(MIa, BaseOpA, OffsetA, WidthA, TRI) &&
828       getMemOperandWithOffsetWidth(MIb, BaseOpB, OffsetB, WidthB, TRI)) {
829     if (BaseOpA->isIdenticalTo(*BaseOpB)) {
830       int LowOffset = std::min(OffsetA, OffsetB);
831       int HighOffset = std::max(OffsetA, OffsetB);
832       int LowWidth = (LowOffset == OffsetA) ? WidthA : WidthB;
833       if (LowOffset + LowWidth <= HighOffset)
834         return true;
835     }
836   }
837   return false;
838 }
839 
840 std::pair<unsigned, unsigned>
841 RISCVInstrInfo::decomposeMachineOperandsTargetFlags(unsigned TF) const {
842   const unsigned Mask = RISCVII::MO_DIRECT_FLAG_MASK;
843   return std::make_pair(TF & Mask, TF & ~Mask);
844 }
845 
846 ArrayRef<std::pair<unsigned, const char *>>
847 RISCVInstrInfo::getSerializableDirectMachineOperandTargetFlags() const {
848   using namespace RISCVII;
849   static const std::pair<unsigned, const char *> TargetFlags[] = {
850       {MO_CALL, "riscv-call"},
851       {MO_PLT, "riscv-plt"},
852       {MO_LO, "riscv-lo"},
853       {MO_HI, "riscv-hi"},
854       {MO_PCREL_LO, "riscv-pcrel-lo"},
855       {MO_PCREL_HI, "riscv-pcrel-hi"},
856       {MO_GOT_HI, "riscv-got-hi"},
857       {MO_TPREL_LO, "riscv-tprel-lo"},
858       {MO_TPREL_HI, "riscv-tprel-hi"},
859       {MO_TPREL_ADD, "riscv-tprel-add"},
860       {MO_TLS_GOT_HI, "riscv-tls-got-hi"},
861       {MO_TLS_GD_HI, "riscv-tls-gd-hi"}};
862   return makeArrayRef(TargetFlags);
863 }
864 bool RISCVInstrInfo::isFunctionSafeToOutlineFrom(
865     MachineFunction &MF, bool OutlineFromLinkOnceODRs) const {
866   const Function &F = MF.getFunction();
867 
868   // Can F be deduplicated by the linker? If it can, don't outline from it.
869   if (!OutlineFromLinkOnceODRs && F.hasLinkOnceODRLinkage())
870     return false;
871 
872   // Don't outline from functions with section markings; the program could
873   // expect that all the code is in the named section.
874   if (F.hasSection())
875     return false;
876 
877   // It's safe to outline from MF.
878   return true;
879 }
880 
881 bool RISCVInstrInfo::isMBBSafeToOutlineFrom(MachineBasicBlock &MBB,
882                                             unsigned &Flags) const {
883   // More accurate safety checking is done in getOutliningCandidateInfo.
884   return true;
885 }
886 
887 // Enum values indicating how an outlined call should be constructed.
888 enum MachineOutlinerConstructionID {
889   MachineOutlinerDefault
890 };
891 
892 outliner::OutlinedFunction RISCVInstrInfo::getOutliningCandidateInfo(
893     std::vector<outliner::Candidate> &RepeatedSequenceLocs) const {
894 
895   // First we need to filter out candidates where the X5 register (IE t0) can't
896   // be used to setup the function call.
897   auto CannotInsertCall = [](outliner::Candidate &C) {
898     const TargetRegisterInfo *TRI = C.getMF()->getSubtarget().getRegisterInfo();
899 
900     C.initLRU(*TRI);
901     LiveRegUnits LRU = C.LRU;
902     return !LRU.available(RISCV::X5);
903   };
904 
905   llvm::erase_if(RepeatedSequenceLocs, CannotInsertCall);
906 
907   // If the sequence doesn't have enough candidates left, then we're done.
908   if (RepeatedSequenceLocs.size() < 2)
909     return outliner::OutlinedFunction();
910 
911   unsigned SequenceSize = 0;
912 
913   auto I = RepeatedSequenceLocs[0].front();
914   auto E = std::next(RepeatedSequenceLocs[0].back());
915   for (; I != E; ++I)
916     SequenceSize += getInstSizeInBytes(*I);
917 
918   // call t0, function = 8 bytes.
919   unsigned CallOverhead = 8;
920   for (auto &C : RepeatedSequenceLocs)
921     C.setCallInfo(MachineOutlinerDefault, CallOverhead);
922 
923   // jr t0 = 4 bytes, 2 bytes if compressed instructions are enabled.
924   unsigned FrameOverhead = 4;
925   if (RepeatedSequenceLocs[0].getMF()->getSubtarget()
926           .getFeatureBits()[RISCV::FeatureStdExtC])
927     FrameOverhead = 2;
928 
929   return outliner::OutlinedFunction(RepeatedSequenceLocs, SequenceSize,
930                                     FrameOverhead, MachineOutlinerDefault);
931 }
932 
933 outliner::InstrType
934 RISCVInstrInfo::getOutliningType(MachineBasicBlock::iterator &MBBI,
935                                  unsigned Flags) const {
936   MachineInstr &MI = *MBBI;
937   MachineBasicBlock *MBB = MI.getParent();
938   const TargetRegisterInfo *TRI =
939       MBB->getParent()->getSubtarget().getRegisterInfo();
940 
941   // Positions generally can't safely be outlined.
942   if (MI.isPosition()) {
943     // We can manually strip out CFI instructions later.
944     if (MI.isCFIInstruction())
945       return outliner::InstrType::Invisible;
946 
947     return outliner::InstrType::Illegal;
948   }
949 
950   // Don't trust the user to write safe inline assembly.
951   if (MI.isInlineAsm())
952     return outliner::InstrType::Illegal;
953 
954   // We can't outline branches to other basic blocks.
955   if (MI.isTerminator() && !MBB->succ_empty())
956     return outliner::InstrType::Illegal;
957 
958   // We need support for tail calls to outlined functions before return
959   // statements can be allowed.
960   if (MI.isReturn())
961     return outliner::InstrType::Illegal;
962 
963   // Don't allow modifying the X5 register which we use for return addresses for
964   // these outlined functions.
965   if (MI.modifiesRegister(RISCV::X5, TRI) ||
966       MI.getDesc().hasImplicitDefOfPhysReg(RISCV::X5))
967     return outliner::InstrType::Illegal;
968 
969   // Make sure the operands don't reference something unsafe.
970   for (const auto &MO : MI.operands())
971     if (MO.isMBB() || MO.isBlockAddress() || MO.isCPI())
972       return outliner::InstrType::Illegal;
973 
974   // Don't allow instructions which won't be materialized to impact outlining
975   // analysis.
976   if (MI.isMetaInstruction())
977     return outliner::InstrType::Invisible;
978 
979   return outliner::InstrType::Legal;
980 }
981 
982 void RISCVInstrInfo::buildOutlinedFrame(
983     MachineBasicBlock &MBB, MachineFunction &MF,
984     const outliner::OutlinedFunction &OF) const {
985 
986   // Strip out any CFI instructions
987   bool Changed = true;
988   while (Changed) {
989     Changed = false;
990     auto I = MBB.begin();
991     auto E = MBB.end();
992     for (; I != E; ++I) {
993       if (I->isCFIInstruction()) {
994         I->removeFromParent();
995         Changed = true;
996         break;
997       }
998     }
999   }
1000 
1001   MBB.addLiveIn(RISCV::X5);
1002 
1003   // Add in a return instruction to the end of the outlined frame.
1004   MBB.insert(MBB.end(), BuildMI(MF, DebugLoc(), get(RISCV::JALR))
1005       .addReg(RISCV::X0, RegState::Define)
1006       .addReg(RISCV::X5)
1007       .addImm(0));
1008 }
1009 
1010 MachineBasicBlock::iterator RISCVInstrInfo::insertOutlinedCall(
1011     Module &M, MachineBasicBlock &MBB, MachineBasicBlock::iterator &It,
1012     MachineFunction &MF, const outliner::Candidate &C) const {
1013 
1014   // Add in a call instruction to the outlined function at the given location.
1015   It = MBB.insert(It,
1016                   BuildMI(MF, DebugLoc(), get(RISCV::PseudoCALLReg), RISCV::X5)
1017                       .addGlobalAddress(M.getNamedValue(MF.getName()), 0,
1018                                         RISCVII::MO_CALL));
1019   return It;
1020 }
1021 
1022 // clang-format off
1023 #define CASE_VFMA_OPCODE_COMMON(OP, TYPE, LMUL)                                \
1024   RISCV::PseudoV##OP##_##TYPE##_##LMUL##_COMMUTABLE
1025 
1026 #define CASE_VFMA_OPCODE_LMULS(OP, TYPE)                                       \
1027   CASE_VFMA_OPCODE_COMMON(OP, TYPE, MF8):                                      \
1028   case CASE_VFMA_OPCODE_COMMON(OP, TYPE, MF4):                                 \
1029   case CASE_VFMA_OPCODE_COMMON(OP, TYPE, MF2):                                 \
1030   case CASE_VFMA_OPCODE_COMMON(OP, TYPE, M1):                                  \
1031   case CASE_VFMA_OPCODE_COMMON(OP, TYPE, M2):                                  \
1032   case CASE_VFMA_OPCODE_COMMON(OP, TYPE, M4):                                  \
1033   case CASE_VFMA_OPCODE_COMMON(OP, TYPE, M8)
1034 
1035 #define CASE_VFMA_SPLATS(OP)                                                   \
1036   CASE_VFMA_OPCODE_LMULS(OP, VF16):                                            \
1037   case CASE_VFMA_OPCODE_LMULS(OP, VF32):                                       \
1038   case CASE_VFMA_OPCODE_LMULS(OP, VF64)
1039 // clang-format on
1040 
1041 bool RISCVInstrInfo::findCommutedOpIndices(const MachineInstr &MI,
1042                                            unsigned &SrcOpIdx1,
1043                                            unsigned &SrcOpIdx2) const {
1044   const MCInstrDesc &Desc = MI.getDesc();
1045   if (!Desc.isCommutable())
1046     return false;
1047 
1048   switch (MI.getOpcode()) {
1049   case CASE_VFMA_SPLATS(FMADD):
1050   case CASE_VFMA_SPLATS(FMSUB):
1051   case CASE_VFMA_SPLATS(FMACC):
1052   case CASE_VFMA_SPLATS(FMSAC):
1053   case CASE_VFMA_SPLATS(FNMADD):
1054   case CASE_VFMA_SPLATS(FNMSUB):
1055   case CASE_VFMA_SPLATS(FNMACC):
1056   case CASE_VFMA_SPLATS(FNMSAC):
1057   case CASE_VFMA_OPCODE_LMULS(FMACC, VV):
1058   case CASE_VFMA_OPCODE_LMULS(FMSAC, VV):
1059   case CASE_VFMA_OPCODE_LMULS(FNMACC, VV):
1060   case CASE_VFMA_OPCODE_LMULS(FNMSAC, VV): {
1061     // For these instructions we can only swap operand 1 and operand 3 by
1062     // changing the opcode.
1063     unsigned CommutableOpIdx1 = 1;
1064     unsigned CommutableOpIdx2 = 3;
1065     if (!fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2, CommutableOpIdx1,
1066                               CommutableOpIdx2))
1067       return false;
1068     return true;
1069   }
1070   case CASE_VFMA_OPCODE_LMULS(FMADD, VV):
1071   case CASE_VFMA_OPCODE_LMULS(FMSUB, VV):
1072   case CASE_VFMA_OPCODE_LMULS(FNMADD, VV):
1073   case CASE_VFMA_OPCODE_LMULS(FNMSUB, VV): {
1074     // For these instructions we have more freedom. We can commute with the
1075     // other multiplicand or with the addend/subtrahend/minuend.
1076 
1077     // Any fixed operand must be from source 1, 2 or 3.
1078     if (SrcOpIdx1 != CommuteAnyOperandIndex && SrcOpIdx1 > 3)
1079       return false;
1080     if (SrcOpIdx2 != CommuteAnyOperandIndex && SrcOpIdx2 > 3)
1081       return false;
1082 
1083     // It both ops are fixed one must be the tied source.
1084     if (SrcOpIdx1 != CommuteAnyOperandIndex &&
1085         SrcOpIdx2 != CommuteAnyOperandIndex && SrcOpIdx1 != 1 && SrcOpIdx2 != 1)
1086       return false;
1087 
1088     // Look for two different register operands assumed to be commutable
1089     // regardless of the FMA opcode. The FMA opcode is adjusted later if
1090     // needed.
1091     if (SrcOpIdx1 == CommuteAnyOperandIndex ||
1092         SrcOpIdx2 == CommuteAnyOperandIndex) {
1093       // At least one of operands to be commuted is not specified and
1094       // this method is free to choose appropriate commutable operands.
1095       unsigned CommutableOpIdx1 = SrcOpIdx1;
1096       if (SrcOpIdx1 == SrcOpIdx2) {
1097         // Both of operands are not fixed. Set one of commutable
1098         // operands to the tied source.
1099         CommutableOpIdx1 = 1;
1100       } else if (SrcOpIdx1 == CommutableOpIdx1) {
1101         // Only one of the operands is not fixed.
1102         CommutableOpIdx1 = SrcOpIdx2;
1103       }
1104 
1105       // CommutableOpIdx1 is well defined now. Let's choose another commutable
1106       // operand and assign its index to CommutableOpIdx2.
1107       unsigned CommutableOpIdx2;
1108       if (CommutableOpIdx1 != 1) {
1109         // If we haven't already used the tied source, we must use it now.
1110         CommutableOpIdx2 = 1;
1111       } else {
1112         Register Op1Reg = MI.getOperand(CommutableOpIdx1).getReg();
1113 
1114         // The commuted operands should have different registers.
1115         // Otherwise, the commute transformation does not change anything and
1116         // is useless. We use this as a hint to make our decision.
1117         if (Op1Reg != MI.getOperand(2).getReg())
1118           CommutableOpIdx2 = 2;
1119         else
1120           CommutableOpIdx2 = 3;
1121       }
1122 
1123       // Assign the found pair of commutable indices to SrcOpIdx1 and
1124       // SrcOpIdx2 to return those values.
1125       if (!fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2, CommutableOpIdx1,
1126                                 CommutableOpIdx2))
1127         return false;
1128     }
1129 
1130     return true;
1131   }
1132   }
1133 
1134   return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
1135 }
1136 
1137 #define CASE_VFMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, LMUL)               \
1138   case RISCV::PseudoV##OLDOP##_##TYPE##_##LMUL##_COMMUTABLE:                   \
1139     Opc = RISCV::PseudoV##NEWOP##_##TYPE##_##LMUL##_COMMUTABLE;                \
1140     break;
1141 
1142 #define CASE_VFMA_CHANGE_OPCODE_LMULS(OLDOP, NEWOP, TYPE)                      \
1143   CASE_VFMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, MF8)                      \
1144   CASE_VFMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, MF4)                      \
1145   CASE_VFMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, MF2)                      \
1146   CASE_VFMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, M1)                       \
1147   CASE_VFMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, M2)                       \
1148   CASE_VFMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, M4)                       \
1149   CASE_VFMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, M8)
1150 
1151 #define CASE_VFMA_CHANGE_OPCODE_SPLATS(OLDOP, NEWOP)                           \
1152   CASE_VFMA_CHANGE_OPCODE_LMULS(OLDOP, NEWOP, VF16)                            \
1153   CASE_VFMA_CHANGE_OPCODE_LMULS(OLDOP, NEWOP, VF32)                            \
1154   CASE_VFMA_CHANGE_OPCODE_LMULS(OLDOP, NEWOP, VF64)
1155 
1156 MachineInstr *RISCVInstrInfo::commuteInstructionImpl(MachineInstr &MI,
1157                                                      bool NewMI,
1158                                                      unsigned OpIdx1,
1159                                                      unsigned OpIdx2) const {
1160   auto cloneIfNew = [NewMI](MachineInstr &MI) -> MachineInstr & {
1161     if (NewMI)
1162       return *MI.getParent()->getParent()->CloneMachineInstr(&MI);
1163     return MI;
1164   };
1165 
1166   switch (MI.getOpcode()) {
1167   case CASE_VFMA_SPLATS(FMACC):
1168   case CASE_VFMA_SPLATS(FMADD):
1169   case CASE_VFMA_SPLATS(FMSAC):
1170   case CASE_VFMA_SPLATS(FMSUB):
1171   case CASE_VFMA_SPLATS(FNMACC):
1172   case CASE_VFMA_SPLATS(FNMADD):
1173   case CASE_VFMA_SPLATS(FNMSAC):
1174   case CASE_VFMA_SPLATS(FNMSUB):
1175   case CASE_VFMA_OPCODE_LMULS(FMACC, VV):
1176   case CASE_VFMA_OPCODE_LMULS(FMSAC, VV):
1177   case CASE_VFMA_OPCODE_LMULS(FNMACC, VV):
1178   case CASE_VFMA_OPCODE_LMULS(FNMSAC, VV): {
1179     // It only make sense to toggle these between clobbering the
1180     // addend/subtrahend/minuend one of the multiplicands.
1181     assert((OpIdx1 == 1 || OpIdx2 == 1) && "Unexpected opcode index");
1182     assert((OpIdx1 == 3 || OpIdx2 == 3) && "Unexpected opcode index");
1183     unsigned Opc;
1184     switch (MI.getOpcode()) {
1185       default:
1186         llvm_unreachable("Unexpected opcode");
1187       CASE_VFMA_CHANGE_OPCODE_SPLATS(FMACC, FMADD)
1188       CASE_VFMA_CHANGE_OPCODE_SPLATS(FMADD, FMACC)
1189       CASE_VFMA_CHANGE_OPCODE_SPLATS(FMSAC, FMSUB)
1190       CASE_VFMA_CHANGE_OPCODE_SPLATS(FMSUB, FMSAC)
1191       CASE_VFMA_CHANGE_OPCODE_SPLATS(FNMACC, FNMADD)
1192       CASE_VFMA_CHANGE_OPCODE_SPLATS(FNMADD, FNMACC)
1193       CASE_VFMA_CHANGE_OPCODE_SPLATS(FNMSAC, FNMSUB)
1194       CASE_VFMA_CHANGE_OPCODE_SPLATS(FNMSUB, FNMSAC)
1195       CASE_VFMA_CHANGE_OPCODE_LMULS(FMACC, FMADD, VV)
1196       CASE_VFMA_CHANGE_OPCODE_LMULS(FMSAC, FMSUB, VV)
1197       CASE_VFMA_CHANGE_OPCODE_LMULS(FNMACC, FNMADD, VV)
1198       CASE_VFMA_CHANGE_OPCODE_LMULS(FNMSAC, FNMSUB, VV)
1199     }
1200 
1201     auto &WorkingMI = cloneIfNew(MI);
1202     WorkingMI.setDesc(get(Opc));
1203     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
1204                                                    OpIdx1, OpIdx2);
1205   }
1206   case CASE_VFMA_OPCODE_LMULS(FMADD, VV):
1207   case CASE_VFMA_OPCODE_LMULS(FMSUB, VV):
1208   case CASE_VFMA_OPCODE_LMULS(FNMADD, VV):
1209   case CASE_VFMA_OPCODE_LMULS(FNMSUB, VV): {
1210     assert((OpIdx1 == 1 || OpIdx2 == 1) && "Unexpected opcode index");
1211     // If one of the operands, is the addend we need to change opcode.
1212     // Otherwise we're just swapping 2 of the multiplicands.
1213     if (OpIdx1 == 3 || OpIdx2 == 3) {
1214       unsigned Opc;
1215       switch (MI.getOpcode()) {
1216         default:
1217           llvm_unreachable("Unexpected opcode");
1218         CASE_VFMA_CHANGE_OPCODE_LMULS(FMADD, FMACC, VV)
1219         CASE_VFMA_CHANGE_OPCODE_LMULS(FMSUB, FMSAC, VV)
1220         CASE_VFMA_CHANGE_OPCODE_LMULS(FNMADD, FNMACC, VV)
1221         CASE_VFMA_CHANGE_OPCODE_LMULS(FNMSUB, FNMSAC, VV)
1222       }
1223 
1224       auto &WorkingMI = cloneIfNew(MI);
1225       WorkingMI.setDesc(get(Opc));
1226       return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
1227                                                      OpIdx1, OpIdx2);
1228     }
1229     // Let the default code handle it.
1230     break;
1231   }
1232   }
1233 
1234   return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
1235 }
1236 
1237 #undef CASE_VFMA_CHANGE_OPCODE_SPLATS
1238 #undef CASE_VFMA_CHANGE_OPCODE_LMULS
1239 #undef CASE_VFMA_CHANGE_OPCODE_COMMON
1240 #undef CASE_VFMA_SPLATS
1241 #undef CASE_VFMA_OPCODE_LMULS
1242 #undef CASE_VFMA_OPCODE_COMMON
1243 
1244 Register RISCVInstrInfo::getVLENFactoredAmount(MachineFunction &MF,
1245                                                MachineBasicBlock &MBB,
1246                                                MachineBasicBlock::iterator II,
1247                                                int64_t Amount) const {
1248   assert(Amount > 0 && "There is no need to get VLEN scaled value.");
1249   assert(Amount % 8 == 0 &&
1250          "Reserve the stack by the multiple of one vector size.");
1251 
1252   MachineRegisterInfo &MRI = MF.getRegInfo();
1253   const RISCVInstrInfo *TII = MF.getSubtarget<RISCVSubtarget>().getInstrInfo();
1254   DebugLoc DL = II->getDebugLoc();
1255   int64_t NumOfVReg = Amount / 8;
1256 
1257   Register SizeOfVector = MRI.createVirtualRegister(&RISCV::GPRRegClass);
1258   BuildMI(MBB, II, DL, TII->get(RISCV::PseudoReadVLENB), SizeOfVector);
1259   Register FactorRegister = MRI.createVirtualRegister(&RISCV::GPRRegClass);
1260   assert(isInt<12>(NumOfVReg) &&
1261          "Expect the number of vector registers within 12-bits.");
1262   if (isPowerOf2_32(NumOfVReg)) {
1263     uint32_t ShiftAmount = Log2_32(NumOfVReg);
1264     if (ShiftAmount == 0)
1265       return SizeOfVector;
1266     BuildMI(MBB, II, DL, TII->get(RISCV::SLLI), FactorRegister)
1267         .addReg(SizeOfVector, RegState::Kill)
1268         .addImm(ShiftAmount);
1269   } else {
1270     Register VN = MRI.createVirtualRegister(&RISCV::GPRRegClass);
1271     BuildMI(MBB, II, DL, TII->get(RISCV::ADDI), VN)
1272         .addReg(RISCV::X0)
1273         .addImm(NumOfVReg);
1274     if (!MF.getSubtarget<RISCVSubtarget>().hasStdExtM())
1275       MF.getFunction().getContext().diagnose(DiagnosticInfoUnsupported{
1276           MF.getFunction(),
1277           "M-extension must be enabled to calculate the vscaled size/offset."});
1278     BuildMI(MBB, II, DL, TII->get(RISCV::MUL), FactorRegister)
1279         .addReg(SizeOfVector, RegState::Kill)
1280         .addReg(VN, RegState::Kill);
1281   }
1282 
1283   return FactorRegister;
1284 }
1285 
1286 Optional<std::pair<unsigned, unsigned>>
1287 RISCVInstrInfo::isRVVSpillForZvlsseg(unsigned Opcode) const {
1288   switch (Opcode) {
1289   default:
1290     return None;
1291   case RISCV::PseudoVSPILL2_M1:
1292   case RISCV::PseudoVRELOAD2_M1:
1293     return std::make_pair(2u, 1u);
1294   case RISCV::PseudoVSPILL2_M2:
1295   case RISCV::PseudoVRELOAD2_M2:
1296     return std::make_pair(2u, 2u);
1297   case RISCV::PseudoVSPILL2_M4:
1298   case RISCV::PseudoVRELOAD2_M4:
1299     return std::make_pair(2u, 4u);
1300   case RISCV::PseudoVSPILL3_M1:
1301   case RISCV::PseudoVRELOAD3_M1:
1302     return std::make_pair(3u, 1u);
1303   case RISCV::PseudoVSPILL3_M2:
1304   case RISCV::PseudoVRELOAD3_M2:
1305     return std::make_pair(3u, 2u);
1306   case RISCV::PseudoVSPILL4_M1:
1307   case RISCV::PseudoVRELOAD4_M1:
1308     return std::make_pair(4u, 1u);
1309   case RISCV::PseudoVSPILL4_M2:
1310   case RISCV::PseudoVRELOAD4_M2:
1311     return std::make_pair(4u, 2u);
1312   case RISCV::PseudoVSPILL5_M1:
1313   case RISCV::PseudoVRELOAD5_M1:
1314     return std::make_pair(5u, 1u);
1315   case RISCV::PseudoVSPILL6_M1:
1316   case RISCV::PseudoVRELOAD6_M1:
1317     return std::make_pair(6u, 1u);
1318   case RISCV::PseudoVSPILL7_M1:
1319   case RISCV::PseudoVRELOAD7_M1:
1320     return std::make_pair(7u, 1u);
1321   case RISCV::PseudoVSPILL8_M1:
1322   case RISCV::PseudoVRELOAD8_M1:
1323     return std::make_pair(8u, 1u);
1324   }
1325 }
1326