1 //===-- RISCVInstrInfo.cpp - RISCV Instruction Information ------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the RISCV implementation of the TargetInstrInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "RISCVInstrInfo.h"
14 #include "RISCV.h"
15 #include "RISCVSubtarget.h"
16 #include "RISCVTargetMachine.h"
17 #include "Utils/RISCVMatInt.h"
18 #include "llvm/ADT/STLExtras.h"
19 #include "llvm/ADT/SmallVector.h"
20 #include "llvm/CodeGen/MachineFunctionPass.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/CodeGen/RegisterScavenging.h"
24 #include "llvm/Support/ErrorHandling.h"
25 #include "llvm/Support/TargetRegistry.h"
26 
27 #define GET_INSTRINFO_CTOR_DTOR
28 #include "RISCVGenInstrInfo.inc"
29 
30 using namespace llvm;
31 
32 RISCVInstrInfo::RISCVInstrInfo()
33     : RISCVGenInstrInfo(RISCV::ADJCALLSTACKDOWN, RISCV::ADJCALLSTACKUP) {}
34 
35 unsigned RISCVInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
36                                              int &FrameIndex) const {
37   switch (MI.getOpcode()) {
38   default:
39     return 0;
40   case RISCV::LB:
41   case RISCV::LBU:
42   case RISCV::LH:
43   case RISCV::LHU:
44   case RISCV::LW:
45   case RISCV::FLW:
46   case RISCV::LWU:
47   case RISCV::LD:
48   case RISCV::FLD:
49     break;
50   }
51 
52   if (MI.getOperand(1).isFI() && MI.getOperand(2).isImm() &&
53       MI.getOperand(2).getImm() == 0) {
54     FrameIndex = MI.getOperand(1).getIndex();
55     return MI.getOperand(0).getReg();
56   }
57 
58   return 0;
59 }
60 
61 unsigned RISCVInstrInfo::isStoreToStackSlot(const MachineInstr &MI,
62                                             int &FrameIndex) const {
63   switch (MI.getOpcode()) {
64   default:
65     return 0;
66   case RISCV::SB:
67   case RISCV::SH:
68   case RISCV::SW:
69   case RISCV::FSW:
70   case RISCV::SD:
71   case RISCV::FSD:
72     break;
73   }
74 
75   if (MI.getOperand(0).isFI() && MI.getOperand(1).isImm() &&
76       MI.getOperand(1).getImm() == 0) {
77     FrameIndex = MI.getOperand(0).getIndex();
78     return MI.getOperand(2).getReg();
79   }
80 
81   return 0;
82 }
83 
84 void RISCVInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
85                                  MachineBasicBlock::iterator MBBI,
86                                  const DebugLoc &DL, unsigned DstReg,
87                                  unsigned SrcReg, bool KillSrc) const {
88   if (RISCV::GPRRegClass.contains(DstReg, SrcReg)) {
89     BuildMI(MBB, MBBI, DL, get(RISCV::ADDI), DstReg)
90         .addReg(SrcReg, getKillRegState(KillSrc))
91         .addImm(0);
92     return;
93   }
94 
95   // FPR->FPR copies
96   unsigned Opc;
97   if (RISCV::FPR32RegClass.contains(DstReg, SrcReg))
98     Opc = RISCV::FSGNJ_S;
99   else if (RISCV::FPR64RegClass.contains(DstReg, SrcReg))
100     Opc = RISCV::FSGNJ_D;
101   else
102     llvm_unreachable("Impossible reg-to-reg copy");
103 
104   BuildMI(MBB, MBBI, DL, get(Opc), DstReg)
105       .addReg(SrcReg, getKillRegState(KillSrc))
106       .addReg(SrcReg, getKillRegState(KillSrc));
107 }
108 
109 void RISCVInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
110                                          MachineBasicBlock::iterator I,
111                                          unsigned SrcReg, bool IsKill, int FI,
112                                          const TargetRegisterClass *RC,
113                                          const TargetRegisterInfo *TRI) const {
114   DebugLoc DL;
115   if (I != MBB.end())
116     DL = I->getDebugLoc();
117 
118   unsigned Opcode;
119 
120   if (RISCV::GPRRegClass.hasSubClassEq(RC))
121     Opcode = TRI->getRegSizeInBits(RISCV::GPRRegClass) == 32 ?
122              RISCV::SW : RISCV::SD;
123   else if (RISCV::FPR32RegClass.hasSubClassEq(RC))
124     Opcode = RISCV::FSW;
125   else if (RISCV::FPR64RegClass.hasSubClassEq(RC))
126     Opcode = RISCV::FSD;
127   else
128     llvm_unreachable("Can't store this register to stack slot");
129 
130   BuildMI(MBB, I, DL, get(Opcode))
131       .addReg(SrcReg, getKillRegState(IsKill))
132       .addFrameIndex(FI)
133       .addImm(0);
134 }
135 
136 void RISCVInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
137                                           MachineBasicBlock::iterator I,
138                                           unsigned DstReg, int FI,
139                                           const TargetRegisterClass *RC,
140                                           const TargetRegisterInfo *TRI) const {
141   DebugLoc DL;
142   if (I != MBB.end())
143     DL = I->getDebugLoc();
144 
145   unsigned Opcode;
146 
147   if (RISCV::GPRRegClass.hasSubClassEq(RC))
148     Opcode = TRI->getRegSizeInBits(RISCV::GPRRegClass) == 32 ?
149              RISCV::LW : RISCV::LD;
150   else if (RISCV::FPR32RegClass.hasSubClassEq(RC))
151     Opcode = RISCV::FLW;
152   else if (RISCV::FPR64RegClass.hasSubClassEq(RC))
153     Opcode = RISCV::FLD;
154   else
155     llvm_unreachable("Can't load this register from stack slot");
156 
157   BuildMI(MBB, I, DL, get(Opcode), DstReg).addFrameIndex(FI).addImm(0);
158 }
159 
160 void RISCVInstrInfo::movImm(MachineBasicBlock &MBB,
161                             MachineBasicBlock::iterator MBBI,
162                             const DebugLoc &DL, Register DstReg, uint64_t Val,
163                             MachineInstr::MIFlag Flag) const {
164   MachineFunction *MF = MBB.getParent();
165   MachineRegisterInfo &MRI = MF->getRegInfo();
166   bool IsRV64 = MF->getSubtarget<RISCVSubtarget>().is64Bit();
167   Register SrcReg = RISCV::X0;
168   Register Result = MRI.createVirtualRegister(&RISCV::GPRRegClass);
169   unsigned Num = 0;
170 
171   if (!IsRV64 && !isInt<32>(Val))
172     report_fatal_error("Should only materialize 32-bit constants for RV32");
173 
174   RISCVMatInt::InstSeq Seq;
175   RISCVMatInt::generateInstSeq(Val, IsRV64, Seq);
176   assert(Seq.size() > 0);
177 
178   for (RISCVMatInt::Inst &Inst : Seq) {
179     // Write the final result to DstReg if it's the last instruction in the Seq.
180     // Otherwise, write the result to the temp register.
181     if (++Num == Seq.size())
182       Result = DstReg;
183 
184     if (Inst.Opc == RISCV::LUI) {
185       BuildMI(MBB, MBBI, DL, get(RISCV::LUI), Result)
186           .addImm(Inst.Imm)
187           .setMIFlag(Flag);
188     } else {
189       BuildMI(MBB, MBBI, DL, get(Inst.Opc), Result)
190           .addReg(SrcReg, RegState::Kill)
191           .addImm(Inst.Imm)
192           .setMIFlag(Flag);
193     }
194     // Only the first instruction has X0 as its source.
195     SrcReg = Result;
196   }
197 }
198 
199 // The contents of values added to Cond are not examined outside of
200 // RISCVInstrInfo, giving us flexibility in what to push to it. For RISCV, we
201 // push BranchOpcode, Reg1, Reg2.
202 static void parseCondBranch(MachineInstr &LastInst, MachineBasicBlock *&Target,
203                             SmallVectorImpl<MachineOperand> &Cond) {
204   // Block ends with fall-through condbranch.
205   assert(LastInst.getDesc().isConditionalBranch() &&
206          "Unknown conditional branch");
207   Target = LastInst.getOperand(2).getMBB();
208   Cond.push_back(MachineOperand::CreateImm(LastInst.getOpcode()));
209   Cond.push_back(LastInst.getOperand(0));
210   Cond.push_back(LastInst.getOperand(1));
211 }
212 
213 static unsigned getOppositeBranchOpcode(int Opc) {
214   switch (Opc) {
215   default:
216     llvm_unreachable("Unrecognized conditional branch");
217   case RISCV::BEQ:
218     return RISCV::BNE;
219   case RISCV::BNE:
220     return RISCV::BEQ;
221   case RISCV::BLT:
222     return RISCV::BGE;
223   case RISCV::BGE:
224     return RISCV::BLT;
225   case RISCV::BLTU:
226     return RISCV::BGEU;
227   case RISCV::BGEU:
228     return RISCV::BLTU;
229   }
230 }
231 
232 bool RISCVInstrInfo::analyzeBranch(MachineBasicBlock &MBB,
233                                    MachineBasicBlock *&TBB,
234                                    MachineBasicBlock *&FBB,
235                                    SmallVectorImpl<MachineOperand> &Cond,
236                                    bool AllowModify) const {
237   TBB = FBB = nullptr;
238   Cond.clear();
239 
240   // If the block has no terminators, it just falls into the block after it.
241   MachineBasicBlock::iterator I = MBB.getLastNonDebugInstr();
242   if (I == MBB.end() || !isUnpredicatedTerminator(*I))
243     return false;
244 
245   // Count the number of terminators and find the first unconditional or
246   // indirect branch.
247   MachineBasicBlock::iterator FirstUncondOrIndirectBr = MBB.end();
248   int NumTerminators = 0;
249   for (auto J = I.getReverse(); J != MBB.rend() && isUnpredicatedTerminator(*J);
250        J++) {
251     NumTerminators++;
252     if (J->getDesc().isUnconditionalBranch() ||
253         J->getDesc().isIndirectBranch()) {
254       FirstUncondOrIndirectBr = J.getReverse();
255     }
256   }
257 
258   // If AllowModify is true, we can erase any terminators after
259   // FirstUncondOrIndirectBR.
260   if (AllowModify && FirstUncondOrIndirectBr != MBB.end()) {
261     while (std::next(FirstUncondOrIndirectBr) != MBB.end()) {
262       std::next(FirstUncondOrIndirectBr)->eraseFromParent();
263       NumTerminators--;
264     }
265     I = FirstUncondOrIndirectBr;
266   }
267 
268   // We can't handle blocks that end in an indirect branch.
269   if (I->getDesc().isIndirectBranch())
270     return true;
271 
272   // We can't handle blocks with more than 2 terminators.
273   if (NumTerminators > 2)
274     return true;
275 
276   // Handle a single unconditional branch.
277   if (NumTerminators == 1 && I->getDesc().isUnconditionalBranch()) {
278     TBB = I->getOperand(0).getMBB();
279     return false;
280   }
281 
282   // Handle a single conditional branch.
283   if (NumTerminators == 1 && I->getDesc().isConditionalBranch()) {
284     parseCondBranch(*I, TBB, Cond);
285     return false;
286   }
287 
288   // Handle a conditional branch followed by an unconditional branch.
289   if (NumTerminators == 2 && std::prev(I)->getDesc().isConditionalBranch() &&
290       I->getDesc().isUnconditionalBranch()) {
291     parseCondBranch(*std::prev(I), TBB, Cond);
292     FBB = I->getOperand(0).getMBB();
293     return false;
294   }
295 
296   // Otherwise, we can't handle this.
297   return true;
298 }
299 
300 unsigned RISCVInstrInfo::removeBranch(MachineBasicBlock &MBB,
301                                       int *BytesRemoved) const {
302   if (BytesRemoved)
303     *BytesRemoved = 0;
304   MachineBasicBlock::iterator I = MBB.getLastNonDebugInstr();
305   if (I == MBB.end())
306     return 0;
307 
308   if (!I->getDesc().isUnconditionalBranch() &&
309       !I->getDesc().isConditionalBranch())
310     return 0;
311 
312   // Remove the branch.
313   if (BytesRemoved)
314     *BytesRemoved += getInstSizeInBytes(*I);
315   I->eraseFromParent();
316 
317   I = MBB.end();
318 
319   if (I == MBB.begin())
320     return 1;
321   --I;
322   if (!I->getDesc().isConditionalBranch())
323     return 1;
324 
325   // Remove the branch.
326   if (BytesRemoved)
327     *BytesRemoved += getInstSizeInBytes(*I);
328   I->eraseFromParent();
329   return 2;
330 }
331 
332 // Inserts a branch into the end of the specific MachineBasicBlock, returning
333 // the number of instructions inserted.
334 unsigned RISCVInstrInfo::insertBranch(
335     MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB,
336     ArrayRef<MachineOperand> Cond, const DebugLoc &DL, int *BytesAdded) const {
337   if (BytesAdded)
338     *BytesAdded = 0;
339 
340   // Shouldn't be a fall through.
341   assert(TBB && "InsertBranch must not be told to insert a fallthrough");
342   assert((Cond.size() == 3 || Cond.size() == 0) &&
343          "RISCV branch conditions have two components!");
344 
345   // Unconditional branch.
346   if (Cond.empty()) {
347     MachineInstr &MI = *BuildMI(&MBB, DL, get(RISCV::PseudoBR)).addMBB(TBB);
348     if (BytesAdded)
349       *BytesAdded += getInstSizeInBytes(MI);
350     return 1;
351   }
352 
353   // Either a one or two-way conditional branch.
354   unsigned Opc = Cond[0].getImm();
355   MachineInstr &CondMI =
356       *BuildMI(&MBB, DL, get(Opc)).add(Cond[1]).add(Cond[2]).addMBB(TBB);
357   if (BytesAdded)
358     *BytesAdded += getInstSizeInBytes(CondMI);
359 
360   // One-way conditional branch.
361   if (!FBB)
362     return 1;
363 
364   // Two-way conditional branch.
365   MachineInstr &MI = *BuildMI(&MBB, DL, get(RISCV::PseudoBR)).addMBB(FBB);
366   if (BytesAdded)
367     *BytesAdded += getInstSizeInBytes(MI);
368   return 2;
369 }
370 
371 unsigned RISCVInstrInfo::insertIndirectBranch(MachineBasicBlock &MBB,
372                                               MachineBasicBlock &DestBB,
373                                               const DebugLoc &DL,
374                                               int64_t BrOffset,
375                                               RegScavenger *RS) const {
376   assert(RS && "RegScavenger required for long branching");
377   assert(MBB.empty() &&
378          "new block should be inserted for expanding unconditional branch");
379   assert(MBB.pred_size() == 1);
380 
381   MachineFunction *MF = MBB.getParent();
382   MachineRegisterInfo &MRI = MF->getRegInfo();
383   const auto &TM = static_cast<const RISCVTargetMachine &>(MF->getTarget());
384 
385   if (TM.isPositionIndependent())
386     report_fatal_error("Unable to insert indirect branch");
387 
388   if (!isInt<32>(BrOffset))
389     report_fatal_error(
390         "Branch offsets outside of the signed 32-bit range not supported");
391 
392   // FIXME: A virtual register must be used initially, as the register
393   // scavenger won't work with empty blocks (SIInstrInfo::insertIndirectBranch
394   // uses the same workaround).
395   Register ScratchReg = MRI.createVirtualRegister(&RISCV::GPRRegClass);
396   auto II = MBB.end();
397 
398   MachineInstr &LuiMI = *BuildMI(MBB, II, DL, get(RISCV::LUI), ScratchReg)
399                              .addMBB(&DestBB, RISCVII::MO_HI);
400   BuildMI(MBB, II, DL, get(RISCV::PseudoBRIND))
401       .addReg(ScratchReg, RegState::Kill)
402       .addMBB(&DestBB, RISCVII::MO_LO);
403 
404   RS->enterBasicBlockEnd(MBB);
405   unsigned Scav = RS->scavengeRegisterBackwards(RISCV::GPRRegClass,
406                                                 LuiMI.getIterator(), false, 0);
407   MRI.replaceRegWith(ScratchReg, Scav);
408   MRI.clearVirtRegs();
409   RS->setRegUsed(Scav);
410   return 8;
411 }
412 
413 bool RISCVInstrInfo::reverseBranchCondition(
414     SmallVectorImpl<MachineOperand> &Cond) const {
415   assert((Cond.size() == 3) && "Invalid branch condition!");
416   Cond[0].setImm(getOppositeBranchOpcode(Cond[0].getImm()));
417   return false;
418 }
419 
420 MachineBasicBlock *
421 RISCVInstrInfo::getBranchDestBlock(const MachineInstr &MI) const {
422   assert(MI.getDesc().isBranch() && "Unexpected opcode!");
423   // The branch target is always the last operand.
424   int NumOp = MI.getNumExplicitOperands();
425   return MI.getOperand(NumOp - 1).getMBB();
426 }
427 
428 bool RISCVInstrInfo::isBranchOffsetInRange(unsigned BranchOp,
429                                            int64_t BrOffset) const {
430   // Ideally we could determine the supported branch offset from the
431   // RISCVII::FormMask, but this can't be used for Pseudo instructions like
432   // PseudoBR.
433   switch (BranchOp) {
434   default:
435     llvm_unreachable("Unexpected opcode!");
436   case RISCV::BEQ:
437   case RISCV::BNE:
438   case RISCV::BLT:
439   case RISCV::BGE:
440   case RISCV::BLTU:
441   case RISCV::BGEU:
442     return isIntN(13, BrOffset);
443   case RISCV::JAL:
444   case RISCV::PseudoBR:
445     return isIntN(21, BrOffset);
446   }
447 }
448 
449 unsigned RISCVInstrInfo::getInstSizeInBytes(const MachineInstr &MI) const {
450   unsigned Opcode = MI.getOpcode();
451 
452   switch (Opcode) {
453   default: { return get(Opcode).getSize(); }
454   case TargetOpcode::EH_LABEL:
455   case TargetOpcode::IMPLICIT_DEF:
456   case TargetOpcode::KILL:
457   case TargetOpcode::DBG_VALUE:
458     return 0;
459   case RISCV::PseudoCALLReg:
460   case RISCV::PseudoCALL:
461   case RISCV::PseudoTAIL:
462   case RISCV::PseudoLLA:
463   case RISCV::PseudoLA:
464   case RISCV::PseudoLA_TLS_IE:
465   case RISCV::PseudoLA_TLS_GD:
466     return 8;
467   case TargetOpcode::INLINEASM:
468   case TargetOpcode::INLINEASM_BR: {
469     const MachineFunction &MF = *MI.getParent()->getParent();
470     const auto &TM = static_cast<const RISCVTargetMachine &>(MF.getTarget());
471     return getInlineAsmLength(MI.getOperand(0).getSymbolName(),
472                               *TM.getMCAsmInfo());
473   }
474   }
475 }
476 
477 bool RISCVInstrInfo::isAsCheapAsAMove(const MachineInstr &MI) const {
478   const unsigned Opcode = MI.getOpcode();
479   switch(Opcode) {
480     default:
481       break;
482     case RISCV::ADDI:
483     case RISCV::ORI:
484     case RISCV::XORI:
485       return (MI.getOperand(1).isReg() && MI.getOperand(1).getReg() == RISCV::X0);
486   }
487   return MI.isAsCheapAsAMove();
488 }
489