1//===-- RISCVInstrFormats.td - RISCV Instruction Formats ---*- tablegen -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
10//===----------------------------------------------------------------------===//
11//
12//  These instruction format definitions are structured to match the
13//  description in the RISC-V User-Level ISA specification as closely as
14//  possible. For instance, the specification describes instructions with the
15//  MSB (31st bit) on the left and the LSB (0th bit) on the right. This is
16//  reflected in the order of parameters to each instruction class.
17//
18//  One area of divergence is in the description of immediates. The
19//  specification describes immediate encoding in terms of bit-slicing
20//  operations on the logical value represented. The immediate argument to
21//  these instruction formats instead represents the bit sequence that will be
22//  inserted into the instruction. e.g. although JAL's immediate is logically
23//  a 21-bit value (where the LSB is always zero), we describe it as an imm20
24//  to match how it is encoded.
25//
26//===----------------------------------------------------------------------===//
27
28class RISCVInst<dag outs, dag ins, string asmstr, list<dag> pattern>
29    : Instruction {
30  field bits<32> Inst;
31  let Size = 4;
32
33  bits<7> Opcode = 0;
34
35  let Inst{6-0} = Opcode;
36
37  let Namespace = "RISCV";
38
39  dag OutOperandList = outs;
40  dag InOperandList = ins;
41  let AsmString = asmstr;
42  let Pattern = pattern;
43}
44
45// Pseudo instructions
46class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern>
47    : RISCVInst<outs, ins, asmstr, pattern> {
48  let isPseudo = 1;
49}
50
51class FR<bits<7> funct7, bits<3> funct3, bits<7> opcode, dag outs, dag ins,
52         string asmstr, list<dag> pattern> : RISCVInst<outs, ins, asmstr, pattern>
53{
54  bits<5> rs2;
55  bits<5> rs1;
56  bits<5> rd;
57
58  let Inst{31-25} = funct7;
59  let Inst{24-20} = rs2;
60  let Inst{19-15} = rs1;
61  let Inst{14-12} = funct3;
62  let Inst{11-7} = rd;
63  let Opcode = opcode;
64}
65
66class FI<bits<3> funct3, bits<7> opcode, dag outs, dag ins, string asmstr, list<dag> pattern>
67    : RISCVInst<outs, ins, asmstr, pattern>
68{
69  bits<12> imm12;
70  bits<5> rs1;
71  bits<5> rd;
72
73  let Inst{31-20} = imm12;
74  let Inst{19-15} = rs1;
75  let Inst{14-12} = funct3;
76  let Inst{11-7} = rd;
77  let Opcode = opcode;
78}
79
80class FI32Shift<bit arithshift, bits<3> funct3, bits<7> opcode, dag outs, dag ins, string asmstr, list<dag> pattern>
81    : RISCVInst<outs, ins, asmstr, pattern>
82{
83  bits<5> shamt;
84  bits<5> rs1;
85  bits<5> rd;
86
87  let Inst{31} = 0;
88  let Inst{30} = arithshift;
89  let Inst{29-25} = 0;
90  let Inst{24-20} = shamt;
91  let Inst{19-15} = rs1;
92  let Inst{14-12} = funct3;
93  let Inst{11-7} = rd;
94  let Opcode = opcode;
95}
96
97class FS<bits<3> funct3, bits<7> opcode, dag outs, dag ins, string asmstr, list<dag> pattern>
98    : RISCVInst<outs, ins, asmstr, pattern>
99{
100  bits<12> imm12;
101  bits<5> rs2;
102  bits<5> rs1;
103
104  let Inst{31-25} = imm12{11-5};
105  let Inst{24-20} = rs2;
106  let Inst{19-15} = rs1;
107  let Inst{14-12} = funct3;
108  let Inst{11-7} = imm12{4-0};
109  let Opcode = opcode;
110}
111
112class FSB<bits<3> funct3, bits<7> opcode, dag outs, dag ins, string asmstr, list<dag> pattern>
113    : RISCVInst<outs, ins, asmstr, pattern>
114{
115  bits<12> imm12;
116  bits<5> rs2;
117  bits<5> rs1;
118
119  let Inst{31} = imm12{11};
120  let Inst{30-25} = imm12{9-4};
121  let Inst{24-20} = rs2;
122  let Inst{19-15} = rs1;
123  let Inst{14-12} = funct3;
124  let Inst{11-8} = imm12{3-0};
125  let Inst{7} = imm12{10};
126  let Opcode = opcode;
127}
128
129class FU<bits<7> opcode, dag outs, dag ins, string asmstr, list<dag> pattern>
130    : RISCVInst<outs, ins, asmstr, pattern>
131{
132  bits<20> imm20;
133  bits<5> rd;
134
135  let Inst{31-12} = imm20;
136  let Inst{11-7} = rd;
137  let Opcode = opcode;
138}
139
140class FUJ<bits<7> opcode, dag outs, dag ins, string asmstr, list<dag> pattern>
141    : RISCVInst<outs, ins, asmstr, pattern>
142{
143  bits<20> imm20;
144  bits<5> rd;
145
146  let Inst{31} = imm20{19};
147  let Inst{30-21} = imm20{9-0};
148  let Inst{20} = imm20{10};
149  let Inst{19-12} = imm20{18-11};
150  let Inst{11-7} = rd;
151  let Opcode = opcode;
152}
153