1 //===-- RISCVISelLowering.h - RISCV DAG Lowering Interface ------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file defines the interfaces that RISCV uses to lower LLVM code into a 10 // selection DAG. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #ifndef LLVM_LIB_TARGET_RISCV_RISCVISELLOWERING_H 15 #define LLVM_LIB_TARGET_RISCV_RISCVISELLOWERING_H 16 17 #include "RISCV.h" 18 #include "llvm/CodeGen/CallingConvLower.h" 19 #include "llvm/CodeGen/SelectionDAG.h" 20 #include "llvm/CodeGen/TargetLowering.h" 21 22 namespace llvm { 23 class RISCVSubtarget; 24 struct RISCVRegisterInfo; 25 namespace RISCVISD { 26 enum NodeType : unsigned { 27 FIRST_NUMBER = ISD::BUILTIN_OP_END, 28 RET_FLAG, 29 URET_FLAG, 30 SRET_FLAG, 31 MRET_FLAG, 32 CALL, 33 /// Select with condition operator - This selects between a true value and 34 /// a false value (ops #3 and #4) based on the boolean result of comparing 35 /// the lhs and rhs (ops #0 and #1) of a conditional expression with the 36 /// condition code in op #2, a XLenVT constant from the ISD::CondCode enum. 37 /// The lhs and rhs are XLenVT integers. The true and false values can be 38 /// integer or floating point. 39 SELECT_CC, 40 BR_CC, 41 BuildPairF64, 42 SplitF64, 43 TAIL, 44 // Multiply high for signedxunsigned. 45 MULHSU, 46 // RV64I shifts, directly matching the semantics of the named RISC-V 47 // instructions. 48 SLLW, 49 SRAW, 50 SRLW, 51 // 32-bit operations from RV64M that can't be simply matched with a pattern 52 // at instruction selection time. These have undefined behavior for division 53 // by 0 or overflow (divw) like their target independent counterparts. 54 DIVW, 55 DIVUW, 56 REMUW, 57 // RV64IB rotates, directly matching the semantics of the named RISC-V 58 // instructions. 59 ROLW, 60 RORW, 61 // RV64IZbb bit counting instructions directly matching the semantics of the 62 // named RISC-V instructions. 63 CLZW, 64 CTZW, 65 // RV64IB/RV32IB funnel shifts, with the semantics of the named RISC-V 66 // instructions. Operand order is rs1, rs3, rs2/shamt. 67 FSR, 68 FSL, 69 // RV64IB funnel shifts, with the semantics of the named RISC-V instructions. 70 // Operand order is rs1, rs3, rs2/shamt. 71 FSRW, 72 FSLW, 73 // FPR<->GPR transfer operations when the FPR is smaller than XLEN, needed as 74 // XLEN is the only legal integer width. 75 // 76 // FMV_H_X matches the semantics of the FMV.H.X. 77 // FMV_X_ANYEXTH is similar to FMV.X.H but has an any-extended result. 78 // FMV_W_X_RV64 matches the semantics of the FMV.W.X. 79 // FMV_X_ANYEXTW_RV64 is similar to FMV.X.W but has an any-extended result. 80 // 81 // This is a more convenient semantic for producing dagcombines that remove 82 // unnecessary GPR->FPR->GPR moves. 83 FMV_H_X, 84 FMV_X_ANYEXTH, 85 FMV_W_X_RV64, 86 FMV_X_ANYEXTW_RV64, 87 // FP to XLen int conversions. Corresponds to fcvt.l(u).s/d/h on RV64 and 88 // fcvt.w(u).s/d/h on RV32. Unlike FP_TO_S/UINT these saturate out of 89 // range inputs. These are used for FP_TO_S/UINT_SAT lowering. Rounding mode 90 // is passed as a TargetConstant operand using the RISCVFPRndMode enum. 91 FCVT_X, 92 FCVT_XU, 93 // FP to 32 bit int conversions for RV64. These are used to keep track of the 94 // result being sign extended to 64 bit. These saturate out of range inputs. 95 // Used for FP_TO_S/UINT and FP_TO_S/UINT_SAT lowering. Rounding mode 96 // is passed as a TargetConstant operand using the RISCVFPRndMode enum. 97 FCVT_W_RV64, 98 FCVT_WU_RV64, 99 // READ_CYCLE_WIDE - A read of the 64-bit cycle CSR on a 32-bit target 100 // (returns (Lo, Hi)). It takes a chain operand. 101 READ_CYCLE_WIDE, 102 // Generalized Reverse and Generalized Or-Combine - directly matching the 103 // semantics of the named RISC-V instructions. Lowered as custom nodes as 104 // TableGen chokes when faced with commutative permutations in deeply-nested 105 // DAGs. Each node takes an input operand and a control operand and outputs a 106 // bit-manipulated version of input. All operands are i32 or XLenVT. 107 GREV, 108 GREVW, 109 GORC, 110 GORCW, 111 SHFL, 112 SHFLW, 113 UNSHFL, 114 UNSHFLW, 115 // Bit Compress/Decompress implement the generic bit extract and bit deposit 116 // functions. This operation is also referred to as bit gather/scatter, bit 117 // pack/unpack, parallel extract/deposit, compress/expand, or right 118 // compress/right expand. 119 BCOMPRESS, 120 BCOMPRESSW, 121 BDECOMPRESS, 122 BDECOMPRESSW, 123 // The bit field place (bfp) instruction places up to XLEN/2 LSB bits from rs2 124 // into the value in rs1. The upper bits of rs2 control the length of the bit 125 // field and target position. The layout of rs2 is chosen in a way that makes 126 // it possible to construct rs2 easily using pack[h] instructions and/or 127 // andi/lui. 128 BFP, 129 BFPW, 130 // Vector Extension 131 // VMV_V_X_VL matches the semantics of vmv.v.x but includes an extra operand 132 // for the VL value to be used for the operation. 133 VMV_V_X_VL, 134 // VFMV_V_F_VL matches the semantics of vfmv.v.f but includes an extra operand 135 // for the VL value to be used for the operation. 136 VFMV_V_F_VL, 137 // VMV_X_S matches the semantics of vmv.x.s. The result is always XLenVT sign 138 // extended from the vector element size. 139 VMV_X_S, 140 // VMV_S_X_VL matches the semantics of vmv.s.x. It carries a VL operand. 141 VMV_S_X_VL, 142 // VFMV_S_F_VL matches the semantics of vfmv.s.f. It carries a VL operand. 143 VFMV_S_F_VL, 144 // Splats an i64 scalar to a vector type (with element type i64) where the 145 // scalar is a sign-extended i32. 146 SPLAT_VECTOR_I64, 147 // Splats an 64-bit value that has been split into two i32 parts. This is 148 // expanded late to two scalar stores and a stride 0 vector load. 149 SPLAT_VECTOR_SPLIT_I64_VL, 150 // Read VLENB CSR 151 READ_VLENB, 152 // Truncates a RVV integer vector by one power-of-two. Carries both an extra 153 // mask and VL operand. 154 TRUNCATE_VECTOR_VL, 155 // Matches the semantics of vslideup/vslidedown. The first operand is the 156 // pass-thru operand, the second is the source vector, the third is the 157 // XLenVT index (either constant or non-constant), the fourth is the mask 158 // and the fifth the VL. 159 VSLIDEUP_VL, 160 VSLIDEDOWN_VL, 161 // Matches the semantics of vslide1up/slide1down. The first operand is the 162 // source vector, the second is the XLenVT scalar value. The third and fourth 163 // operands are the mask and VL operands. 164 VSLIDE1UP_VL, 165 VSLIDE1DOWN_VL, 166 // Matches the semantics of the vid.v instruction, with a mask and VL 167 // operand. 168 VID_VL, 169 // Matches the semantics of the vfcnvt.rod function (Convert double-width 170 // float to single-width float, rounding towards odd). Takes a double-width 171 // float vector and produces a single-width float vector. Also has a mask and 172 // VL operand. 173 VFNCVT_ROD_VL, 174 // These nodes match the semantics of the corresponding RVV vector reduction 175 // instructions. They produce a vector result which is the reduction 176 // performed over the second vector operand plus the first element of the 177 // third vector operand. The first operand is the pass-thru operand. The 178 // second operand is an unconstrained vector type, and the result, first, and 179 // third operand's types are expected to be the corresponding full-width 180 // LMUL=1 type for the second operand: 181 // nxv8i8 = vecreduce_add nxv8i8, nxv32i8, nxv8i8 182 // nxv2i32 = vecreduce_add nxv2i32, nxv8i32, nxv2i32 183 // The different in types does introduce extra vsetvli instructions but 184 // similarly it reduces the number of registers consumed per reduction. 185 // Also has a mask and VL operand. 186 VECREDUCE_ADD_VL, 187 VECREDUCE_UMAX_VL, 188 VECREDUCE_SMAX_VL, 189 VECREDUCE_UMIN_VL, 190 VECREDUCE_SMIN_VL, 191 VECREDUCE_AND_VL, 192 VECREDUCE_OR_VL, 193 VECREDUCE_XOR_VL, 194 VECREDUCE_FADD_VL, 195 VECREDUCE_SEQ_FADD_VL, 196 VECREDUCE_FMIN_VL, 197 VECREDUCE_FMAX_VL, 198 199 // Vector binary and unary ops with a mask as a third operand, and VL as a 200 // fourth operand. 201 // FIXME: Can we replace these with ISD::VP_*? 202 ADD_VL, 203 AND_VL, 204 MUL_VL, 205 OR_VL, 206 SDIV_VL, 207 SHL_VL, 208 SREM_VL, 209 SRA_VL, 210 SRL_VL, 211 SUB_VL, 212 UDIV_VL, 213 UREM_VL, 214 XOR_VL, 215 216 SADDSAT_VL, 217 UADDSAT_VL, 218 SSUBSAT_VL, 219 USUBSAT_VL, 220 221 FADD_VL, 222 FSUB_VL, 223 FMUL_VL, 224 FDIV_VL, 225 FNEG_VL, 226 FABS_VL, 227 FSQRT_VL, 228 FMA_VL, 229 FCOPYSIGN_VL, 230 SMIN_VL, 231 SMAX_VL, 232 UMIN_VL, 233 UMAX_VL, 234 FMINNUM_VL, 235 FMAXNUM_VL, 236 MULHS_VL, 237 MULHU_VL, 238 FP_TO_SINT_VL, 239 FP_TO_UINT_VL, 240 SINT_TO_FP_VL, 241 UINT_TO_FP_VL, 242 FP_ROUND_VL, 243 FP_EXTEND_VL, 244 245 // Widening instructions 246 VWMUL_VL, 247 VWMULU_VL, 248 VWADDU_VL, 249 250 // Vector compare producing a mask. Fourth operand is input mask. Fifth 251 // operand is VL. 252 SETCC_VL, 253 254 // Vector select with an additional VL operand. This operation is unmasked. 255 VSELECT_VL, 256 257 // Mask binary operators. 258 VMAND_VL, 259 VMOR_VL, 260 VMXOR_VL, 261 262 // Set mask vector to all zeros or ones. 263 VMCLR_VL, 264 VMSET_VL, 265 266 // Matches the semantics of vrgather.vx and vrgather.vv with an extra operand 267 // for VL. 268 VRGATHER_VX_VL, 269 VRGATHER_VV_VL, 270 VRGATHEREI16_VV_VL, 271 272 // Vector sign/zero extend with additional mask & VL operands. 273 VSEXT_VL, 274 VZEXT_VL, 275 276 // vcpop.m with additional mask and VL operands. 277 VCPOP_VL, 278 279 // Reads value of CSR. 280 // The first operand is a chain pointer. The second specifies address of the 281 // required CSR. Two results are produced, the read value and the new chain 282 // pointer. 283 READ_CSR, 284 // Write value to CSR. 285 // The first operand is a chain pointer, the second specifies address of the 286 // required CSR and the third is the value to write. The result is the new 287 // chain pointer. 288 WRITE_CSR, 289 // Read and write value of CSR. 290 // The first operand is a chain pointer, the second specifies address of the 291 // required CSR and the third is the value to write. Two results are produced, 292 // the value read before the modification and the new chain pointer. 293 SWAP_CSR, 294 295 // FP to 32 bit int conversions for RV64. These are used to keep track of the 296 // result being sign extended to 64 bit. These saturate out of range inputs. 297 STRICT_FCVT_W_RV64 = ISD::FIRST_TARGET_STRICTFP_OPCODE, 298 STRICT_FCVT_WU_RV64, 299 300 // Memory opcodes start here. 301 VLE_VL = ISD::FIRST_TARGET_MEMORY_OPCODE, 302 VSE_VL, 303 304 // WARNING: Do not add anything in the end unless you want the node to 305 // have memop! In fact, starting from FIRST_TARGET_MEMORY_OPCODE all 306 // opcodes will be thought as target memory ops! 307 }; 308 } // namespace RISCVISD 309 310 class RISCVTargetLowering : public TargetLowering { 311 const RISCVSubtarget &Subtarget; 312 313 public: 314 explicit RISCVTargetLowering(const TargetMachine &TM, 315 const RISCVSubtarget &STI); 316 317 const RISCVSubtarget &getSubtarget() const { return Subtarget; } 318 319 bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I, 320 MachineFunction &MF, 321 unsigned Intrinsic) const override; 322 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, 323 unsigned AS, 324 Instruction *I = nullptr) const override; 325 bool isLegalICmpImmediate(int64_t Imm) const override; 326 bool isLegalAddImmediate(int64_t Imm) const override; 327 bool isTruncateFree(Type *SrcTy, Type *DstTy) const override; 328 bool isTruncateFree(EVT SrcVT, EVT DstVT) const override; 329 bool isZExtFree(SDValue Val, EVT VT2) const override; 330 bool isSExtCheaperThanZExt(EVT SrcVT, EVT DstVT) const override; 331 bool isCheapToSpeculateCttz() const override; 332 bool isCheapToSpeculateCtlz() const override; 333 bool hasAndNotCompare(SDValue Y) const override; 334 bool shouldSinkOperands(Instruction *I, 335 SmallVectorImpl<Use *> &Ops) const override; 336 bool isFPImmLegal(const APFloat &Imm, EVT VT, 337 bool ForCodeSize) const override; 338 339 bool softPromoteHalfType() const override { return true; } 340 341 /// Return the register type for a given MVT, ensuring vectors are treated 342 /// as a series of gpr sized integers. 343 MVT getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC, 344 EVT VT) const override; 345 346 /// Return the number of registers for a given MVT, ensuring vectors are 347 /// treated as a series of gpr sized integers. 348 unsigned getNumRegistersForCallingConv(LLVMContext &Context, 349 CallingConv::ID CC, 350 EVT VT) const override; 351 352 /// Return true if the given shuffle mask can be codegen'd directly, or if it 353 /// should be stack expanded. 354 bool isShuffleMaskLegal(ArrayRef<int> M, EVT VT) const override; 355 356 bool hasBitPreservingFPLogic(EVT VT) const override; 357 bool 358 shouldExpandBuildVectorWithShuffles(EVT VT, 359 unsigned DefinedValues) const override; 360 361 // Provide custom lowering hooks for some operations. 362 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override; 363 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results, 364 SelectionDAG &DAG) const override; 365 366 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override; 367 368 bool targetShrinkDemandedConstant(SDValue Op, const APInt &DemandedBits, 369 const APInt &DemandedElts, 370 TargetLoweringOpt &TLO) const override; 371 372 void computeKnownBitsForTargetNode(const SDValue Op, 373 KnownBits &Known, 374 const APInt &DemandedElts, 375 const SelectionDAG &DAG, 376 unsigned Depth) const override; 377 unsigned ComputeNumSignBitsForTargetNode(SDValue Op, 378 const APInt &DemandedElts, 379 const SelectionDAG &DAG, 380 unsigned Depth) const override; 381 382 // This method returns the name of a target specific DAG node. 383 const char *getTargetNodeName(unsigned Opcode) const override; 384 385 ConstraintType getConstraintType(StringRef Constraint) const override; 386 387 unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override; 388 389 std::pair<unsigned, const TargetRegisterClass *> 390 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, 391 StringRef Constraint, MVT VT) const override; 392 393 void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, 394 std::vector<SDValue> &Ops, 395 SelectionDAG &DAG) const override; 396 397 MachineBasicBlock * 398 EmitInstrWithCustomInserter(MachineInstr &MI, 399 MachineBasicBlock *BB) const override; 400 401 void AdjustInstrPostInstrSelection(MachineInstr &MI, 402 SDNode *Node) const override; 403 404 EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, 405 EVT VT) const override; 406 407 bool convertSetCCLogicToBitwiseLogic(EVT VT) const override { 408 return VT.isScalarInteger(); 409 } 410 bool convertSelectOfConstantsToMath(EVT VT) const override { return true; } 411 412 bool shouldInsertFencesForAtomic(const Instruction *I) const override { 413 return isa<LoadInst>(I) || isa<StoreInst>(I); 414 } 415 Instruction *emitLeadingFence(IRBuilderBase &Builder, Instruction *Inst, 416 AtomicOrdering Ord) const override; 417 Instruction *emitTrailingFence(IRBuilderBase &Builder, Instruction *Inst, 418 AtomicOrdering Ord) const override; 419 420 bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF, 421 EVT VT) const override; 422 423 ISD::NodeType getExtendForAtomicOps() const override { 424 return ISD::SIGN_EXTEND; 425 } 426 427 ISD::NodeType getExtendForAtomicCmpSwapArg() const override { 428 return ISD::SIGN_EXTEND; 429 } 430 431 bool shouldExpandShift(SelectionDAG &DAG, SDNode *N) const override { 432 if (DAG.getMachineFunction().getFunction().hasMinSize()) 433 return false; 434 return true; 435 } 436 bool isDesirableToCommuteWithShift(const SDNode *N, 437 CombineLevel Level) const override; 438 439 /// If a physical register, this returns the register that receives the 440 /// exception address on entry to an EH pad. 441 Register 442 getExceptionPointerRegister(const Constant *PersonalityFn) const override; 443 444 /// If a physical register, this returns the register that receives the 445 /// exception typeid on entry to a landing pad. 446 Register 447 getExceptionSelectorRegister(const Constant *PersonalityFn) const override; 448 449 bool shouldExtendTypeInLibCall(EVT Type) const override; 450 bool shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const override; 451 452 /// Returns the register with the specified architectural or ABI name. This 453 /// method is necessary to lower the llvm.read_register.* and 454 /// llvm.write_register.* intrinsics. Allocatable registers must be reserved 455 /// with the clang -ffixed-xX flag for access to be allowed. 456 Register getRegisterByName(const char *RegName, LLT VT, 457 const MachineFunction &MF) const override; 458 459 // Lower incoming arguments, copy physregs into vregs 460 SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, 461 bool IsVarArg, 462 const SmallVectorImpl<ISD::InputArg> &Ins, 463 const SDLoc &DL, SelectionDAG &DAG, 464 SmallVectorImpl<SDValue> &InVals) const override; 465 bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, 466 bool IsVarArg, 467 const SmallVectorImpl<ISD::OutputArg> &Outs, 468 LLVMContext &Context) const override; 469 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, 470 const SmallVectorImpl<ISD::OutputArg> &Outs, 471 const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL, 472 SelectionDAG &DAG) const override; 473 SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI, 474 SmallVectorImpl<SDValue> &InVals) const override; 475 template <class NodeTy> 476 SDValue getAddr(NodeTy *N, SelectionDAG &DAG, bool IsLocal = true) const; 477 478 bool shouldConvertConstantLoadToIntImm(const APInt &Imm, 479 Type *Ty) const override { 480 return true; 481 } 482 bool mayBeEmittedAsTailCall(const CallInst *CI) const override; 483 bool shouldConsiderGEPOffsetSplit() const override { return true; } 484 485 bool decomposeMulByConstant(LLVMContext &Context, EVT VT, 486 SDValue C) const override; 487 488 bool isMulAddWithConstProfitable(const SDValue &AddNode, 489 const SDValue &ConstNode) const override; 490 491 TargetLowering::AtomicExpansionKind 492 shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override; 493 Value *emitMaskedAtomicRMWIntrinsic(IRBuilderBase &Builder, AtomicRMWInst *AI, 494 Value *AlignedAddr, Value *Incr, 495 Value *Mask, Value *ShiftAmt, 496 AtomicOrdering Ord) const override; 497 TargetLowering::AtomicExpansionKind 498 shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *CI) const override; 499 Value *emitMaskedAtomicCmpXchgIntrinsic(IRBuilderBase &Builder, 500 AtomicCmpXchgInst *CI, 501 Value *AlignedAddr, Value *CmpVal, 502 Value *NewVal, Value *Mask, 503 AtomicOrdering Ord) const override; 504 505 /// Returns true if the target allows unaligned memory accesses of the 506 /// specified type. 507 bool allowsMisalignedMemoryAccesses( 508 EVT VT, unsigned AddrSpace = 0, Align Alignment = Align(1), 509 MachineMemOperand::Flags Flags = MachineMemOperand::MONone, 510 bool *Fast = nullptr) const override; 511 512 bool splitValueIntoRegisterParts(SelectionDAG &DAG, const SDLoc &DL, 513 SDValue Val, SDValue *Parts, 514 unsigned NumParts, MVT PartVT, 515 Optional<CallingConv::ID> CC) const override; 516 517 SDValue 518 joinRegisterPartsIntoValue(SelectionDAG &DAG, const SDLoc &DL, 519 const SDValue *Parts, unsigned NumParts, 520 MVT PartVT, EVT ValueVT, 521 Optional<CallingConv::ID> CC) const override; 522 523 static RISCVII::VLMUL getLMUL(MVT VT); 524 static unsigned getRegClassIDForLMUL(RISCVII::VLMUL LMul); 525 static unsigned getSubregIndexByMVT(MVT VT, unsigned Index); 526 static unsigned getRegClassIDForVecVT(MVT VT); 527 static std::pair<unsigned, unsigned> 528 decomposeSubvectorInsertExtractToSubRegs(MVT VecVT, MVT SubVecVT, 529 unsigned InsertExtractIdx, 530 const RISCVRegisterInfo *TRI); 531 MVT getContainerForFixedLengthVector(MVT VT) const; 532 533 bool shouldRemoveExtendFromGSIndex(EVT VT) const override; 534 535 bool isLegalElementTypeForRVV(Type *ScalarTy) const; 536 537 bool shouldConvertFpToSat(unsigned Op, EVT FPVT, EVT VT) const override; 538 539 SDValue BuildSDIVPow2(SDNode *N, const APInt &Divisor, SelectionDAG &DAG, 540 SmallVectorImpl<SDNode *> &Created) const override; 541 542 unsigned getJumpTableEncoding() const override; 543 544 const MCExpr *LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI, 545 const MachineBasicBlock *MBB, 546 unsigned uid, 547 MCContext &Ctx) const override; 548 549 private: 550 /// RISCVCCAssignFn - This target-specific function extends the default 551 /// CCValAssign with additional information used to lower RISC-V calling 552 /// conventions. 553 typedef bool RISCVCCAssignFn(const DataLayout &DL, RISCVABI::ABI, 554 unsigned ValNo, MVT ValVT, MVT LocVT, 555 CCValAssign::LocInfo LocInfo, 556 ISD::ArgFlagsTy ArgFlags, CCState &State, 557 bool IsFixed, bool IsRet, Type *OrigTy, 558 const RISCVTargetLowering &TLI, 559 Optional<unsigned> FirstMaskArgument); 560 561 void analyzeInputArgs(MachineFunction &MF, CCState &CCInfo, 562 const SmallVectorImpl<ISD::InputArg> &Ins, bool IsRet, 563 RISCVCCAssignFn Fn) const; 564 void analyzeOutputArgs(MachineFunction &MF, CCState &CCInfo, 565 const SmallVectorImpl<ISD::OutputArg> &Outs, 566 bool IsRet, CallLoweringInfo *CLI, 567 RISCVCCAssignFn Fn) const; 568 569 SDValue getStaticTLSAddr(GlobalAddressSDNode *N, SelectionDAG &DAG, 570 bool UseGOT) const; 571 SDValue getDynamicTLSAddr(GlobalAddressSDNode *N, SelectionDAG &DAG) const; 572 573 SDValue lowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const; 574 SDValue lowerBlockAddress(SDValue Op, SelectionDAG &DAG) const; 575 SDValue lowerConstantPool(SDValue Op, SelectionDAG &DAG) const; 576 SDValue lowerJumpTable(SDValue Op, SelectionDAG &DAG) const; 577 SDValue lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const; 578 SDValue lowerSELECT(SDValue Op, SelectionDAG &DAG) const; 579 SDValue lowerBRCOND(SDValue Op, SelectionDAG &DAG) const; 580 SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const; 581 SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const; 582 SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const; 583 SDValue lowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const; 584 SDValue lowerShiftRightParts(SDValue Op, SelectionDAG &DAG, bool IsSRA) const; 585 SDValue lowerSPLAT_VECTOR_PARTS(SDValue Op, SelectionDAG &DAG) const; 586 SDValue lowerVectorMaskSplat(SDValue Op, SelectionDAG &DAG) const; 587 SDValue lowerVectorMaskExt(SDValue Op, SelectionDAG &DAG, 588 int64_t ExtTrueVal) const; 589 SDValue lowerVectorMaskTrunc(SDValue Op, SelectionDAG &DAG) const; 590 SDValue lowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const; 591 SDValue lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const; 592 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const; 593 SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const; 594 SDValue LowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const; 595 SDValue lowerVPREDUCE(SDValue Op, SelectionDAG &DAG) const; 596 SDValue lowerVECREDUCE(SDValue Op, SelectionDAG &DAG) const; 597 SDValue lowerVectorMaskVecReduction(SDValue Op, SelectionDAG &DAG, 598 bool IsVP) const; 599 SDValue lowerFPVECREDUCE(SDValue Op, SelectionDAG &DAG) const; 600 SDValue lowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const; 601 SDValue lowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const; 602 SDValue lowerSTEP_VECTOR(SDValue Op, SelectionDAG &DAG) const; 603 SDValue lowerVECTOR_REVERSE(SDValue Op, SelectionDAG &DAG) const; 604 SDValue lowerABS(SDValue Op, SelectionDAG &DAG) const; 605 SDValue lowerMaskedLoad(SDValue Op, SelectionDAG &DAG) const; 606 SDValue lowerMaskedStore(SDValue Op, SelectionDAG &DAG) const; 607 SDValue lowerFixedLengthVectorFCOPYSIGNToRVV(SDValue Op, 608 SelectionDAG &DAG) const; 609 SDValue lowerMaskedGather(SDValue Op, SelectionDAG &DAG) const; 610 SDValue lowerMaskedScatter(SDValue Op, SelectionDAG &DAG) const; 611 SDValue lowerFixedLengthVectorLoadToRVV(SDValue Op, SelectionDAG &DAG) const; 612 SDValue lowerFixedLengthVectorStoreToRVV(SDValue Op, SelectionDAG &DAG) const; 613 SDValue lowerFixedLengthVectorSetccToRVV(SDValue Op, SelectionDAG &DAG) const; 614 SDValue lowerFixedLengthVectorLogicOpToRVV(SDValue Op, SelectionDAG &DAG, 615 unsigned MaskOpc, 616 unsigned VecOpc) const; 617 SDValue lowerFixedLengthVectorShiftToRVV(SDValue Op, SelectionDAG &DAG) const; 618 SDValue lowerFixedLengthVectorSelectToRVV(SDValue Op, 619 SelectionDAG &DAG) const; 620 SDValue lowerToScalableOp(SDValue Op, SelectionDAG &DAG, unsigned NewOpc, 621 bool HasMask = true) const; 622 SDValue lowerVPOp(SDValue Op, SelectionDAG &DAG, unsigned RISCVISDOpc) const; 623 SDValue lowerLogicVPOp(SDValue Op, SelectionDAG &DAG, unsigned MaskOpc, 624 unsigned VecOpc) const; 625 SDValue lowerFixedLengthVectorExtendToRVV(SDValue Op, SelectionDAG &DAG, 626 unsigned ExtendOpc) const; 627 SDValue lowerGET_ROUNDING(SDValue Op, SelectionDAG &DAG) const; 628 SDValue lowerSET_ROUNDING(SDValue Op, SelectionDAG &DAG) const; 629 630 SDValue expandUnalignedRVVLoad(SDValue Op, SelectionDAG &DAG) const; 631 SDValue expandUnalignedRVVStore(SDValue Op, SelectionDAG &DAG) const; 632 633 bool isEligibleForTailCallOptimization( 634 CCState &CCInfo, CallLoweringInfo &CLI, MachineFunction &MF, 635 const SmallVector<CCValAssign, 16> &ArgLocs) const; 636 637 /// Generate error diagnostics if any register used by CC has been marked 638 /// reserved. 639 void validateCCReservedRegs( 640 const SmallVectorImpl<std::pair<llvm::Register, llvm::SDValue>> &Regs, 641 MachineFunction &MF) const; 642 643 bool useRVVForFixedLengthVectorVT(MVT VT) const; 644 645 MVT getVPExplicitVectorLengthTy() const override; 646 647 /// RVV code generation for fixed length vectors does not lower all 648 /// BUILD_VECTORs. This makes BUILD_VECTOR legalisation a source of stores to 649 /// merge. However, merging them creates a BUILD_VECTOR that is just as 650 /// illegal as the original, thus leading to an infinite legalisation loop. 651 /// NOTE: Once BUILD_VECTOR can be custom lowered for all legal vector types, 652 /// this override can be removed. 653 bool mergeStoresAfterLegalization(EVT VT) const override; 654 655 /// Disable normalizing 656 /// select(N0&N1, X, Y) => select(N0, select(N1, X, Y), Y) and 657 /// select(N0|N1, X, Y) => select(N0, select(N1, X, Y, Y)) 658 /// RISCV doesn't have flags so it's better to perform the and/or in a GPR. 659 bool shouldNormalizeToSelectSequence(LLVMContext &, EVT) const override { 660 return false; 661 }; 662 }; 663 664 namespace RISCV { 665 // We use 64 bits as the known part in the scalable vector types. 666 static constexpr unsigned RVVBitsPerBlock = 64; 667 } // namespace RISCV 668 669 namespace RISCVVIntrinsicsTable { 670 671 struct RISCVVIntrinsicInfo { 672 unsigned IntrinsicID; 673 uint8_t SplatOperand; 674 uint8_t VLOperand; 675 bool hasSplatOperand() const { 676 // 0xF is not valid. See NoSplatOperand in IntrinsicsRISCV.td. 677 return SplatOperand != 0xF; 678 } 679 bool hasVLOperand() const { 680 // 0x1F is not valid. See NoVLOperand in IntrinsicsRISCV.td. 681 return VLOperand != 0x1F; 682 } 683 }; 684 685 using namespace RISCV; 686 687 #define GET_RISCVVIntrinsicsTable_DECL 688 #include "RISCVGenSearchableTables.inc" 689 690 } // end namespace RISCVVIntrinsicsTable 691 692 } // end namespace llvm 693 694 #endif 695