1 //===-- RISCVISelLowering.h - RISCV DAG Lowering Interface ------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines the interfaces that RISCV uses to lower LLVM code into a
10 // selection DAG.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_RISCV_RISCVISELLOWERING_H
15 #define LLVM_LIB_TARGET_RISCV_RISCVISELLOWERING_H
16 
17 #include "RISCV.h"
18 #include "llvm/CodeGen/SelectionDAG.h"
19 #include "llvm/CodeGen/TargetLowering.h"
20 
21 namespace llvm {
22 class RISCVSubtarget;
23 namespace RISCVISD {
24 enum NodeType : unsigned {
25   FIRST_NUMBER = ISD::BUILTIN_OP_END,
26   RET_FLAG,
27   URET_FLAG,
28   SRET_FLAG,
29   MRET_FLAG,
30   CALL,
31   SELECT_CC,
32   BuildPairF64,
33   SplitF64,
34   TAIL,
35   // RV64I shifts, directly matching the semantics of the named RISC-V
36   // instructions.
37   SLLW,
38   SRAW,
39   SRLW,
40   // 32-bit operations from RV64M that can't be simply matched with a pattern
41   // at instruction selection time.
42   DIVW,
43   DIVUW,
44   REMUW,
45   // FPR32<->GPR transfer operations for RV64. Needed as an i32<->f32 bitcast
46   // is not legal on RV64. FMV_W_X_RV64 matches the semantics of the FMV.W.X.
47   // FMV_X_ANYEXTW_RV64 is similar to FMV.X.W but has an any-extended result.
48   // This is a more convenient semantic for producing dagcombines that remove
49   // unnecessary GPR->FPR->GPR moves.
50   FMV_W_X_RV64,
51   FMV_X_ANYEXTW_RV64
52 };
53 }
54 
55 class RISCVTargetLowering : public TargetLowering {
56   const RISCVSubtarget &Subtarget;
57 
58 public:
59   explicit RISCVTargetLowering(const TargetMachine &TM,
60                                const RISCVSubtarget &STI);
61 
62   bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I,
63                           MachineFunction &MF,
64                           unsigned Intrinsic) const override;
65   bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty,
66                              unsigned AS,
67                              Instruction *I = nullptr) const override;
68   bool isLegalICmpImmediate(int64_t Imm) const override;
69   bool isLegalAddImmediate(int64_t Imm) const override;
70   bool isTruncateFree(Type *SrcTy, Type *DstTy) const override;
71   bool isTruncateFree(EVT SrcVT, EVT DstVT) const override;
72   bool isZExtFree(SDValue Val, EVT VT2) const override;
73   bool isSExtCheaperThanZExt(EVT SrcVT, EVT DstVT) const override;
74 
75   // Provide custom lowering hooks for some operations.
76   SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
77   void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
78                           SelectionDAG &DAG) const override;
79 
80   SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
81 
82   unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
83                                            const APInt &DemandedElts,
84                                            const SelectionDAG &DAG,
85                                            unsigned Depth) const override;
86 
87   // This method returns the name of a target specific DAG node.
88   const char *getTargetNodeName(unsigned Opcode) const override;
89 
90   std::pair<unsigned, const TargetRegisterClass *>
91   getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
92                                StringRef Constraint, MVT VT) const override;
93 
94   MachineBasicBlock *
95   EmitInstrWithCustomInserter(MachineInstr &MI,
96                               MachineBasicBlock *BB) const override;
97 
98   EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
99                          EVT VT) const override;
100 
101   bool convertSetCCLogicToBitwiseLogic(EVT VT) const override {
102     return VT.isScalarInteger();
103   }
104 
105   bool shouldInsertFencesForAtomic(const Instruction *I) const override {
106     return isa<LoadInst>(I) || isa<StoreInst>(I);
107   }
108   Instruction *emitLeadingFence(IRBuilder<> &Builder, Instruction *Inst,
109                                 AtomicOrdering Ord) const override;
110   Instruction *emitTrailingFence(IRBuilder<> &Builder, Instruction *Inst,
111                                  AtomicOrdering Ord) const override;
112 
113   ISD::NodeType getExtendForAtomicOps() const override {
114     return ISD::SIGN_EXTEND;
115   }
116 
117 private:
118   void analyzeInputArgs(MachineFunction &MF, CCState &CCInfo,
119                         const SmallVectorImpl<ISD::InputArg> &Ins,
120                         bool IsRet) const;
121   void analyzeOutputArgs(MachineFunction &MF, CCState &CCInfo,
122                          const SmallVectorImpl<ISD::OutputArg> &Outs,
123                          bool IsRet, CallLoweringInfo *CLI) const;
124   // Lower incoming arguments, copy physregs into vregs
125   SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,
126                                bool IsVarArg,
127                                const SmallVectorImpl<ISD::InputArg> &Ins,
128                                const SDLoc &DL, SelectionDAG &DAG,
129                                SmallVectorImpl<SDValue> &InVals) const override;
130   bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
131                       bool IsVarArg,
132                       const SmallVectorImpl<ISD::OutputArg> &Outs,
133                       LLVMContext &Context) const override;
134   SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
135                       const SmallVectorImpl<ISD::OutputArg> &Outs,
136                       const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL,
137                       SelectionDAG &DAG) const override;
138   SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI,
139                     SmallVectorImpl<SDValue> &InVals) const override;
140   bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
141                                          Type *Ty) const override {
142     return true;
143   }
144   SDValue lowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
145   SDValue lowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
146   SDValue lowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
147   SDValue lowerSELECT(SDValue Op, SelectionDAG &DAG) const;
148   SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const;
149   SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
150   SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
151 
152   bool isEligibleForTailCallOptimization(
153       CCState &CCInfo, CallLoweringInfo &CLI, MachineFunction &MF,
154       const SmallVector<CCValAssign, 16> &ArgLocs) const;
155 
156   TargetLowering::AtomicExpansionKind
157   shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override;
158   virtual Value *emitMaskedAtomicRMWIntrinsic(
159       IRBuilder<> &Builder, AtomicRMWInst *AI, Value *AlignedAddr, Value *Incr,
160       Value *Mask, Value *ShiftAmt, AtomicOrdering Ord) const override;
161   TargetLowering::AtomicExpansionKind
162   shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *CI) const override;
163   virtual Value *
164   emitMaskedAtomicCmpXchgIntrinsic(IRBuilder<> &Builder, AtomicCmpXchgInst *CI,
165                                    Value *AlignedAddr, Value *CmpVal,
166                                    Value *NewVal, Value *Mask,
167                                    AtomicOrdering Ord) const override;
168 };
169 }
170 
171 #endif
172