1 //===-- RISCVISelLowering.h - RISCV DAG Lowering Interface ------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file defines the interfaces that RISCV uses to lower LLVM code into a 10 // selection DAG. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #ifndef LLVM_LIB_TARGET_RISCV_RISCVISELLOWERING_H 15 #define LLVM_LIB_TARGET_RISCV_RISCVISELLOWERING_H 16 17 #include "RISCV.h" 18 #include "llvm/CodeGen/CallingConvLower.h" 19 #include "llvm/CodeGen/SelectionDAG.h" 20 #include "llvm/CodeGen/TargetLowering.h" 21 22 namespace llvm { 23 class RISCVSubtarget; 24 struct RISCVRegisterInfo; 25 namespace RISCVISD { 26 enum NodeType : unsigned { 27 FIRST_NUMBER = ISD::BUILTIN_OP_END, 28 RET_FLAG, 29 URET_FLAG, 30 SRET_FLAG, 31 MRET_FLAG, 32 CALL, 33 /// Select with condition operator - This selects between a true value and 34 /// a false value (ops #3 and #4) based on the boolean result of comparing 35 /// the lhs and rhs (ops #0 and #1) of a conditional expression with the 36 /// condition code in op #2, a XLenVT constant from the ISD::CondCode enum. 37 /// The lhs and rhs are XLenVT integers. The true and false values can be 38 /// integer or floating point. 39 SELECT_CC, 40 BR_CC, 41 BuildPairF64, 42 SplitF64, 43 TAIL, 44 // Multiply high for signedxunsigned. 45 MULHSU, 46 // RV64I shifts, directly matching the semantics of the named RISC-V 47 // instructions. 48 SLLW, 49 SRAW, 50 SRLW, 51 // 32-bit operations from RV64M that can't be simply matched with a pattern 52 // at instruction selection time. These have undefined behavior for division 53 // by 0 or overflow (divw) like their target independent counterparts. 54 DIVW, 55 DIVUW, 56 REMUW, 57 // RV64IB rotates, directly matching the semantics of the named RISC-V 58 // instructions. 59 ROLW, 60 RORW, 61 // RV64IZbb bit counting instructions directly matching the semantics of the 62 // named RISC-V instructions. 63 CLZW, 64 CTZW, 65 // RV64IB/RV32IB funnel shifts, with the semantics of the named RISC-V 66 // instructions, but the same operand order as fshl/fshr intrinsics. 67 FSR, 68 FSL, 69 // RV64IB funnel shifts, with the semantics of the named RISC-V instructions, 70 // but the same operand order as fshl/fshr intrinsics. 71 FSRW, 72 FSLW, 73 // FPR<->GPR transfer operations when the FPR is smaller than XLEN, needed as 74 // XLEN is the only legal integer width. 75 // 76 // FMV_H_X matches the semantics of the FMV.H.X. 77 // FMV_X_ANYEXTH is similar to FMV.X.H but has an any-extended result. 78 // FMV_W_X_RV64 matches the semantics of the FMV.W.X. 79 // FMV_X_ANYEXTW_RV64 is similar to FMV.X.W but has an any-extended result. 80 // 81 // This is a more convenient semantic for producing dagcombines that remove 82 // unnecessary GPR->FPR->GPR moves. 83 FMV_H_X, 84 FMV_X_ANYEXTH, 85 FMV_W_X_RV64, 86 FMV_X_ANYEXTW_RV64, 87 // READ_CYCLE_WIDE - A read of the 64-bit cycle CSR on a 32-bit target 88 // (returns (Lo, Hi)). It takes a chain operand. 89 READ_CYCLE_WIDE, 90 // Generalized Reverse and Generalized Or-Combine - directly matching the 91 // semantics of the named RISC-V instructions. Lowered as custom nodes as 92 // TableGen chokes when faced with commutative permutations in deeply-nested 93 // DAGs. Each node takes an input operand and a control operand and outputs a 94 // bit-manipulated version of input. All operands are i32 or XLenVT. 95 GREV, 96 GREVW, 97 GORC, 98 GORCW, 99 SHFL, 100 SHFLW, 101 UNSHFL, 102 UNSHFLW, 103 // Bit Compress/Decompress implement the generic bit extract and bit deposit 104 // functions. This operation is also referred to as bit gather/scatter, bit 105 // pack/unpack, parallel extract/deposit, compress/expand, or right 106 // compress/right expand. 107 BCOMPRESS, 108 BCOMPRESSW, 109 BDECOMPRESS, 110 BDECOMPRESSW, 111 // Vector Extension 112 // VMV_V_X_VL matches the semantics of vmv.v.x but includes an extra operand 113 // for the VL value to be used for the operation. 114 VMV_V_X_VL, 115 // VFMV_V_F_VL matches the semantics of vfmv.v.f but includes an extra operand 116 // for the VL value to be used for the operation. 117 VFMV_V_F_VL, 118 // VMV_X_S matches the semantics of vmv.x.s. The result is always XLenVT sign 119 // extended from the vector element size. 120 VMV_X_S, 121 // VMV_S_X_VL matches the semantics of vmv.s.x. It carries a VL operand. 122 VMV_S_X_VL, 123 // VFMV_S_F_VL matches the semantics of vfmv.s.f. It carries a VL operand. 124 VFMV_S_F_VL, 125 // Splats an i64 scalar to a vector type (with element type i64) where the 126 // scalar is a sign-extended i32. 127 SPLAT_VECTOR_I64, 128 // Splats an 64-bit value that has been split into two i32 parts. This is 129 // expanded late to two scalar stores and a stride 0 vector load. 130 SPLAT_VECTOR_SPLIT_I64_VL, 131 // Read VLENB CSR 132 READ_VLENB, 133 // Truncates a RVV integer vector by one power-of-two. Carries both an extra 134 // mask and VL operand. 135 TRUNCATE_VECTOR_VL, 136 // Matches the semantics of vslideup/vslidedown. The first operand is the 137 // pass-thru operand, the second is the source vector, the third is the 138 // XLenVT index (either constant or non-constant), the fourth is the mask 139 // and the fifth the VL. 140 VSLIDEUP_VL, 141 VSLIDEDOWN_VL, 142 // Matches the semantics of vslide1up/slide1down. The first operand is the 143 // source vector, the second is the XLenVT scalar value. The third and fourth 144 // operands are the mask and VL operands. 145 VSLIDE1UP_VL, 146 VSLIDE1DOWN_VL, 147 // Matches the semantics of the vid.v instruction, with a mask and VL 148 // operand. 149 VID_VL, 150 // Matches the semantics of the vfcnvt.rod function (Convert double-width 151 // float to single-width float, rounding towards odd). Takes a double-width 152 // float vector and produces a single-width float vector. Also has a mask and 153 // VL operand. 154 VFNCVT_ROD_VL, 155 // These nodes match the semantics of the corresponding RVV vector reduction 156 // instructions. They produce a vector result which is the reduction 157 // performed over the first vector operand plus the first element of the 158 // second vector operand. The first operand is an unconstrained vector type, 159 // and the result and second operand's types are expected to be the 160 // corresponding full-width LMUL=1 type for the first operand: 161 // nxv8i8 = vecreduce_add nxv32i8, nxv8i8 162 // nxv2i32 = vecreduce_add nxv8i32, nxv2i32 163 // The different in types does introduce extra vsetvli instructions but 164 // similarly it reduces the number of registers consumed per reduction. 165 // Also has a mask and VL operand. 166 VECREDUCE_ADD_VL, 167 VECREDUCE_UMAX_VL, 168 VECREDUCE_SMAX_VL, 169 VECREDUCE_UMIN_VL, 170 VECREDUCE_SMIN_VL, 171 VECREDUCE_AND_VL, 172 VECREDUCE_OR_VL, 173 VECREDUCE_XOR_VL, 174 VECREDUCE_FADD_VL, 175 VECREDUCE_SEQ_FADD_VL, 176 VECREDUCE_FMIN_VL, 177 VECREDUCE_FMAX_VL, 178 179 // Vector binary and unary ops with a mask as a third operand, and VL as a 180 // fourth operand. 181 // FIXME: Can we replace these with ISD::VP_*? 182 ADD_VL, 183 AND_VL, 184 MUL_VL, 185 OR_VL, 186 SDIV_VL, 187 SHL_VL, 188 SREM_VL, 189 SRA_VL, 190 SRL_VL, 191 SUB_VL, 192 UDIV_VL, 193 UREM_VL, 194 XOR_VL, 195 FADD_VL, 196 FSUB_VL, 197 FMUL_VL, 198 FDIV_VL, 199 FNEG_VL, 200 FABS_VL, 201 FSQRT_VL, 202 FMA_VL, 203 FCOPYSIGN_VL, 204 SMIN_VL, 205 SMAX_VL, 206 UMIN_VL, 207 UMAX_VL, 208 FMINNUM_VL, 209 FMAXNUM_VL, 210 MULHS_VL, 211 MULHU_VL, 212 FP_TO_SINT_VL, 213 FP_TO_UINT_VL, 214 SINT_TO_FP_VL, 215 UINT_TO_FP_VL, 216 FP_ROUND_VL, 217 FP_EXTEND_VL, 218 219 // Vector compare producing a mask. Fourth operand is input mask. Fifth 220 // operand is VL. 221 SETCC_VL, 222 223 // Vector select with an additional VL operand. This operation is unmasked. 224 VSELECT_VL, 225 226 // Mask binary operators. 227 VMAND_VL, 228 VMOR_VL, 229 VMXOR_VL, 230 231 // Set mask vector to all zeros or ones. 232 VMCLR_VL, 233 VMSET_VL, 234 235 // Matches the semantics of vrgather.vx and vrgather.vv with an extra operand 236 // for VL. 237 VRGATHER_VX_VL, 238 VRGATHER_VV_VL, 239 VRGATHEREI16_VV_VL, 240 241 // Vector sign/zero extend with additional mask & VL operands. 242 VSEXT_VL, 243 VZEXT_VL, 244 // vpopc.m with additional mask and VL operands. 245 VPOPC_VL, 246 247 // Reads value of CSR. 248 // The first operand is a chain pointer. The second specifies address of the 249 // required CSR. Two results are produced, the read value and the new chain 250 // pointer. 251 READ_CSR, 252 // Write value to CSR. 253 // The first operand is a chain pointer, the second specifies address of the 254 // required CSR and the third is the value to write. The result is the new 255 // chain pointer. 256 WRITE_CSR, 257 // Read and write value of CSR. 258 // The first operand is a chain pointer, the second specifies address of the 259 // required CSR and the third is the value to write. Two results are produced, 260 // the value read before the modification and the new chain pointer. 261 SWAP_CSR, 262 263 // Memory opcodes start here. 264 VLE_VL = ISD::FIRST_TARGET_MEMORY_OPCODE, 265 VSE_VL, 266 267 // WARNING: Do not add anything in the end unless you want the node to 268 // have memop! In fact, starting from FIRST_TARGET_MEMORY_OPCODE all 269 // opcodes will be thought as target memory ops! 270 }; 271 } // namespace RISCVISD 272 273 class RISCVTargetLowering : public TargetLowering { 274 const RISCVSubtarget &Subtarget; 275 276 public: 277 explicit RISCVTargetLowering(const TargetMachine &TM, 278 const RISCVSubtarget &STI); 279 280 const RISCVSubtarget &getSubtarget() const { return Subtarget; } 281 282 bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I, 283 MachineFunction &MF, 284 unsigned Intrinsic) const override; 285 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, 286 unsigned AS, 287 Instruction *I = nullptr) const override; 288 bool isLegalICmpImmediate(int64_t Imm) const override; 289 bool isLegalAddImmediate(int64_t Imm) const override; 290 bool isTruncateFree(Type *SrcTy, Type *DstTy) const override; 291 bool isTruncateFree(EVT SrcVT, EVT DstVT) const override; 292 bool isZExtFree(SDValue Val, EVT VT2) const override; 293 bool isSExtCheaperThanZExt(EVT SrcVT, EVT DstVT) const override; 294 bool isCheapToSpeculateCttz() const override; 295 bool isCheapToSpeculateCtlz() const override; 296 bool isFPImmLegal(const APFloat &Imm, EVT VT, 297 bool ForCodeSize) const override; 298 299 bool softPromoteHalfType() const override { return true; } 300 301 /// Return the register type for a given MVT, ensuring vectors are treated 302 /// as a series of gpr sized integers. 303 MVT getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC, 304 EVT VT) const override; 305 306 /// Return the number of registers for a given MVT, ensuring vectors are 307 /// treated as a series of gpr sized integers. 308 unsigned getNumRegistersForCallingConv(LLVMContext &Context, 309 CallingConv::ID CC, 310 EVT VT) const override; 311 312 /// Return true if the given shuffle mask can be codegen'd directly, or if it 313 /// should be stack expanded. 314 bool isShuffleMaskLegal(ArrayRef<int> M, EVT VT) const override; 315 316 bool hasBitPreservingFPLogic(EVT VT) const override; 317 bool 318 shouldExpandBuildVectorWithShuffles(EVT VT, 319 unsigned DefinedValues) const override; 320 321 // Provide custom lowering hooks for some operations. 322 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override; 323 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results, 324 SelectionDAG &DAG) const override; 325 326 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override; 327 328 bool targetShrinkDemandedConstant(SDValue Op, const APInt &DemandedBits, 329 const APInt &DemandedElts, 330 TargetLoweringOpt &TLO) const override; 331 332 void computeKnownBitsForTargetNode(const SDValue Op, 333 KnownBits &Known, 334 const APInt &DemandedElts, 335 const SelectionDAG &DAG, 336 unsigned Depth) const override; 337 unsigned ComputeNumSignBitsForTargetNode(SDValue Op, 338 const APInt &DemandedElts, 339 const SelectionDAG &DAG, 340 unsigned Depth) const override; 341 342 // This method returns the name of a target specific DAG node. 343 const char *getTargetNodeName(unsigned Opcode) const override; 344 345 ConstraintType getConstraintType(StringRef Constraint) const override; 346 347 unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override; 348 349 std::pair<unsigned, const TargetRegisterClass *> 350 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, 351 StringRef Constraint, MVT VT) const override; 352 353 void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, 354 std::vector<SDValue> &Ops, 355 SelectionDAG &DAG) const override; 356 357 MachineBasicBlock * 358 EmitInstrWithCustomInserter(MachineInstr &MI, 359 MachineBasicBlock *BB) const override; 360 361 EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, 362 EVT VT) const override; 363 364 bool convertSetCCLogicToBitwiseLogic(EVT VT) const override { 365 return VT.isScalarInteger(); 366 } 367 bool convertSelectOfConstantsToMath(EVT VT) const override { return true; } 368 369 bool shouldInsertFencesForAtomic(const Instruction *I) const override { 370 return isa<LoadInst>(I) || isa<StoreInst>(I); 371 } 372 Instruction *emitLeadingFence(IRBuilderBase &Builder, Instruction *Inst, 373 AtomicOrdering Ord) const override; 374 Instruction *emitTrailingFence(IRBuilderBase &Builder, Instruction *Inst, 375 AtomicOrdering Ord) const override; 376 377 bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF, 378 EVT VT) const override; 379 380 ISD::NodeType getExtendForAtomicOps() const override { 381 return ISD::SIGN_EXTEND; 382 } 383 384 ISD::NodeType getExtendForAtomicCmpSwapArg() const override { 385 return ISD::SIGN_EXTEND; 386 } 387 388 bool shouldExpandShift(SelectionDAG &DAG, SDNode *N) const override { 389 if (DAG.getMachineFunction().getFunction().hasMinSize()) 390 return false; 391 return true; 392 } 393 bool isDesirableToCommuteWithShift(const SDNode *N, 394 CombineLevel Level) const override; 395 396 /// If a physical register, this returns the register that receives the 397 /// exception address on entry to an EH pad. 398 Register 399 getExceptionPointerRegister(const Constant *PersonalityFn) const override; 400 401 /// If a physical register, this returns the register that receives the 402 /// exception typeid on entry to a landing pad. 403 Register 404 getExceptionSelectorRegister(const Constant *PersonalityFn) const override; 405 406 bool shouldExtendTypeInLibCall(EVT Type) const override; 407 bool shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const override; 408 409 /// Returns the register with the specified architectural or ABI name. This 410 /// method is necessary to lower the llvm.read_register.* and 411 /// llvm.write_register.* intrinsics. Allocatable registers must be reserved 412 /// with the clang -ffixed-xX flag for access to be allowed. 413 Register getRegisterByName(const char *RegName, LLT VT, 414 const MachineFunction &MF) const override; 415 416 // Lower incoming arguments, copy physregs into vregs 417 SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, 418 bool IsVarArg, 419 const SmallVectorImpl<ISD::InputArg> &Ins, 420 const SDLoc &DL, SelectionDAG &DAG, 421 SmallVectorImpl<SDValue> &InVals) const override; 422 bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, 423 bool IsVarArg, 424 const SmallVectorImpl<ISD::OutputArg> &Outs, 425 LLVMContext &Context) const override; 426 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, 427 const SmallVectorImpl<ISD::OutputArg> &Outs, 428 const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL, 429 SelectionDAG &DAG) const override; 430 SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI, 431 SmallVectorImpl<SDValue> &InVals) const override; 432 433 bool shouldConvertConstantLoadToIntImm(const APInt &Imm, 434 Type *Ty) const override { 435 return true; 436 } 437 bool mayBeEmittedAsTailCall(const CallInst *CI) const override; 438 bool shouldConsiderGEPOffsetSplit() const override { return true; } 439 440 bool decomposeMulByConstant(LLVMContext &Context, EVT VT, 441 SDValue C) const override; 442 443 TargetLowering::AtomicExpansionKind 444 shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override; 445 Value *emitMaskedAtomicRMWIntrinsic(IRBuilderBase &Builder, AtomicRMWInst *AI, 446 Value *AlignedAddr, Value *Incr, 447 Value *Mask, Value *ShiftAmt, 448 AtomicOrdering Ord) const override; 449 TargetLowering::AtomicExpansionKind 450 shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *CI) const override; 451 Value *emitMaskedAtomicCmpXchgIntrinsic(IRBuilderBase &Builder, 452 AtomicCmpXchgInst *CI, 453 Value *AlignedAddr, Value *CmpVal, 454 Value *NewVal, Value *Mask, 455 AtomicOrdering Ord) const override; 456 457 /// Returns true if the target allows unaligned memory accesses of the 458 /// specified type. 459 bool allowsMisalignedMemoryAccesses( 460 EVT VT, unsigned AddrSpace = 0, Align Alignment = Align(1), 461 MachineMemOperand::Flags Flags = MachineMemOperand::MONone, 462 bool *Fast = nullptr) const override; 463 464 bool splitValueIntoRegisterParts(SelectionDAG &DAG, const SDLoc &DL, 465 SDValue Val, SDValue *Parts, 466 unsigned NumParts, MVT PartVT, 467 Optional<CallingConv::ID> CC) const override; 468 469 SDValue 470 joinRegisterPartsIntoValue(SelectionDAG &DAG, const SDLoc &DL, 471 const SDValue *Parts, unsigned NumParts, 472 MVT PartVT, EVT ValueVT, 473 Optional<CallingConv::ID> CC) const override; 474 475 static RISCVII::VLMUL getLMUL(MVT VT); 476 static unsigned getRegClassIDForLMUL(RISCVII::VLMUL LMul); 477 static unsigned getSubregIndexByMVT(MVT VT, unsigned Index); 478 static unsigned getRegClassIDForVecVT(MVT VT); 479 static std::pair<unsigned, unsigned> 480 decomposeSubvectorInsertExtractToSubRegs(MVT VecVT, MVT SubVecVT, 481 unsigned InsertExtractIdx, 482 const RISCVRegisterInfo *TRI); 483 MVT getContainerForFixedLengthVector(MVT VT) const; 484 485 bool shouldRemoveExtendFromGSIndex(EVT VT) const override; 486 487 private: 488 /// RISCVCCAssignFn - This target-specific function extends the default 489 /// CCValAssign with additional information used to lower RISC-V calling 490 /// conventions. 491 typedef bool RISCVCCAssignFn(const DataLayout &DL, RISCVABI::ABI, 492 unsigned ValNo, MVT ValVT, MVT LocVT, 493 CCValAssign::LocInfo LocInfo, 494 ISD::ArgFlagsTy ArgFlags, CCState &State, 495 bool IsFixed, bool IsRet, Type *OrigTy, 496 const RISCVTargetLowering &TLI, 497 Optional<unsigned> FirstMaskArgument); 498 499 void analyzeInputArgs(MachineFunction &MF, CCState &CCInfo, 500 const SmallVectorImpl<ISD::InputArg> &Ins, bool IsRet, 501 RISCVCCAssignFn Fn) const; 502 void analyzeOutputArgs(MachineFunction &MF, CCState &CCInfo, 503 const SmallVectorImpl<ISD::OutputArg> &Outs, 504 bool IsRet, CallLoweringInfo *CLI, 505 RISCVCCAssignFn Fn) const; 506 507 template <class NodeTy> 508 SDValue getAddr(NodeTy *N, SelectionDAG &DAG, bool IsLocal = true) const; 509 510 SDValue getStaticTLSAddr(GlobalAddressSDNode *N, SelectionDAG &DAG, 511 bool UseGOT) const; 512 SDValue getDynamicTLSAddr(GlobalAddressSDNode *N, SelectionDAG &DAG) const; 513 514 SDValue lowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const; 515 SDValue lowerBlockAddress(SDValue Op, SelectionDAG &DAG) const; 516 SDValue lowerConstantPool(SDValue Op, SelectionDAG &DAG) const; 517 SDValue lowerJumpTable(SDValue Op, SelectionDAG &DAG) const; 518 SDValue lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const; 519 SDValue lowerSELECT(SDValue Op, SelectionDAG &DAG) const; 520 SDValue lowerBRCOND(SDValue Op, SelectionDAG &DAG) const; 521 SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const; 522 SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const; 523 SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const; 524 SDValue lowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const; 525 SDValue lowerShiftRightParts(SDValue Op, SelectionDAG &DAG, bool IsSRA) const; 526 SDValue lowerSPLAT_VECTOR_PARTS(SDValue Op, SelectionDAG &DAG) const; 527 SDValue lowerVectorMaskSplat(SDValue Op, SelectionDAG &DAG) const; 528 SDValue lowerVectorMaskExt(SDValue Op, SelectionDAG &DAG, 529 int64_t ExtTrueVal) const; 530 SDValue lowerVectorMaskTrunc(SDValue Op, SelectionDAG &DAG) const; 531 SDValue lowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const; 532 SDValue lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const; 533 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const; 534 SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const; 535 SDValue lowerVECREDUCE(SDValue Op, SelectionDAG &DAG) const; 536 SDValue lowerVectorMaskVECREDUCE(SDValue Op, SelectionDAG &DAG) const; 537 SDValue lowerFPVECREDUCE(SDValue Op, SelectionDAG &DAG) const; 538 SDValue lowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const; 539 SDValue lowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const; 540 SDValue lowerSTEP_VECTOR(SDValue Op, SelectionDAG &DAG) const; 541 SDValue lowerVECTOR_REVERSE(SDValue Op, SelectionDAG &DAG) const; 542 SDValue lowerABS(SDValue Op, SelectionDAG &DAG) const; 543 SDValue lowerMLOAD(SDValue Op, SelectionDAG &DAG) const; 544 SDValue lowerMSTORE(SDValue Op, SelectionDAG &DAG) const; 545 SDValue lowerFixedLengthVectorFCOPYSIGNToRVV(SDValue Op, 546 SelectionDAG &DAG) const; 547 SDValue lowerMGATHER(SDValue Op, SelectionDAG &DAG) const; 548 SDValue lowerMSCATTER(SDValue Op, SelectionDAG &DAG) const; 549 SDValue lowerFixedLengthVectorLoadToRVV(SDValue Op, SelectionDAG &DAG) const; 550 SDValue lowerFixedLengthVectorStoreToRVV(SDValue Op, SelectionDAG &DAG) const; 551 SDValue lowerFixedLengthVectorSetccToRVV(SDValue Op, SelectionDAG &DAG) const; 552 SDValue lowerFixedLengthVectorLogicOpToRVV(SDValue Op, SelectionDAG &DAG, 553 unsigned MaskOpc, 554 unsigned VecOpc) const; 555 SDValue lowerFixedLengthVectorShiftToRVV(SDValue Op, SelectionDAG &DAG) const; 556 SDValue lowerFixedLengthVectorSelectToRVV(SDValue Op, 557 SelectionDAG &DAG) const; 558 SDValue lowerToScalableOp(SDValue Op, SelectionDAG &DAG, unsigned NewOpc, 559 bool HasMask = true) const; 560 SDValue lowerVPOp(SDValue Op, SelectionDAG &DAG, unsigned RISCVISDOpc) const; 561 SDValue lowerFixedLengthVectorExtendToRVV(SDValue Op, SelectionDAG &DAG, 562 unsigned ExtendOpc) const; 563 SDValue lowerGET_ROUNDING(SDValue Op, SelectionDAG &DAG) const; 564 SDValue lowerSET_ROUNDING(SDValue Op, SelectionDAG &DAG) const; 565 566 SDValue expandUnalignedRVVLoad(SDValue Op, SelectionDAG &DAG) const; 567 SDValue expandUnalignedRVVStore(SDValue Op, SelectionDAG &DAG) const; 568 569 bool isEligibleForTailCallOptimization( 570 CCState &CCInfo, CallLoweringInfo &CLI, MachineFunction &MF, 571 const SmallVector<CCValAssign, 16> &ArgLocs) const; 572 573 /// Generate error diagnostics if any register used by CC has been marked 574 /// reserved. 575 void validateCCReservedRegs( 576 const SmallVectorImpl<std::pair<llvm::Register, llvm::SDValue>> &Regs, 577 MachineFunction &MF) const; 578 579 bool useRVVForFixedLengthVectorVT(MVT VT) const; 580 581 MVT getVPExplicitVectorLengthTy() const override; 582 583 /// RVV code generation for fixed length vectors does not lower all 584 /// BUILD_VECTORs. This makes BUILD_VECTOR legalisation a source of stores to 585 /// merge. However, merging them creates a BUILD_VECTOR that is just as 586 /// illegal as the original, thus leading to an infinite legalisation loop. 587 /// NOTE: Once BUILD_VECTOR can be custom lowered for all legal vector types, 588 /// this override can be removed. 589 bool mergeStoresAfterLegalization(EVT VT) const override; 590 }; 591 592 namespace RISCV { 593 // We use 64 bits as the known part in the scalable vector types. 594 static constexpr unsigned RVVBitsPerBlock = 64; 595 } // namespace RISCV 596 597 namespace RISCVVIntrinsicsTable { 598 599 struct RISCVVIntrinsicInfo { 600 unsigned IntrinsicID; 601 uint8_t SplatOperand; 602 }; 603 604 using namespace RISCV; 605 606 #define GET_RISCVVIntrinsicsTable_DECL 607 #include "RISCVGenSearchableTables.inc" 608 609 } // end namespace RISCVVIntrinsicsTable 610 611 } // end namespace llvm 612 613 #endif 614