1 //===-- RISCVISelLowering.h - RISCV DAG Lowering Interface ------*- C++ -*-===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines the interfaces that RISCV uses to lower LLVM code into a
11 // selection DAG.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #ifndef LLVM_LIB_TARGET_RISCV_RISCVISELLOWERING_H
16 #define LLVM_LIB_TARGET_RISCV_RISCVISELLOWERING_H
17 
18 #include "RISCV.h"
19 #include "llvm/CodeGen/SelectionDAG.h"
20 #include "llvm/CodeGen/TargetLowering.h"
21 
22 namespace llvm {
23 class RISCVSubtarget;
24 namespace RISCVISD {
25 enum NodeType : unsigned {
26   FIRST_NUMBER = ISD::BUILTIN_OP_END,
27   RET_FLAG,
28   URET_FLAG,
29   SRET_FLAG,
30   MRET_FLAG,
31   CALL,
32   SELECT_CC,
33   BuildPairF64,
34   SplitF64,
35   TAIL
36 };
37 }
38 
39 class RISCVTargetLowering : public TargetLowering {
40   const RISCVSubtarget &Subtarget;
41 
42 public:
43   explicit RISCVTargetLowering(const TargetMachine &TM,
44                                const RISCVSubtarget &STI);
45 
46   bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I,
47                           MachineFunction &MF,
48                           unsigned Intrinsic) const override;
49   bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty,
50                              unsigned AS,
51                              Instruction *I = nullptr) const override;
52   bool isLegalICmpImmediate(int64_t Imm) const override;
53   bool isLegalAddImmediate(int64_t Imm) const override;
54   bool isTruncateFree(Type *SrcTy, Type *DstTy) const override;
55   bool isTruncateFree(EVT SrcVT, EVT DstVT) const override;
56   bool isZExtFree(SDValue Val, EVT VT2) const override;
57 
58   // Provide custom lowering hooks for some operations.
59   SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
60 
61   SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
62 
63   // This method returns the name of a target specific DAG node.
64   const char *getTargetNodeName(unsigned Opcode) const override;
65 
66   std::pair<unsigned, const TargetRegisterClass *>
67   getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
68                                StringRef Constraint, MVT VT) const override;
69 
70   MachineBasicBlock *
71   EmitInstrWithCustomInserter(MachineInstr &MI,
72                               MachineBasicBlock *BB) const override;
73 
74   EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
75                          EVT VT) const override;
76 
77   bool shouldInsertFencesForAtomic(const Instruction *I) const override {
78     return isa<LoadInst>(I) || isa<StoreInst>(I);
79   }
80   Instruction *emitLeadingFence(IRBuilder<> &Builder, Instruction *Inst,
81                                 AtomicOrdering Ord) const override;
82   Instruction *emitTrailingFence(IRBuilder<> &Builder, Instruction *Inst,
83                                  AtomicOrdering Ord) const override;
84 
85 private:
86   void analyzeInputArgs(MachineFunction &MF, CCState &CCInfo,
87                         const SmallVectorImpl<ISD::InputArg> &Ins,
88                         bool IsRet) const;
89   void analyzeOutputArgs(MachineFunction &MF, CCState &CCInfo,
90                          const SmallVectorImpl<ISD::OutputArg> &Outs,
91                          bool IsRet, CallLoweringInfo *CLI) const;
92   // Lower incoming arguments, copy physregs into vregs
93   SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,
94                                bool IsVarArg,
95                                const SmallVectorImpl<ISD::InputArg> &Ins,
96                                const SDLoc &DL, SelectionDAG &DAG,
97                                SmallVectorImpl<SDValue> &InVals) const override;
98   bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
99                       bool IsVarArg,
100                       const SmallVectorImpl<ISD::OutputArg> &Outs,
101                       LLVMContext &Context) const override;
102   SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
103                       const SmallVectorImpl<ISD::OutputArg> &Outs,
104                       const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL,
105                       SelectionDAG &DAG) const override;
106   SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI,
107                     SmallVectorImpl<SDValue> &InVals) const override;
108   bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
109                                          Type *Ty) const override {
110     return true;
111   }
112   SDValue lowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
113   SDValue lowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
114   SDValue lowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
115   SDValue lowerSELECT(SDValue Op, SelectionDAG &DAG) const;
116   SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const;
117   SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
118   SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
119 
120   bool IsEligibleForTailCallOptimization(CCState &CCInfo,
121     CallLoweringInfo &CLI, MachineFunction &MF,
122     const SmallVector<CCValAssign, 16> &ArgLocs) const;
123 
124   TargetLowering::AtomicExpansionKind
125   shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override;
126   virtual Value *emitMaskedAtomicRMWIntrinsic(
127       IRBuilder<> &Builder, AtomicRMWInst *AI, Value *AlignedAddr, Value *Incr,
128       Value *Mask, Value *ShiftAmt, AtomicOrdering Ord) const override;
129 };
130 }
131 
132 #endif
133