1 //===-- RISCVISelLowering.h - RISCV DAG Lowering Interface ------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file defines the interfaces that RISCV uses to lower LLVM code into a 10 // selection DAG. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #ifndef LLVM_LIB_TARGET_RISCV_RISCVISELLOWERING_H 15 #define LLVM_LIB_TARGET_RISCV_RISCVISELLOWERING_H 16 17 #include "RISCV.h" 18 #include "llvm/CodeGen/CallingConvLower.h" 19 #include "llvm/CodeGen/SelectionDAG.h" 20 #include "llvm/CodeGen/TargetLowering.h" 21 22 namespace llvm { 23 class RISCVSubtarget; 24 struct RISCVRegisterInfo; 25 namespace RISCVISD { 26 enum NodeType : unsigned { 27 FIRST_NUMBER = ISD::BUILTIN_OP_END, 28 RET_FLAG, 29 URET_FLAG, 30 SRET_FLAG, 31 MRET_FLAG, 32 CALL, 33 /// Select with condition operator - This selects between a true value and 34 /// a false value (ops #3 and #4) based on the boolean result of comparing 35 /// the lhs and rhs (ops #0 and #1) of a conditional expression with the 36 /// condition code in op #2, a XLenVT constant from the ISD::CondCode enum. 37 /// The lhs and rhs are XLenVT integers. The true and false values can be 38 /// integer or floating point. 39 SELECT_CC, 40 BR_CC, 41 BuildPairF64, 42 SplitF64, 43 TAIL, 44 45 // Add the Lo 12 bits from an address. Selected to ADDI. 46 ADD_LO, 47 // Get the Hi 20 bits from an address. Selected to LUI. 48 HI, 49 50 // Represents an AUIPC+ADDI pair. Selected to PseudoLLA. 51 LLA, 52 53 // Selected as PseudoAddTPRel. Used to emit a TP-relative relocation. 54 ADD_TPREL, 55 56 // Load address. 57 LA_TLS_GD, 58 59 // Multiply high for signedxunsigned. 60 MULHSU, 61 // RV64I shifts, directly matching the semantics of the named RISC-V 62 // instructions. 63 SLLW, 64 SRAW, 65 SRLW, 66 // 32-bit operations from RV64M that can't be simply matched with a pattern 67 // at instruction selection time. These have undefined behavior for division 68 // by 0 or overflow (divw) like their target independent counterparts. 69 DIVW, 70 DIVUW, 71 REMUW, 72 // RV64IB rotates, directly matching the semantics of the named RISC-V 73 // instructions. 74 ROLW, 75 RORW, 76 // RV64IZbb bit counting instructions directly matching the semantics of the 77 // named RISC-V instructions. 78 CLZW, 79 CTZW, 80 // RV64IB/RV32IB funnel shifts, with the semantics of the named RISC-V 81 // instructions. Operand order is rs1, rs3, rs2/shamt. 82 FSR, 83 FSL, 84 // RV64IB funnel shifts, with the semantics of the named RISC-V instructions. 85 // Operand order is rs1, rs3, rs2/shamt. 86 FSRW, 87 FSLW, 88 // FPR<->GPR transfer operations when the FPR is smaller than XLEN, needed as 89 // XLEN is the only legal integer width. 90 // 91 // FMV_H_X matches the semantics of the FMV.H.X. 92 // FMV_X_ANYEXTH is similar to FMV.X.H but has an any-extended result. 93 // FMV_X_SIGNEXTH is similar to FMV.X.H and has a sign-extended result. 94 // FMV_W_X_RV64 matches the semantics of the FMV.W.X. 95 // FMV_X_ANYEXTW_RV64 is similar to FMV.X.W but has an any-extended result. 96 // 97 // This is a more convenient semantic for producing dagcombines that remove 98 // unnecessary GPR->FPR->GPR moves. 99 FMV_H_X, 100 FMV_X_ANYEXTH, 101 FMV_X_SIGNEXTH, 102 FMV_W_X_RV64, 103 FMV_X_ANYEXTW_RV64, 104 // FP to XLen int conversions. Corresponds to fcvt.l(u).s/d/h on RV64 and 105 // fcvt.w(u).s/d/h on RV32. Unlike FP_TO_S/UINT these saturate out of 106 // range inputs. These are used for FP_TO_S/UINT_SAT lowering. Rounding mode 107 // is passed as a TargetConstant operand using the RISCVFPRndMode enum. 108 FCVT_X, 109 FCVT_XU, 110 // FP to 32 bit int conversions for RV64. These are used to keep track of the 111 // result being sign extended to 64 bit. These saturate out of range inputs. 112 // Used for FP_TO_S/UINT and FP_TO_S/UINT_SAT lowering. Rounding mode 113 // is passed as a TargetConstant operand using the RISCVFPRndMode enum. 114 FCVT_W_RV64, 115 FCVT_WU_RV64, 116 // READ_CYCLE_WIDE - A read of the 64-bit cycle CSR on a 32-bit target 117 // (returns (Lo, Hi)). It takes a chain operand. 118 READ_CYCLE_WIDE, 119 // Generalized Reverse and Generalized Or-Combine - directly matching the 120 // semantics of the named RISC-V instructions. Lowered as custom nodes as 121 // TableGen chokes when faced with commutative permutations in deeply-nested 122 // DAGs. Each node takes an input operand and a control operand and outputs a 123 // bit-manipulated version of input. All operands are i32 or XLenVT. 124 GREV, 125 GREVW, 126 GORC, 127 GORCW, 128 SHFL, 129 SHFLW, 130 UNSHFL, 131 UNSHFLW, 132 // Bit Compress/Decompress implement the generic bit extract and bit deposit 133 // functions. This operation is also referred to as bit gather/scatter, bit 134 // pack/unpack, parallel extract/deposit, compress/expand, or right 135 // compress/right expand. 136 BCOMPRESS, 137 BCOMPRESSW, 138 BDECOMPRESS, 139 BDECOMPRESSW, 140 // The bit field place (bfp) instruction places up to XLEN/2 LSB bits from rs2 141 // into the value in rs1. The upper bits of rs2 control the length of the bit 142 // field and target position. The layout of rs2 is chosen in a way that makes 143 // it possible to construct rs2 easily using pack[h] instructions and/or 144 // andi/lui. 145 BFP, 146 BFPW, 147 // Vector Extension 148 // VMV_V_X_VL matches the semantics of vmv.v.x but includes an extra operand 149 // for the VL value to be used for the operation. The first operand is 150 // passthru operand. 151 VMV_V_X_VL, 152 // VFMV_V_F_VL matches the semantics of vfmv.v.f but includes an extra operand 153 // for the VL value to be used for the operation. The first operand is 154 // passthru operand. 155 VFMV_V_F_VL, 156 // VMV_X_S matches the semantics of vmv.x.s. The result is always XLenVT sign 157 // extended from the vector element size. 158 VMV_X_S, 159 // VMV_S_X_VL matches the semantics of vmv.s.x. It carries a VL operand. 160 VMV_S_X_VL, 161 // VFMV_S_F_VL matches the semantics of vfmv.s.f. It carries a VL operand. 162 VFMV_S_F_VL, 163 // Splats an 64-bit value that has been split into two i32 parts. This is 164 // expanded late to two scalar stores and a stride 0 vector load. 165 // The first operand is passthru operand. 166 SPLAT_VECTOR_SPLIT_I64_VL, 167 // Read VLENB CSR 168 READ_VLENB, 169 // Truncates a RVV integer vector by one power-of-two. Carries both an extra 170 // mask and VL operand. 171 TRUNCATE_VECTOR_VL, 172 // Matches the semantics of vslideup/vslidedown. The first operand is the 173 // pass-thru operand, the second is the source vector, the third is the 174 // XLenVT index (either constant or non-constant), the fourth is the mask 175 // and the fifth the VL. 176 VSLIDEUP_VL, 177 VSLIDEDOWN_VL, 178 // Matches the semantics of vslide1up/slide1down. The first operand is 179 // passthru operand, the second is source vector, third is the XLenVT scalar 180 // value. The fourth and fifth operands are the mask and VL operands. 181 VSLIDE1UP_VL, 182 VSLIDE1DOWN_VL, 183 // Matches the semantics of the vid.v instruction, with a mask and VL 184 // operand. 185 VID_VL, 186 // Matches the semantics of the vfcnvt.rod function (Convert double-width 187 // float to single-width float, rounding towards odd). Takes a double-width 188 // float vector and produces a single-width float vector. Also has a mask and 189 // VL operand. 190 VFNCVT_ROD_VL, 191 // These nodes match the semantics of the corresponding RVV vector reduction 192 // instructions. They produce a vector result which is the reduction 193 // performed over the second vector operand plus the first element of the 194 // third vector operand. The first operand is the pass-thru operand. The 195 // second operand is an unconstrained vector type, and the result, first, and 196 // third operand's types are expected to be the corresponding full-width 197 // LMUL=1 type for the second operand: 198 // nxv8i8 = vecreduce_add nxv8i8, nxv32i8, nxv8i8 199 // nxv2i32 = vecreduce_add nxv2i32, nxv8i32, nxv2i32 200 // The different in types does introduce extra vsetvli instructions but 201 // similarly it reduces the number of registers consumed per reduction. 202 // Also has a mask and VL operand. 203 VECREDUCE_ADD_VL, 204 VECREDUCE_UMAX_VL, 205 VECREDUCE_SMAX_VL, 206 VECREDUCE_UMIN_VL, 207 VECREDUCE_SMIN_VL, 208 VECREDUCE_AND_VL, 209 VECREDUCE_OR_VL, 210 VECREDUCE_XOR_VL, 211 VECREDUCE_FADD_VL, 212 VECREDUCE_SEQ_FADD_VL, 213 VECREDUCE_FMIN_VL, 214 VECREDUCE_FMAX_VL, 215 216 // Vector binary and unary ops with a mask as a third operand, and VL as a 217 // fourth operand. 218 // FIXME: Can we replace these with ISD::VP_*? 219 ADD_VL, 220 AND_VL, 221 MUL_VL, 222 OR_VL, 223 SDIV_VL, 224 SHL_VL, 225 SREM_VL, 226 SRA_VL, 227 SRL_VL, 228 SUB_VL, 229 UDIV_VL, 230 UREM_VL, 231 XOR_VL, 232 233 SADDSAT_VL, 234 UADDSAT_VL, 235 SSUBSAT_VL, 236 USUBSAT_VL, 237 238 FADD_VL, 239 FSUB_VL, 240 FMUL_VL, 241 FDIV_VL, 242 FNEG_VL, 243 FABS_VL, 244 FSQRT_VL, 245 VFMADD_VL, 246 VFNMADD_VL, 247 VFMSUB_VL, 248 VFNMSUB_VL, 249 FCOPYSIGN_VL, 250 SMIN_VL, 251 SMAX_VL, 252 UMIN_VL, 253 UMAX_VL, 254 FMINNUM_VL, 255 FMAXNUM_VL, 256 MULHS_VL, 257 MULHU_VL, 258 FP_TO_SINT_VL, 259 FP_TO_UINT_VL, 260 SINT_TO_FP_VL, 261 UINT_TO_FP_VL, 262 FP_ROUND_VL, 263 FP_EXTEND_VL, 264 265 // Widening instructions 266 VWMUL_VL, 267 VWMULU_VL, 268 VWMULSU_VL, 269 VWADD_VL, 270 VWADDU_VL, 271 VWSUB_VL, 272 VWSUBU_VL, 273 VWADD_W_VL, 274 VWADDU_W_VL, 275 VWSUB_W_VL, 276 VWSUBU_W_VL, 277 278 // Vector compare producing a mask. Fourth operand is input mask. Fifth 279 // operand is VL. 280 SETCC_VL, 281 282 // Vector select with an additional VL operand. This operation is unmasked. 283 VSELECT_VL, 284 // Vector select with operand #2 (the value when the condition is false) tied 285 // to the destination and an additional VL operand. This operation is 286 // unmasked. 287 VP_MERGE_VL, 288 289 // Mask binary operators. 290 VMAND_VL, 291 VMOR_VL, 292 VMXOR_VL, 293 294 // Set mask vector to all zeros or ones. 295 VMCLR_VL, 296 VMSET_VL, 297 298 // Matches the semantics of vrgather.vx and vrgather.vv with extra operands 299 // for passthru and VL. Operands are (src, index, mask, passthru, vl). 300 VRGATHER_VX_VL, 301 VRGATHER_VV_VL, 302 VRGATHEREI16_VV_VL, 303 304 // Vector sign/zero extend with additional mask & VL operands. 305 VSEXT_VL, 306 VZEXT_VL, 307 308 // vcpop.m with additional mask and VL operands. 309 VCPOP_VL, 310 311 // Reads value of CSR. 312 // The first operand is a chain pointer. The second specifies address of the 313 // required CSR. Two results are produced, the read value and the new chain 314 // pointer. 315 READ_CSR, 316 // Write value to CSR. 317 // The first operand is a chain pointer, the second specifies address of the 318 // required CSR and the third is the value to write. The result is the new 319 // chain pointer. 320 WRITE_CSR, 321 // Read and write value of CSR. 322 // The first operand is a chain pointer, the second specifies address of the 323 // required CSR and the third is the value to write. Two results are produced, 324 // the value read before the modification and the new chain pointer. 325 SWAP_CSR, 326 327 // FP to 32 bit int conversions for RV64. These are used to keep track of the 328 // result being sign extended to 64 bit. These saturate out of range inputs. 329 STRICT_FCVT_W_RV64 = ISD::FIRST_TARGET_STRICTFP_OPCODE, 330 STRICT_FCVT_WU_RV64, 331 332 // WARNING: Do not add anything in the end unless you want the node to 333 // have memop! In fact, starting from FIRST_TARGET_MEMORY_OPCODE all 334 // opcodes will be thought as target memory ops! 335 336 // Load address. 337 LA = ISD::FIRST_TARGET_MEMORY_OPCODE, 338 LA_TLS_IE, 339 }; 340 } // namespace RISCVISD 341 342 namespace RISCV { 343 // We use 64 bits as the known part in the scalable vector types. 344 static constexpr unsigned RVVBitsPerBlock = 64; 345 } // namespace RISCV 346 347 class RISCVTargetLowering : public TargetLowering { 348 const RISCVSubtarget &Subtarget; 349 350 public: 351 explicit RISCVTargetLowering(const TargetMachine &TM, 352 const RISCVSubtarget &STI); 353 354 const RISCVSubtarget &getSubtarget() const { return Subtarget; } 355 356 bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I, 357 MachineFunction &MF, 358 unsigned Intrinsic) const override; 359 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, 360 unsigned AS, 361 Instruction *I = nullptr) const override; 362 bool isLegalICmpImmediate(int64_t Imm) const override; 363 bool isLegalAddImmediate(int64_t Imm) const override; 364 bool isTruncateFree(Type *SrcTy, Type *DstTy) const override; 365 bool isTruncateFree(EVT SrcVT, EVT DstVT) const override; 366 bool isZExtFree(SDValue Val, EVT VT2) const override; 367 bool isSExtCheaperThanZExt(EVT SrcVT, EVT DstVT) const override; 368 bool signExtendConstant(const ConstantInt *CI) const override; 369 bool isCheapToSpeculateCttz() const override; 370 bool isCheapToSpeculateCtlz() const override; 371 bool hasAndNotCompare(SDValue Y) const override; 372 bool hasBitTest(SDValue X, SDValue Y) const override; 373 bool shouldProduceAndByConstByHoistingConstFromShiftsLHSOfAnd( 374 SDValue X, ConstantSDNode *XC, ConstantSDNode *CC, SDValue Y, 375 unsigned OldShiftOpcode, unsigned NewShiftOpcode, 376 SelectionDAG &DAG) const override; 377 bool shouldSinkOperands(Instruction *I, 378 SmallVectorImpl<Use *> &Ops) const override; 379 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override; 380 bool isFPImmLegal(const APFloat &Imm, EVT VT, 381 bool ForCodeSize) const override; 382 383 bool softPromoteHalfType() const override { return true; } 384 385 /// Return the register type for a given MVT, ensuring vectors are treated 386 /// as a series of gpr sized integers. 387 MVT getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC, 388 EVT VT) const override; 389 390 /// Return the number of registers for a given MVT, ensuring vectors are 391 /// treated as a series of gpr sized integers. 392 unsigned getNumRegistersForCallingConv(LLVMContext &Context, 393 CallingConv::ID CC, 394 EVT VT) const override; 395 396 /// Return true if the given shuffle mask can be codegen'd directly, or if it 397 /// should be stack expanded. 398 bool isShuffleMaskLegal(ArrayRef<int> M, EVT VT) const override; 399 400 bool hasBitPreservingFPLogic(EVT VT) const override; 401 bool 402 shouldExpandBuildVectorWithShuffles(EVT VT, 403 unsigned DefinedValues) const override; 404 405 // Provide custom lowering hooks for some operations. 406 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override; 407 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results, 408 SelectionDAG &DAG) const override; 409 410 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override; 411 412 bool targetShrinkDemandedConstant(SDValue Op, const APInt &DemandedBits, 413 const APInt &DemandedElts, 414 TargetLoweringOpt &TLO) const override; 415 416 void computeKnownBitsForTargetNode(const SDValue Op, 417 KnownBits &Known, 418 const APInt &DemandedElts, 419 const SelectionDAG &DAG, 420 unsigned Depth) const override; 421 unsigned ComputeNumSignBitsForTargetNode(SDValue Op, 422 const APInt &DemandedElts, 423 const SelectionDAG &DAG, 424 unsigned Depth) const override; 425 426 const Constant *getTargetConstantFromLoad(LoadSDNode *LD) const override; 427 428 // This method returns the name of a target specific DAG node. 429 const char *getTargetNodeName(unsigned Opcode) const override; 430 431 ConstraintType getConstraintType(StringRef Constraint) const override; 432 433 unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override; 434 435 std::pair<unsigned, const TargetRegisterClass *> 436 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, 437 StringRef Constraint, MVT VT) const override; 438 439 void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, 440 std::vector<SDValue> &Ops, 441 SelectionDAG &DAG) const override; 442 443 MachineBasicBlock * 444 EmitInstrWithCustomInserter(MachineInstr &MI, 445 MachineBasicBlock *BB) const override; 446 447 void AdjustInstrPostInstrSelection(MachineInstr &MI, 448 SDNode *Node) const override; 449 450 EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, 451 EVT VT) const override; 452 453 bool convertSetCCLogicToBitwiseLogic(EVT VT) const override { 454 return VT.isScalarInteger(); 455 } 456 bool convertSelectOfConstantsToMath(EVT VT) const override { return true; } 457 458 bool shouldInsertFencesForAtomic(const Instruction *I) const override { 459 return isa<LoadInst>(I) || isa<StoreInst>(I); 460 } 461 Instruction *emitLeadingFence(IRBuilderBase &Builder, Instruction *Inst, 462 AtomicOrdering Ord) const override; 463 Instruction *emitTrailingFence(IRBuilderBase &Builder, Instruction *Inst, 464 AtomicOrdering Ord) const override; 465 466 bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF, 467 EVT VT) const override; 468 469 ISD::NodeType getExtendForAtomicOps() const override { 470 return ISD::SIGN_EXTEND; 471 } 472 473 ISD::NodeType getExtendForAtomicCmpSwapArg() const override { 474 return ISD::SIGN_EXTEND; 475 } 476 477 bool shouldExpandShift(SelectionDAG &DAG, SDNode *N) const override { 478 if (DAG.getMachineFunction().getFunction().hasMinSize()) 479 return false; 480 return true; 481 } 482 bool isDesirableToCommuteWithShift(const SDNode *N, 483 CombineLevel Level) const override; 484 485 /// If a physical register, this returns the register that receives the 486 /// exception address on entry to an EH pad. 487 Register 488 getExceptionPointerRegister(const Constant *PersonalityFn) const override; 489 490 /// If a physical register, this returns the register that receives the 491 /// exception typeid on entry to a landing pad. 492 Register 493 getExceptionSelectorRegister(const Constant *PersonalityFn) const override; 494 495 bool shouldExtendTypeInLibCall(EVT Type) const override; 496 bool shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const override; 497 498 /// Returns the register with the specified architectural or ABI name. This 499 /// method is necessary to lower the llvm.read_register.* and 500 /// llvm.write_register.* intrinsics. Allocatable registers must be reserved 501 /// with the clang -ffixed-xX flag for access to be allowed. 502 Register getRegisterByName(const char *RegName, LLT VT, 503 const MachineFunction &MF) const override; 504 505 // Lower incoming arguments, copy physregs into vregs 506 SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, 507 bool IsVarArg, 508 const SmallVectorImpl<ISD::InputArg> &Ins, 509 const SDLoc &DL, SelectionDAG &DAG, 510 SmallVectorImpl<SDValue> &InVals) const override; 511 bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, 512 bool IsVarArg, 513 const SmallVectorImpl<ISD::OutputArg> &Outs, 514 LLVMContext &Context) const override; 515 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, 516 const SmallVectorImpl<ISD::OutputArg> &Outs, 517 const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL, 518 SelectionDAG &DAG) const override; 519 SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI, 520 SmallVectorImpl<SDValue> &InVals) const override; 521 522 bool shouldConvertConstantLoadToIntImm(const APInt &Imm, 523 Type *Ty) const override; 524 bool mayBeEmittedAsTailCall(const CallInst *CI) const override; 525 bool shouldConsiderGEPOffsetSplit() const override { return true; } 526 527 bool decomposeMulByConstant(LLVMContext &Context, EVT VT, 528 SDValue C) const override; 529 530 bool isMulAddWithConstProfitable(SDValue AddNode, 531 SDValue ConstNode) const override; 532 533 TargetLowering::AtomicExpansionKind 534 shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override; 535 Value *emitMaskedAtomicRMWIntrinsic(IRBuilderBase &Builder, AtomicRMWInst *AI, 536 Value *AlignedAddr, Value *Incr, 537 Value *Mask, Value *ShiftAmt, 538 AtomicOrdering Ord) const override; 539 TargetLowering::AtomicExpansionKind 540 shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *CI) const override; 541 Value *emitMaskedAtomicCmpXchgIntrinsic(IRBuilderBase &Builder, 542 AtomicCmpXchgInst *CI, 543 Value *AlignedAddr, Value *CmpVal, 544 Value *NewVal, Value *Mask, 545 AtomicOrdering Ord) const override; 546 547 /// Returns true if the target allows unaligned memory accesses of the 548 /// specified type. 549 bool allowsMisalignedMemoryAccesses( 550 EVT VT, unsigned AddrSpace = 0, Align Alignment = Align(1), 551 MachineMemOperand::Flags Flags = MachineMemOperand::MONone, 552 bool *Fast = nullptr) const override; 553 554 bool splitValueIntoRegisterParts(SelectionDAG &DAG, const SDLoc &DL, 555 SDValue Val, SDValue *Parts, 556 unsigned NumParts, MVT PartVT, 557 Optional<CallingConv::ID> CC) const override; 558 559 SDValue 560 joinRegisterPartsIntoValue(SelectionDAG &DAG, const SDLoc &DL, 561 const SDValue *Parts, unsigned NumParts, 562 MVT PartVT, EVT ValueVT, 563 Optional<CallingConv::ID> CC) const override; 564 565 static RISCVII::VLMUL getLMUL(MVT VT); 566 inline static unsigned computeVLMAX(unsigned VectorBits, unsigned EltSize, 567 unsigned MinSize) { 568 // Original equation: 569 // VLMAX = (VectorBits / EltSize) * LMUL 570 // where LMUL = MinSize / RISCV::RVVBitsPerBlock 571 // The following equations have been reordered to prevent loss of precision 572 // when calculating fractional LMUL. 573 return ((VectorBits / EltSize) * MinSize) / RISCV::RVVBitsPerBlock; 574 }; 575 static unsigned getRegClassIDForLMUL(RISCVII::VLMUL LMul); 576 static unsigned getSubregIndexByMVT(MVT VT, unsigned Index); 577 static unsigned getRegClassIDForVecVT(MVT VT); 578 static std::pair<unsigned, unsigned> 579 decomposeSubvectorInsertExtractToSubRegs(MVT VecVT, MVT SubVecVT, 580 unsigned InsertExtractIdx, 581 const RISCVRegisterInfo *TRI); 582 MVT getContainerForFixedLengthVector(MVT VT) const; 583 584 bool shouldRemoveExtendFromGSIndex(EVT IndexVT, EVT DataVT) const override; 585 586 bool isLegalElementTypeForRVV(Type *ScalarTy) const; 587 588 bool shouldConvertFpToSat(unsigned Op, EVT FPVT, EVT VT) const override; 589 590 SDValue BuildSDIVPow2(SDNode *N, const APInt &Divisor, SelectionDAG &DAG, 591 SmallVectorImpl<SDNode *> &Created) const override; 592 593 unsigned getJumpTableEncoding() const override; 594 595 const MCExpr *LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI, 596 const MachineBasicBlock *MBB, 597 unsigned uid, 598 MCContext &Ctx) const override; 599 600 private: 601 /// RISCVCCAssignFn - This target-specific function extends the default 602 /// CCValAssign with additional information used to lower RISC-V calling 603 /// conventions. 604 typedef bool RISCVCCAssignFn(const DataLayout &DL, RISCVABI::ABI, 605 unsigned ValNo, MVT ValVT, MVT LocVT, 606 CCValAssign::LocInfo LocInfo, 607 ISD::ArgFlagsTy ArgFlags, CCState &State, 608 bool IsFixed, bool IsRet, Type *OrigTy, 609 const RISCVTargetLowering &TLI, 610 Optional<unsigned> FirstMaskArgument); 611 612 void analyzeInputArgs(MachineFunction &MF, CCState &CCInfo, 613 const SmallVectorImpl<ISD::InputArg> &Ins, bool IsRet, 614 RISCVCCAssignFn Fn) const; 615 void analyzeOutputArgs(MachineFunction &MF, CCState &CCInfo, 616 const SmallVectorImpl<ISD::OutputArg> &Outs, 617 bool IsRet, CallLoweringInfo *CLI, 618 RISCVCCAssignFn Fn) const; 619 620 template <class NodeTy> 621 SDValue getAddr(NodeTy *N, SelectionDAG &DAG, bool IsLocal = true) const; 622 SDValue getStaticTLSAddr(GlobalAddressSDNode *N, SelectionDAG &DAG, 623 bool UseGOT) const; 624 SDValue getDynamicTLSAddr(GlobalAddressSDNode *N, SelectionDAG &DAG) const; 625 626 SDValue lowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const; 627 SDValue lowerBlockAddress(SDValue Op, SelectionDAG &DAG) const; 628 SDValue lowerConstantPool(SDValue Op, SelectionDAG &DAG) const; 629 SDValue lowerJumpTable(SDValue Op, SelectionDAG &DAG) const; 630 SDValue lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const; 631 SDValue lowerSELECT(SDValue Op, SelectionDAG &DAG) const; 632 SDValue lowerBRCOND(SDValue Op, SelectionDAG &DAG) const; 633 SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const; 634 SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const; 635 SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const; 636 SDValue lowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const; 637 SDValue lowerShiftRightParts(SDValue Op, SelectionDAG &DAG, bool IsSRA) const; 638 SDValue lowerSPLAT_VECTOR_PARTS(SDValue Op, SelectionDAG &DAG) const; 639 SDValue lowerVectorMaskSplat(SDValue Op, SelectionDAG &DAG) const; 640 SDValue lowerVectorMaskExt(SDValue Op, SelectionDAG &DAG, 641 int64_t ExtTrueVal) const; 642 SDValue lowerVectorMaskTruncLike(SDValue Op, SelectionDAG &DAG) const; 643 SDValue lowerVectorTruncLike(SDValue Op, SelectionDAG &DAG) const; 644 SDValue lowerVectorFPExtendOrRoundLike(SDValue Op, SelectionDAG &DAG) const; 645 SDValue lowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const; 646 SDValue lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const; 647 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const; 648 SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const; 649 SDValue LowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const; 650 SDValue lowerVPREDUCE(SDValue Op, SelectionDAG &DAG) const; 651 SDValue lowerVECREDUCE(SDValue Op, SelectionDAG &DAG) const; 652 SDValue lowerVectorMaskVecReduction(SDValue Op, SelectionDAG &DAG, 653 bool IsVP) const; 654 SDValue lowerFPVECREDUCE(SDValue Op, SelectionDAG &DAG) const; 655 SDValue lowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const; 656 SDValue lowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const; 657 SDValue lowerSTEP_VECTOR(SDValue Op, SelectionDAG &DAG) const; 658 SDValue lowerVECTOR_REVERSE(SDValue Op, SelectionDAG &DAG) const; 659 SDValue lowerVECTOR_SPLICE(SDValue Op, SelectionDAG &DAG) const; 660 SDValue lowerABS(SDValue Op, SelectionDAG &DAG) const; 661 SDValue lowerMaskedLoad(SDValue Op, SelectionDAG &DAG) const; 662 SDValue lowerMaskedStore(SDValue Op, SelectionDAG &DAG) const; 663 SDValue lowerFixedLengthVectorFCOPYSIGNToRVV(SDValue Op, 664 SelectionDAG &DAG) const; 665 SDValue lowerMaskedGather(SDValue Op, SelectionDAG &DAG) const; 666 SDValue lowerMaskedScatter(SDValue Op, SelectionDAG &DAG) const; 667 SDValue lowerFixedLengthVectorLoadToRVV(SDValue Op, SelectionDAG &DAG) const; 668 SDValue lowerFixedLengthVectorStoreToRVV(SDValue Op, SelectionDAG &DAG) const; 669 SDValue lowerFixedLengthVectorSetccToRVV(SDValue Op, SelectionDAG &DAG) const; 670 SDValue lowerFixedLengthVectorLogicOpToRVV(SDValue Op, SelectionDAG &DAG, 671 unsigned MaskOpc, 672 unsigned VecOpc) const; 673 SDValue lowerFixedLengthVectorShiftToRVV(SDValue Op, SelectionDAG &DAG) const; 674 SDValue lowerFixedLengthVectorSelectToRVV(SDValue Op, 675 SelectionDAG &DAG) const; 676 SDValue lowerToScalableOp(SDValue Op, SelectionDAG &DAG, unsigned NewOpc, 677 bool HasMask = true) const; 678 SDValue lowerVPOp(SDValue Op, SelectionDAG &DAG, unsigned RISCVISDOpc) const; 679 SDValue lowerLogicVPOp(SDValue Op, SelectionDAG &DAG, unsigned MaskOpc, 680 unsigned VecOpc) const; 681 SDValue lowerVPExtMaskOp(SDValue Op, SelectionDAG &DAG) const; 682 SDValue lowerVPSetCCMaskOp(SDValue Op, SelectionDAG &DAG) const; 683 SDValue lowerVPFPIntConvOp(SDValue Op, SelectionDAG &DAG, 684 unsigned RISCVISDOpc) const; 685 SDValue lowerFixedLengthVectorExtendToRVV(SDValue Op, SelectionDAG &DAG, 686 unsigned ExtendOpc) const; 687 SDValue lowerGET_ROUNDING(SDValue Op, SelectionDAG &DAG) const; 688 SDValue lowerSET_ROUNDING(SDValue Op, SelectionDAG &DAG) const; 689 690 SDValue lowerEH_DWARF_CFA(SDValue Op, SelectionDAG &DAG) const; 691 692 SDValue expandUnalignedRVVLoad(SDValue Op, SelectionDAG &DAG) const; 693 SDValue expandUnalignedRVVStore(SDValue Op, SelectionDAG &DAG) const; 694 695 bool isEligibleForTailCallOptimization( 696 CCState &CCInfo, CallLoweringInfo &CLI, MachineFunction &MF, 697 const SmallVector<CCValAssign, 16> &ArgLocs) const; 698 699 /// Generate error diagnostics if any register used by CC has been marked 700 /// reserved. 701 void validateCCReservedRegs( 702 const SmallVectorImpl<std::pair<llvm::Register, llvm::SDValue>> &Regs, 703 MachineFunction &MF) const; 704 705 bool useRVVForFixedLengthVectorVT(MVT VT) const; 706 707 MVT getVPExplicitVectorLengthTy() const override; 708 709 /// RVV code generation for fixed length vectors does not lower all 710 /// BUILD_VECTORs. This makes BUILD_VECTOR legalisation a source of stores to 711 /// merge. However, merging them creates a BUILD_VECTOR that is just as 712 /// illegal as the original, thus leading to an infinite legalisation loop. 713 /// NOTE: Once BUILD_VECTOR can be custom lowered for all legal vector types, 714 /// this override can be removed. 715 bool mergeStoresAfterLegalization(EVT VT) const override; 716 717 /// Disable normalizing 718 /// select(N0&N1, X, Y) => select(N0, select(N1, X, Y), Y) and 719 /// select(N0|N1, X, Y) => select(N0, select(N1, X, Y, Y)) 720 /// RISCV doesn't have flags so it's better to perform the and/or in a GPR. 721 bool shouldNormalizeToSelectSequence(LLVMContext &, EVT) const override { 722 return false; 723 }; 724 }; 725 namespace RISCVVIntrinsicsTable { 726 727 struct RISCVVIntrinsicInfo { 728 unsigned IntrinsicID; 729 uint8_t ScalarOperand; 730 uint8_t VLOperand; 731 bool hasScalarOperand() const { 732 // 0xF is not valid. See NoScalarOperand in IntrinsicsRISCV.td. 733 return ScalarOperand != 0xF; 734 } 735 bool hasVLOperand() const { 736 // 0x1F is not valid. See NoVLOperand in IntrinsicsRISCV.td. 737 return VLOperand != 0x1F; 738 } 739 }; 740 741 using namespace RISCV; 742 743 #define GET_RISCVVIntrinsicsTable_DECL 744 #include "RISCVGenSearchableTables.inc" 745 746 } // end namespace RISCVVIntrinsicsTable 747 748 } // end namespace llvm 749 750 #endif 751