1 //===-- RISCVISelLowering.h - RISCV DAG Lowering Interface ------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file defines the interfaces that RISCV uses to lower LLVM code into a 10 // selection DAG. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #ifndef LLVM_LIB_TARGET_RISCV_RISCVISELLOWERING_H 15 #define LLVM_LIB_TARGET_RISCV_RISCVISELLOWERING_H 16 17 #include "RISCV.h" 18 #include "llvm/CodeGen/SelectionDAG.h" 19 #include "llvm/CodeGen/TargetLowering.h" 20 21 namespace llvm { 22 class RISCVSubtarget; 23 namespace RISCVISD { 24 enum NodeType : unsigned { 25 FIRST_NUMBER = ISD::BUILTIN_OP_END, 26 RET_FLAG, 27 URET_FLAG, 28 SRET_FLAG, 29 MRET_FLAG, 30 CALL, 31 SELECT_CC, 32 BuildPairF64, 33 SplitF64, 34 TAIL, 35 // RV64I shifts, directly matching the semantics of the named RISC-V 36 // instructions. 37 SLLW, 38 SRAW, 39 SRLW, 40 // 32-bit operations from RV64M that can't be simply matched with a pattern 41 // at instruction selection time. 42 DIVW, 43 DIVUW, 44 REMUW, 45 // FPR32<->GPR transfer operations for RV64. Needed as an i32<->f32 bitcast 46 // is not legal on RV64. FMV_W_X_RV64 matches the semantics of the FMV.W.X. 47 // FMV_X_ANYEXTW_RV64 is similar to FMV.X.W but has an any-extended result. 48 // This is a more convenient semantic for producing dagcombines that remove 49 // unnecessary GPR->FPR->GPR moves. 50 FMV_W_X_RV64, 51 FMV_X_ANYEXTW_RV64, 52 // READ_CYCLE_WIDE - A read of the 64-bit cycle CSR on a 32-bit target 53 // (returns (Lo, Hi)). It takes a chain operand. 54 READ_CYCLE_WIDE 55 }; 56 } 57 58 class RISCVTargetLowering : public TargetLowering { 59 const RISCVSubtarget &Subtarget; 60 61 public: 62 explicit RISCVTargetLowering(const TargetMachine &TM, 63 const RISCVSubtarget &STI); 64 65 bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I, 66 MachineFunction &MF, 67 unsigned Intrinsic) const override; 68 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, 69 unsigned AS, 70 Instruction *I = nullptr) const override; 71 bool isLegalICmpImmediate(int64_t Imm) const override; 72 bool isLegalAddImmediate(int64_t Imm) const override; 73 bool isTruncateFree(Type *SrcTy, Type *DstTy) const override; 74 bool isTruncateFree(EVT SrcVT, EVT DstVT) const override; 75 bool isZExtFree(SDValue Val, EVT VT2) const override; 76 bool isSExtCheaperThanZExt(EVT SrcVT, EVT DstVT) const override; 77 bool isFPImmLegal(const APFloat &Imm, EVT VT, 78 bool ForCodeSize) const override; 79 80 bool hasBitPreservingFPLogic(EVT VT) const override; 81 82 // Provide custom lowering hooks for some operations. 83 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override; 84 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results, 85 SelectionDAG &DAG) const override; 86 87 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override; 88 89 unsigned ComputeNumSignBitsForTargetNode(SDValue Op, 90 const APInt &DemandedElts, 91 const SelectionDAG &DAG, 92 unsigned Depth) const override; 93 94 // This method returns the name of a target specific DAG node. 95 const char *getTargetNodeName(unsigned Opcode) const override; 96 97 ConstraintType getConstraintType(StringRef Constraint) const override; 98 99 unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override; 100 101 std::pair<unsigned, const TargetRegisterClass *> 102 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, 103 StringRef Constraint, MVT VT) const override; 104 105 void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, 106 std::vector<SDValue> &Ops, 107 SelectionDAG &DAG) const override; 108 109 MachineBasicBlock * 110 EmitInstrWithCustomInserter(MachineInstr &MI, 111 MachineBasicBlock *BB) const override; 112 113 EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, 114 EVT VT) const override; 115 116 bool convertSetCCLogicToBitwiseLogic(EVT VT) const override { 117 return VT.isScalarInteger(); 118 } 119 120 bool shouldInsertFencesForAtomic(const Instruction *I) const override { 121 return isa<LoadInst>(I) || isa<StoreInst>(I); 122 } 123 Instruction *emitLeadingFence(IRBuilder<> &Builder, Instruction *Inst, 124 AtomicOrdering Ord) const override; 125 Instruction *emitTrailingFence(IRBuilder<> &Builder, Instruction *Inst, 126 AtomicOrdering Ord) const override; 127 128 ISD::NodeType getExtendForAtomicOps() const override { 129 return ISD::SIGN_EXTEND; 130 } 131 132 ISD::NodeType getExtendForAtomicCmpSwapArg() const override { 133 return ISD::SIGN_EXTEND; 134 } 135 136 bool shouldExpandShift(SelectionDAG &DAG, SDNode *N) const override { 137 if (DAG.getMachineFunction().getFunction().hasMinSize()) 138 return false; 139 return true; 140 } 141 bool isDesirableToCommuteWithShift(const SDNode *N, 142 CombineLevel Level) const override; 143 144 /// If a physical register, this returns the register that receives the 145 /// exception address on entry to an EH pad. 146 unsigned 147 getExceptionPointerRegister(const Constant *PersonalityFn) const override; 148 149 /// If a physical register, this returns the register that receives the 150 /// exception typeid on entry to a landing pad. 151 unsigned 152 getExceptionSelectorRegister(const Constant *PersonalityFn) const override; 153 154 bool shouldExtendTypeInLibCall(EVT Type) const override; 155 156 /// Returns the register with the specified architectural or ABI name. This 157 /// method is necessary to lower the llvm.read_register.* and 158 /// llvm.write_register.* intrinsics. Allocatable registers must be reserved 159 /// with the clang -ffixed-xX flag for access to be allowed. 160 Register getRegisterByName(const char *RegName, LLT VT, 161 const MachineFunction &MF) const override; 162 163 private: 164 void analyzeInputArgs(MachineFunction &MF, CCState &CCInfo, 165 const SmallVectorImpl<ISD::InputArg> &Ins, 166 bool IsRet) const; 167 void analyzeOutputArgs(MachineFunction &MF, CCState &CCInfo, 168 const SmallVectorImpl<ISD::OutputArg> &Outs, 169 bool IsRet, CallLoweringInfo *CLI) const; 170 // Lower incoming arguments, copy physregs into vregs 171 SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, 172 bool IsVarArg, 173 const SmallVectorImpl<ISD::InputArg> &Ins, 174 const SDLoc &DL, SelectionDAG &DAG, 175 SmallVectorImpl<SDValue> &InVals) const override; 176 bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, 177 bool IsVarArg, 178 const SmallVectorImpl<ISD::OutputArg> &Outs, 179 LLVMContext &Context) const override; 180 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, 181 const SmallVectorImpl<ISD::OutputArg> &Outs, 182 const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL, 183 SelectionDAG &DAG) const override; 184 SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI, 185 SmallVectorImpl<SDValue> &InVals) const override; 186 bool shouldConvertConstantLoadToIntImm(const APInt &Imm, 187 Type *Ty) const override { 188 return true; 189 } 190 bool mayBeEmittedAsTailCall(const CallInst *CI) const override; 191 192 template <class NodeTy> 193 SDValue getAddr(NodeTy *N, SelectionDAG &DAG, bool IsLocal = true) const; 194 195 SDValue getStaticTLSAddr(GlobalAddressSDNode *N, SelectionDAG &DAG, 196 bool UseGOT) const; 197 SDValue getDynamicTLSAddr(GlobalAddressSDNode *N, SelectionDAG &DAG) const; 198 199 bool shouldConsiderGEPOffsetSplit() const override { return true; } 200 SDValue lowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const; 201 SDValue lowerBlockAddress(SDValue Op, SelectionDAG &DAG) const; 202 SDValue lowerConstantPool(SDValue Op, SelectionDAG &DAG) const; 203 SDValue lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const; 204 SDValue lowerSELECT(SDValue Op, SelectionDAG &DAG) const; 205 SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const; 206 SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const; 207 SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const; 208 SDValue lowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const; 209 SDValue lowerShiftRightParts(SDValue Op, SelectionDAG &DAG, bool IsSRA) const; 210 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const; 211 212 bool isEligibleForTailCallOptimization( 213 CCState &CCInfo, CallLoweringInfo &CLI, MachineFunction &MF, 214 const SmallVector<CCValAssign, 16> &ArgLocs) const; 215 216 TargetLowering::AtomicExpansionKind 217 shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override; 218 virtual Value *emitMaskedAtomicRMWIntrinsic( 219 IRBuilder<> &Builder, AtomicRMWInst *AI, Value *AlignedAddr, Value *Incr, 220 Value *Mask, Value *ShiftAmt, AtomicOrdering Ord) const override; 221 TargetLowering::AtomicExpansionKind 222 shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *CI) const override; 223 virtual Value * 224 emitMaskedAtomicCmpXchgIntrinsic(IRBuilder<> &Builder, AtomicCmpXchgInst *CI, 225 Value *AlignedAddr, Value *CmpVal, 226 Value *NewVal, Value *Mask, 227 AtomicOrdering Ord) const override; 228 229 /// Generate error diagnostics if any register used by CC has been marked 230 /// reserved. 231 void validateCCReservedRegs( 232 const SmallVectorImpl<std::pair<llvm::Register, llvm::SDValue>> &Regs, 233 MachineFunction &MF) const; 234 }; 235 } 236 237 #endif 238