1 //===-- RISCVISelLowering.h - RISCV DAG Lowering Interface ------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file defines the interfaces that RISCV uses to lower LLVM code into a 10 // selection DAG. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #ifndef LLVM_LIB_TARGET_RISCV_RISCVISELLOWERING_H 15 #define LLVM_LIB_TARGET_RISCV_RISCVISELLOWERING_H 16 17 #include "RISCV.h" 18 #include "llvm/CodeGen/SelectionDAG.h" 19 #include "llvm/CodeGen/TargetLowering.h" 20 21 namespace llvm { 22 class RISCVSubtarget; 23 struct RISCVRegisterInfo; 24 namespace RISCVISD { 25 enum NodeType : unsigned { 26 FIRST_NUMBER = ISD::BUILTIN_OP_END, 27 RET_FLAG, 28 URET_FLAG, 29 SRET_FLAG, 30 MRET_FLAG, 31 CALL, 32 /// Select with condition operator - This selects between a true value and 33 /// a false value (ops #3 and #4) based on the boolean result of comparing 34 /// the lhs and rhs (ops #0 and #1) of a conditional expression with the 35 /// condition code in op #2, a XLenVT constant from the ISD::CondCode enum. 36 /// The lhs and rhs are XLenVT integers. The true and false values can be 37 /// integer or floating point. 38 SELECT_CC, 39 BR_CC, 40 BuildPairF64, 41 SplitF64, 42 TAIL, 43 // Multiply high for signedxunsigned. 44 MULHSU, 45 // RV64I shifts, directly matching the semantics of the named RISC-V 46 // instructions. 47 SLLW, 48 SRAW, 49 SRLW, 50 // 32-bit operations from RV64M that can't be simply matched with a pattern 51 // at instruction selection time. These have undefined behavior for division 52 // by 0 or overflow (divw) like their target independent counterparts. 53 DIVW, 54 DIVUW, 55 REMUW, 56 // RV64IB rotates, directly matching the semantics of the named RISC-V 57 // instructions. 58 ROLW, 59 RORW, 60 // RV64IZbb bit counting instructions directly matching the semantics of the 61 // named RISC-V instructions. 62 CLZW, 63 CTZW, 64 // RV64IB/RV32IB funnel shifts, with the semantics of the named RISC-V 65 // instructions, but the same operand order as fshl/fshr intrinsics. 66 FSR, 67 FSL, 68 // RV64IB funnel shifts, with the semantics of the named RISC-V instructions, 69 // but the same operand order as fshl/fshr intrinsics. 70 FSRW, 71 FSLW, 72 // FPR<->GPR transfer operations when the FPR is smaller than XLEN, needed as 73 // XLEN is the only legal integer width. 74 // 75 // FMV_H_X matches the semantics of the FMV.H.X. 76 // FMV_X_ANYEXTH is similar to FMV.X.H but has an any-extended result. 77 // FMV_W_X_RV64 matches the semantics of the FMV.W.X. 78 // FMV_X_ANYEXTW_RV64 is similar to FMV.X.W but has an any-extended result. 79 // 80 // This is a more convenient semantic for producing dagcombines that remove 81 // unnecessary GPR->FPR->GPR moves. 82 FMV_H_X, 83 FMV_X_ANYEXTH, 84 FMV_W_X_RV64, 85 FMV_X_ANYEXTW_RV64, 86 // READ_CYCLE_WIDE - A read of the 64-bit cycle CSR on a 32-bit target 87 // (returns (Lo, Hi)). It takes a chain operand. 88 READ_CYCLE_WIDE, 89 // Generalized Reverse and Generalized Or-Combine - directly matching the 90 // semantics of the named RISC-V instructions. Lowered as custom nodes as 91 // TableGen chokes when faced with commutative permutations in deeply-nested 92 // DAGs. Each node takes an input operand and a control operand and outputs a 93 // bit-manipulated version of input. All operands are i32 or XLenVT. 94 GREV, 95 GREVW, 96 GORC, 97 GORCW, 98 SHFL, 99 // Vector Extension 100 // VMV_V_X_VL matches the semantics of vmv.v.x but includes an extra operand 101 // for the VL value to be used for the operation. 102 VMV_V_X_VL, 103 // VFMV_V_F_VL matches the semantics of vfmv.v.f but includes an extra operand 104 // for the VL value to be used for the operation. 105 VFMV_V_F_VL, 106 // VMV_X_S matches the semantics of vmv.x.s. The result is always XLenVT sign 107 // extended from the vector element size. 108 VMV_X_S, 109 // VMV_S_X_VL matches the semantics of vmv.s.x. It carries a VL operand. 110 VMV_S_X_VL, 111 // VFMV_S_F_VL matches the semantics of vfmv.s.f. It carries a VL operand. 112 VFMV_S_F_VL, 113 // Splats an i64 scalar to a vector type (with element type i64) where the 114 // scalar is a sign-extended i32. 115 SPLAT_VECTOR_I64, 116 // Read VLENB CSR 117 READ_VLENB, 118 // Truncates a RVV integer vector by one power-of-two. Carries both an extra 119 // mask and VL operand. 120 TRUNCATE_VECTOR_VL, 121 // Unit-stride fault-only-first load 122 VLEFF, 123 VLEFF_MASK, 124 // Matches the semantics of vslideup/vslidedown. The first operand is the 125 // pass-thru operand, the second is the source vector, the third is the 126 // XLenVT index (either constant or non-constant), the fourth is the mask 127 // and the fifth the VL. 128 VSLIDEUP_VL, 129 VSLIDEDOWN_VL, 130 // Matches the semantics of vslide1up/slide1down. The first operand is the 131 // source vector, the second is the XLenVT scalar value. The third and fourth 132 // operands are the mask and VL operands. 133 VSLIDE1UP_VL, 134 VSLIDE1DOWN_VL, 135 // Matches the semantics of the vid.v instruction, with a mask and VL 136 // operand. 137 VID_VL, 138 // Matches the semantics of the vfcnvt.rod function (Convert double-width 139 // float to single-width float, rounding towards odd). Takes a double-width 140 // float vector and produces a single-width float vector. Also has a mask and 141 // VL operand. 142 VFNCVT_ROD_VL, 143 // These nodes match the semantics of the corresponding RVV vector reduction 144 // instructions. They produce a vector result which is the reduction 145 // performed over the first vector operand plus the first element of the 146 // second vector operand. The first operand is an unconstrained vector type, 147 // and the result and second operand's types are expected to be the 148 // corresponding full-width LMUL=1 type for the first operand: 149 // nxv8i8 = vecreduce_add nxv32i8, nxv8i8 150 // nxv2i32 = vecreduce_add nxv8i32, nxv2i32 151 // The different in types does introduce extra vsetvli instructions but 152 // similarly it reduces the number of registers consumed per reduction. 153 // Also has a mask and VL operand. 154 VECREDUCE_ADD_VL, 155 VECREDUCE_UMAX_VL, 156 VECREDUCE_SMAX_VL, 157 VECREDUCE_UMIN_VL, 158 VECREDUCE_SMIN_VL, 159 VECREDUCE_AND_VL, 160 VECREDUCE_OR_VL, 161 VECREDUCE_XOR_VL, 162 VECREDUCE_FADD_VL, 163 VECREDUCE_SEQ_FADD_VL, 164 165 // Vector binary and unary ops with a mask as a third operand, and VL as a 166 // fourth operand. 167 // FIXME: Can we replace these with ISD::VP_*? 168 ADD_VL, 169 AND_VL, 170 MUL_VL, 171 OR_VL, 172 SDIV_VL, 173 SHL_VL, 174 SREM_VL, 175 SRA_VL, 176 SRL_VL, 177 SUB_VL, 178 UDIV_VL, 179 UREM_VL, 180 XOR_VL, 181 FADD_VL, 182 FSUB_VL, 183 FMUL_VL, 184 FDIV_VL, 185 FNEG_VL, 186 FABS_VL, 187 FSQRT_VL, 188 FMA_VL, 189 FCOPYSIGN_VL, 190 SMIN_VL, 191 SMAX_VL, 192 UMIN_VL, 193 UMAX_VL, 194 MULHS_VL, 195 MULHU_VL, 196 FP_TO_SINT_VL, 197 FP_TO_UINT_VL, 198 SINT_TO_FP_VL, 199 UINT_TO_FP_VL, 200 FP_ROUND_VL, 201 FP_EXTEND_VL, 202 203 // Vector compare producing a mask. Fourth operand is input mask. Fifth 204 // operand is VL. 205 SETCC_VL, 206 207 // Vector select with an additional VL operand. This operation is unmasked. 208 VSELECT_VL, 209 210 // Mask binary operators. 211 VMAND_VL, 212 VMOR_VL, 213 VMXOR_VL, 214 215 // Set mask vector to all zeros or ones. 216 VMCLR_VL, 217 VMSET_VL, 218 219 // Matches the semantics of vrgather.vx and vrgather.vv with an extra operand 220 // for VL. 221 VRGATHER_VX_VL, 222 VRGATHER_VV_VL, 223 VRGATHEREI16_VV_VL, 224 225 // Vector sign/zero extend with additional mask & VL operands. 226 VSEXT_VL, 227 VZEXT_VL, 228 // vpopc.m with additional mask and VL operands. 229 VPOPC_VL, 230 231 // Reads value of CSR. 232 // The first operand is a chain pointer. The second specifies address of the 233 // required CSR. Two results are produced, the read value and the new chain 234 // pointer. 235 READ_CSR, 236 // Write value to CSR. 237 // The first operand is a chain pointer, the second specifies address of the 238 // required CSR and the third is the value to write. The result is the new 239 // chain pointer. 240 WRITE_CSR, 241 // Read and write value of CSR. 242 // The first operand is a chain pointer, the second specifies address of the 243 // required CSR and the third is the value to write. Two results are produced, 244 // the value read before the modification and the new chain pointer. 245 SWAP_CSR, 246 247 // Memory opcodes start here. 248 VLE_VL = ISD::FIRST_TARGET_MEMORY_OPCODE, 249 VSE_VL, 250 251 // WARNING: Do not add anything in the end unless you want the node to 252 // have memop! In fact, starting from FIRST_TARGET_MEMORY_OPCODE all 253 // opcodes will be thought as target memory ops! 254 }; 255 } // namespace RISCVISD 256 257 class RISCVTargetLowering : public TargetLowering { 258 const RISCVSubtarget &Subtarget; 259 260 public: 261 explicit RISCVTargetLowering(const TargetMachine &TM, 262 const RISCVSubtarget &STI); 263 264 const RISCVSubtarget &getSubtarget() const { return Subtarget; } 265 266 bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I, 267 MachineFunction &MF, 268 unsigned Intrinsic) const override; 269 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, 270 unsigned AS, 271 Instruction *I = nullptr) const override; 272 bool isLegalICmpImmediate(int64_t Imm) const override; 273 bool isLegalAddImmediate(int64_t Imm) const override; 274 bool isTruncateFree(Type *SrcTy, Type *DstTy) const override; 275 bool isTruncateFree(EVT SrcVT, EVT DstVT) const override; 276 bool isZExtFree(SDValue Val, EVT VT2) const override; 277 bool isSExtCheaperThanZExt(EVT SrcVT, EVT DstVT) const override; 278 bool isCheapToSpeculateCttz() const override; 279 bool isCheapToSpeculateCtlz() const override; 280 bool isFPImmLegal(const APFloat &Imm, EVT VT, 281 bool ForCodeSize) const override; 282 283 bool softPromoteHalfType() const override { return true; } 284 285 /// Return the register type for a given MVT, ensuring vectors are treated 286 /// as a series of gpr sized integers. 287 MVT getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC, 288 EVT VT) const override; 289 290 /// Return the number of registers for a given MVT, ensuring vectors are 291 /// treated as a series of gpr sized integers. 292 unsigned getNumRegistersForCallingConv(LLVMContext &Context, 293 CallingConv::ID CC, 294 EVT VT) const override; 295 296 /// Return true if the given shuffle mask can be codegen'd directly, or if it 297 /// should be stack expanded. 298 bool isShuffleMaskLegal(ArrayRef<int> M, EVT VT) const override; 299 300 bool hasBitPreservingFPLogic(EVT VT) const override; 301 bool 302 shouldExpandBuildVectorWithShuffles(EVT VT, 303 unsigned DefinedValues) const override; 304 305 // Provide custom lowering hooks for some operations. 306 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override; 307 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results, 308 SelectionDAG &DAG) const override; 309 310 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override; 311 312 bool targetShrinkDemandedConstant(SDValue Op, const APInt &DemandedBits, 313 const APInt &DemandedElts, 314 TargetLoweringOpt &TLO) const override; 315 316 void computeKnownBitsForTargetNode(const SDValue Op, 317 KnownBits &Known, 318 const APInt &DemandedElts, 319 const SelectionDAG &DAG, 320 unsigned Depth) const override; 321 unsigned ComputeNumSignBitsForTargetNode(SDValue Op, 322 const APInt &DemandedElts, 323 const SelectionDAG &DAG, 324 unsigned Depth) const override; 325 326 // This method returns the name of a target specific DAG node. 327 const char *getTargetNodeName(unsigned Opcode) const override; 328 329 ConstraintType getConstraintType(StringRef Constraint) const override; 330 331 unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override; 332 333 std::pair<unsigned, const TargetRegisterClass *> 334 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, 335 StringRef Constraint, MVT VT) const override; 336 337 void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, 338 std::vector<SDValue> &Ops, 339 SelectionDAG &DAG) const override; 340 341 MachineBasicBlock * 342 EmitInstrWithCustomInserter(MachineInstr &MI, 343 MachineBasicBlock *BB) const override; 344 345 EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, 346 EVT VT) const override; 347 348 bool convertSetCCLogicToBitwiseLogic(EVT VT) const override { 349 return VT.isScalarInteger(); 350 } 351 bool convertSelectOfConstantsToMath(EVT VT) const override { return true; } 352 353 bool shouldInsertFencesForAtomic(const Instruction *I) const override { 354 return isa<LoadInst>(I) || isa<StoreInst>(I); 355 } 356 Instruction *emitLeadingFence(IRBuilder<> &Builder, Instruction *Inst, 357 AtomicOrdering Ord) const override; 358 Instruction *emitTrailingFence(IRBuilder<> &Builder, Instruction *Inst, 359 AtomicOrdering Ord) const override; 360 361 bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF, 362 EVT VT) const override; 363 364 ISD::NodeType getExtendForAtomicOps() const override { 365 return ISD::SIGN_EXTEND; 366 } 367 368 ISD::NodeType getExtendForAtomicCmpSwapArg() const override { 369 return ISD::SIGN_EXTEND; 370 } 371 372 bool shouldExpandShift(SelectionDAG &DAG, SDNode *N) const override { 373 if (DAG.getMachineFunction().getFunction().hasMinSize()) 374 return false; 375 return true; 376 } 377 bool isDesirableToCommuteWithShift(const SDNode *N, 378 CombineLevel Level) const override; 379 380 /// If a physical register, this returns the register that receives the 381 /// exception address on entry to an EH pad. 382 Register 383 getExceptionPointerRegister(const Constant *PersonalityFn) const override; 384 385 /// If a physical register, this returns the register that receives the 386 /// exception typeid on entry to a landing pad. 387 Register 388 getExceptionSelectorRegister(const Constant *PersonalityFn) const override; 389 390 bool shouldExtendTypeInLibCall(EVT Type) const override; 391 bool shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const override; 392 393 /// Returns the register with the specified architectural or ABI name. This 394 /// method is necessary to lower the llvm.read_register.* and 395 /// llvm.write_register.* intrinsics. Allocatable registers must be reserved 396 /// with the clang -ffixed-xX flag for access to be allowed. 397 Register getRegisterByName(const char *RegName, LLT VT, 398 const MachineFunction &MF) const override; 399 400 // Lower incoming arguments, copy physregs into vregs 401 SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, 402 bool IsVarArg, 403 const SmallVectorImpl<ISD::InputArg> &Ins, 404 const SDLoc &DL, SelectionDAG &DAG, 405 SmallVectorImpl<SDValue> &InVals) const override; 406 bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, 407 bool IsVarArg, 408 const SmallVectorImpl<ISD::OutputArg> &Outs, 409 LLVMContext &Context) const override; 410 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, 411 const SmallVectorImpl<ISD::OutputArg> &Outs, 412 const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL, 413 SelectionDAG &DAG) const override; 414 SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI, 415 SmallVectorImpl<SDValue> &InVals) const override; 416 417 bool shouldConvertConstantLoadToIntImm(const APInt &Imm, 418 Type *Ty) const override { 419 return true; 420 } 421 bool mayBeEmittedAsTailCall(const CallInst *CI) const override; 422 bool shouldConsiderGEPOffsetSplit() const override { return true; } 423 424 bool decomposeMulByConstant(LLVMContext &Context, EVT VT, 425 SDValue C) const override; 426 427 TargetLowering::AtomicExpansionKind 428 shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override; 429 Value *emitMaskedAtomicRMWIntrinsic(IRBuilder<> &Builder, AtomicRMWInst *AI, 430 Value *AlignedAddr, Value *Incr, 431 Value *Mask, Value *ShiftAmt, 432 AtomicOrdering Ord) const override; 433 TargetLowering::AtomicExpansionKind 434 shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *CI) const override; 435 Value *emitMaskedAtomicCmpXchgIntrinsic(IRBuilder<> &Builder, 436 AtomicCmpXchgInst *CI, 437 Value *AlignedAddr, Value *CmpVal, 438 Value *NewVal, Value *Mask, 439 AtomicOrdering Ord) const override; 440 441 /// Returns true if the target allows unaligned memory accesses of the 442 /// specified type. 443 bool allowsMisalignedMemoryAccesses( 444 EVT VT, unsigned AddrSpace = 0, Align Alignment = Align(1), 445 MachineMemOperand::Flags Flags = MachineMemOperand::MONone, 446 bool *Fast = nullptr) const override; 447 448 bool splitValueIntoRegisterParts(SelectionDAG &DAG, const SDLoc &DL, 449 SDValue Val, SDValue *Parts, 450 unsigned NumParts, MVT PartVT, 451 Optional<CallingConv::ID> CC) const override; 452 453 SDValue 454 joinRegisterPartsIntoValue(SelectionDAG &DAG, const SDLoc &DL, 455 const SDValue *Parts, unsigned NumParts, 456 MVT PartVT, EVT ValueVT, 457 Optional<CallingConv::ID> CC) const override; 458 459 static RISCVVLMUL getLMUL(MVT VT); 460 static unsigned getRegClassIDForLMUL(RISCVVLMUL LMul); 461 static unsigned getSubregIndexByMVT(MVT VT, unsigned Index); 462 static unsigned getRegClassIDForVecVT(MVT VT); 463 static std::pair<unsigned, unsigned> 464 decomposeSubvectorInsertExtractToSubRegs(MVT VecVT, MVT SubVecVT, 465 unsigned InsertExtractIdx, 466 const RISCVRegisterInfo *TRI); 467 MVT getContainerForFixedLengthVector(MVT VT) const; 468 static MVT getContainerForFixedLengthVector(const TargetLowering &TLI, MVT VT, 469 const RISCVSubtarget &Subtarget); 470 static MVT getContainerForFixedLengthVector(SelectionDAG &DAG, MVT VT, 471 const RISCVSubtarget &Subtarget); 472 473 bool shouldRemoveExtendFromGSIndex(EVT VT) const override; 474 475 private: 476 void analyzeInputArgs(MachineFunction &MF, CCState &CCInfo, 477 const SmallVectorImpl<ISD::InputArg> &Ins, 478 bool IsRet) const; 479 void analyzeOutputArgs(MachineFunction &MF, CCState &CCInfo, 480 const SmallVectorImpl<ISD::OutputArg> &Outs, 481 bool IsRet, CallLoweringInfo *CLI) const; 482 483 template <class NodeTy> 484 SDValue getAddr(NodeTy *N, SelectionDAG &DAG, bool IsLocal = true) const; 485 486 SDValue getStaticTLSAddr(GlobalAddressSDNode *N, SelectionDAG &DAG, 487 bool UseGOT) const; 488 SDValue getDynamicTLSAddr(GlobalAddressSDNode *N, SelectionDAG &DAG) const; 489 490 SDValue lowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const; 491 SDValue lowerBlockAddress(SDValue Op, SelectionDAG &DAG) const; 492 SDValue lowerConstantPool(SDValue Op, SelectionDAG &DAG) const; 493 SDValue lowerJumpTable(SDValue Op, SelectionDAG &DAG) const; 494 SDValue lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const; 495 SDValue lowerSELECT(SDValue Op, SelectionDAG &DAG) const; 496 SDValue lowerBRCOND(SDValue Op, SelectionDAG &DAG) const; 497 SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const; 498 SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const; 499 SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const; 500 SDValue lowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const; 501 SDValue lowerShiftRightParts(SDValue Op, SelectionDAG &DAG, bool IsSRA) const; 502 SDValue lowerSPLAT_VECTOR_PARTS(SDValue Op, SelectionDAG &DAG) const; 503 SDValue lowerVectorMaskExt(SDValue Op, SelectionDAG &DAG, 504 int64_t ExtTrueVal) const; 505 SDValue lowerVectorMaskTrunc(SDValue Op, SelectionDAG &DAG) const; 506 SDValue lowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const; 507 SDValue lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const; 508 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const; 509 SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const; 510 SDValue lowerVECREDUCE(SDValue Op, SelectionDAG &DAG) const; 511 SDValue lowerVectorMaskVECREDUCE(SDValue Op, SelectionDAG &DAG) const; 512 SDValue lowerFPVECREDUCE(SDValue Op, SelectionDAG &DAG) const; 513 SDValue lowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const; 514 SDValue lowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const; 515 SDValue lowerSTEP_VECTOR(SDValue Op, SelectionDAG &DAG) const; 516 SDValue lowerVECTOR_REVERSE(SDValue Op, SelectionDAG &DAG) const; 517 SDValue lowerABS(SDValue Op, SelectionDAG &DAG) const; 518 SDValue lowerMLOAD(SDValue Op, SelectionDAG &DAG) const; 519 SDValue lowerMSTORE(SDValue Op, SelectionDAG &DAG) const; 520 SDValue lowerFixedLengthVectorFCOPYSIGNToRVV(SDValue Op, 521 SelectionDAG &DAG) const; 522 SDValue lowerMGATHER(SDValue Op, SelectionDAG &DAG) const; 523 SDValue lowerMSCATTER(SDValue Op, SelectionDAG &DAG) const; 524 SDValue lowerFixedLengthVectorLoadToRVV(SDValue Op, SelectionDAG &DAG) const; 525 SDValue lowerFixedLengthVectorStoreToRVV(SDValue Op, SelectionDAG &DAG) const; 526 SDValue lowerFixedLengthVectorSetccToRVV(SDValue Op, SelectionDAG &DAG) const; 527 SDValue lowerFixedLengthVectorLogicOpToRVV(SDValue Op, SelectionDAG &DAG, 528 unsigned MaskOpc, 529 unsigned VecOpc) const; 530 SDValue lowerFixedLengthVectorSelectToRVV(SDValue Op, 531 SelectionDAG &DAG) const; 532 SDValue lowerToScalableOp(SDValue Op, SelectionDAG &DAG, unsigned NewOpc, 533 bool HasMask = true) const; 534 SDValue lowerFixedLengthVectorExtendToRVV(SDValue Op, SelectionDAG &DAG, 535 unsigned ExtendOpc) const; 536 537 bool isEligibleForTailCallOptimization( 538 CCState &CCInfo, CallLoweringInfo &CLI, MachineFunction &MF, 539 const SmallVector<CCValAssign, 16> &ArgLocs) const; 540 541 /// Generate error diagnostics if any register used by CC has been marked 542 /// reserved. 543 void validateCCReservedRegs( 544 const SmallVectorImpl<std::pair<llvm::Register, llvm::SDValue>> &Regs, 545 MachineFunction &MF) const; 546 547 bool useRVVForFixedLengthVectorVT(MVT VT) const; 548 }; 549 550 namespace RISCV { 551 // We use 64 bits as the known part in the scalable vector types. 552 static constexpr unsigned RVVBitsPerBlock = 64; 553 } // namespace RISCV 554 555 namespace RISCVVIntrinsicsTable { 556 557 struct RISCVVIntrinsicInfo { 558 unsigned IntrinsicID; 559 uint8_t SplatOperand; 560 }; 561 562 using namespace RISCV; 563 564 #define GET_RISCVVIntrinsicsTable_DECL 565 #include "RISCVGenSearchableTables.inc" 566 567 } // end namespace RISCVVIntrinsicsTable 568 569 } // end namespace llvm 570 571 #endif 572