1 //===-- RISCVISelLowering.h - RISCV DAG Lowering Interface ------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file defines the interfaces that RISCV uses to lower LLVM code into a 10 // selection DAG. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #ifndef LLVM_LIB_TARGET_RISCV_RISCVISELLOWERING_H 15 #define LLVM_LIB_TARGET_RISCV_RISCVISELLOWERING_H 16 17 #include "RISCV.h" 18 #include "llvm/CodeGen/SelectionDAG.h" 19 #include "llvm/CodeGen/TargetLowering.h" 20 21 namespace llvm { 22 class RISCVSubtarget; 23 struct RISCVRegisterInfo; 24 namespace RISCVISD { 25 enum NodeType : unsigned { 26 FIRST_NUMBER = ISD::BUILTIN_OP_END, 27 RET_FLAG, 28 URET_FLAG, 29 SRET_FLAG, 30 MRET_FLAG, 31 CALL, 32 /// Select with condition operator - This selects between a true value and 33 /// a false value (ops #3 and #4) based on the boolean result of comparing 34 /// the lhs and rhs (ops #0 and #1) of a conditional expression with the 35 /// condition code in op #2, a XLenVT constant from the ISD::CondCode enum. 36 /// The lhs and rhs are XLenVT integers. The true and false values can be 37 /// integer or floating point. 38 SELECT_CC, 39 BR_CC, 40 BuildPairF64, 41 SplitF64, 42 TAIL, 43 // Multiply high for signedxunsigned. 44 MULHSU, 45 // RV64I shifts, directly matching the semantics of the named RISC-V 46 // instructions. 47 SLLW, 48 SRAW, 49 SRLW, 50 // 32-bit operations from RV64M that can't be simply matched with a pattern 51 // at instruction selection time. These have undefined behavior for division 52 // by 0 or overflow (divw) like their target independent counterparts. 53 DIVW, 54 DIVUW, 55 REMUW, 56 // RV64IB rotates, directly matching the semantics of the named RISC-V 57 // instructions. 58 ROLW, 59 RORW, 60 // RV64IZbb bit counting instructions directly matching the semantics of the 61 // named RISC-V instructions. 62 CLZW, 63 CTZW, 64 // RV64IB/RV32IB funnel shifts, with the semantics of the named RISC-V 65 // instructions, but the same operand order as fshl/fshr intrinsics. 66 FSR, 67 FSL, 68 // RV64IB funnel shifts, with the semantics of the named RISC-V instructions, 69 // but the same operand order as fshl/fshr intrinsics. 70 FSRW, 71 FSLW, 72 // FPR<->GPR transfer operations when the FPR is smaller than XLEN, needed as 73 // XLEN is the only legal integer width. 74 // 75 // FMV_H_X matches the semantics of the FMV.H.X. 76 // FMV_X_ANYEXTH is similar to FMV.X.H but has an any-extended result. 77 // FMV_W_X_RV64 matches the semantics of the FMV.W.X. 78 // FMV_X_ANYEXTW_RV64 is similar to FMV.X.W but has an any-extended result. 79 // 80 // This is a more convenient semantic for producing dagcombines that remove 81 // unnecessary GPR->FPR->GPR moves. 82 FMV_H_X, 83 FMV_X_ANYEXTH, 84 FMV_W_X_RV64, 85 FMV_X_ANYEXTW_RV64, 86 // READ_CYCLE_WIDE - A read of the 64-bit cycle CSR on a 32-bit target 87 // (returns (Lo, Hi)). It takes a chain operand. 88 READ_CYCLE_WIDE, 89 // Generalized Reverse and Generalized Or-Combine - directly matching the 90 // semantics of the named RISC-V instructions. Lowered as custom nodes as 91 // TableGen chokes when faced with commutative permutations in deeply-nested 92 // DAGs. Each node takes an input operand and a TargetConstant immediate 93 // shift amount, and outputs a bit-manipulated version of input. All operands 94 // are of type XLenVT. 95 GREVI, 96 GREVIW, 97 GORCI, 98 GORCIW, 99 SHFLI, 100 // Vector Extension 101 // VMV_V_X_VL matches the semantics of vmv.v.x but includes an extra operand 102 // for the VL value to be used for the operation. 103 VMV_V_X_VL, 104 // VFMV_V_F_VL matches the semantics of vfmv.v.f but includes an extra operand 105 // for the VL value to be used for the operation. 106 VFMV_V_F_VL, 107 // VMV_X_S matches the semantics of vmv.x.s. The result is always XLenVT sign 108 // extended from the vector element size. 109 VMV_X_S, 110 // VMV_S_X_VL matches the semantics of vmv.s.x. It carries a VL operand. 111 VMV_S_X_VL, 112 // VFMV_S_F_VL matches the semantics of vfmv.s.f. It carries a VL operand. 113 VFMV_S_F_VL, 114 // Splats an i64 scalar to a vector type (with element type i64) where the 115 // scalar is a sign-extended i32. 116 SPLAT_VECTOR_I64, 117 // Read VLENB CSR 118 READ_VLENB, 119 // Truncates a RVV integer vector by one power-of-two. Carries both an extra 120 // mask and VL operand. 121 TRUNCATE_VECTOR_VL, 122 // Unit-stride fault-only-first load 123 VLEFF, 124 VLEFF_MASK, 125 // Matches the semantics of vslideup/vslidedown. The first operand is the 126 // pass-thru operand, the second is the source vector, the third is the 127 // XLenVT index (either constant or non-constant), the fourth is the mask 128 // and the fifth the VL. 129 VSLIDEUP_VL, 130 VSLIDEDOWN_VL, 131 // Matches the semantics of vslide1up/slide1down. The first operand is the 132 // source vector, the second is the XLenVT scalar value. The third and fourth 133 // operands are the mask and VL operands. 134 VSLIDE1UP_VL, 135 VSLIDE1DOWN_VL, 136 // Matches the semantics of the vid.v instruction, with a mask and VL 137 // operand. 138 VID_VL, 139 // Matches the semantics of the vfcnvt.rod function (Convert double-width 140 // float to single-width float, rounding towards odd). Takes a double-width 141 // float vector and produces a single-width float vector. Also has a mask and 142 // VL operand. 143 VFNCVT_ROD_VL, 144 // These nodes match the semantics of the corresponding RVV vector reduction 145 // instructions. They produce a vector result which is the reduction 146 // performed over the first vector operand plus the first element of the 147 // second vector operand. The first operand is an unconstrained vector type, 148 // and the result and second operand's types are expected to be the 149 // corresponding full-width LMUL=1 type for the first operand: 150 // nxv8i8 = vecreduce_add nxv32i8, nxv8i8 151 // nxv2i32 = vecreduce_add nxv8i32, nxv2i32 152 // The different in types does introduce extra vsetvli instructions but 153 // similarly it reduces the number of registers consumed per reduction. 154 // Also has a mask and VL operand. 155 VECREDUCE_ADD_VL, 156 VECREDUCE_UMAX_VL, 157 VECREDUCE_SMAX_VL, 158 VECREDUCE_UMIN_VL, 159 VECREDUCE_SMIN_VL, 160 VECREDUCE_AND_VL, 161 VECREDUCE_OR_VL, 162 VECREDUCE_XOR_VL, 163 VECREDUCE_FADD_VL, 164 VECREDUCE_SEQ_FADD_VL, 165 166 // Vector binary and unary ops with a mask as a third operand, and VL as a 167 // fourth operand. 168 // FIXME: Can we replace these with ISD::VP_*? 169 ADD_VL, 170 AND_VL, 171 MUL_VL, 172 OR_VL, 173 SDIV_VL, 174 SHL_VL, 175 SREM_VL, 176 SRA_VL, 177 SRL_VL, 178 SUB_VL, 179 UDIV_VL, 180 UREM_VL, 181 XOR_VL, 182 FADD_VL, 183 FSUB_VL, 184 FMUL_VL, 185 FDIV_VL, 186 FNEG_VL, 187 FABS_VL, 188 FSQRT_VL, 189 FMA_VL, 190 FCOPYSIGN_VL, 191 SMIN_VL, 192 SMAX_VL, 193 UMIN_VL, 194 UMAX_VL, 195 MULHS_VL, 196 MULHU_VL, 197 FP_TO_SINT_VL, 198 FP_TO_UINT_VL, 199 SINT_TO_FP_VL, 200 UINT_TO_FP_VL, 201 FP_ROUND_VL, 202 FP_EXTEND_VL, 203 204 // Vector compare producing a mask. Fourth operand is input mask. Fifth 205 // operand is VL. 206 SETCC_VL, 207 208 // Vector select with an additional VL operand. This operation is unmasked. 209 VSELECT_VL, 210 211 // Mask binary operators. 212 VMAND_VL, 213 VMOR_VL, 214 VMXOR_VL, 215 216 // Set mask vector to all zeros or ones. 217 VMCLR_VL, 218 VMSET_VL, 219 220 // Matches the semantics of vrgather.vx and vrgather.vv with an extra operand 221 // for VL. 222 VRGATHER_VX_VL, 223 VRGATHER_VV_VL, 224 VRGATHEREI16_VV_VL, 225 226 // Vector sign/zero extend with additional mask & VL operands. 227 VSEXT_VL, 228 VZEXT_VL, 229 // vpopc.m with additional mask and VL operands. 230 VPOPC_VL, 231 232 // Reads value of CSR. 233 // The first operand is a chain pointer. The second specifies address of the 234 // required CSR. Two results are produced, the read value and the new chain 235 // pointer. 236 READ_CSR, 237 // Write value to CSR. 238 // The first operand is a chain pointer, the second specifies address of the 239 // required CSR and the third is the value to write. The result is the new 240 // chain pointer. 241 WRITE_CSR, 242 // Read and write value of CSR. 243 // The first operand is a chain pointer, the second specifies address of the 244 // required CSR and the third is the value to write. Two results are produced, 245 // the value read before the modification and the new chain pointer. 246 SWAP_CSR, 247 248 // Memory opcodes start here. 249 VLE_VL = ISD::FIRST_TARGET_MEMORY_OPCODE, 250 VSE_VL, 251 252 // WARNING: Do not add anything in the end unless you want the node to 253 // have memop! In fact, starting from FIRST_TARGET_MEMORY_OPCODE all 254 // opcodes will be thought as target memory ops! 255 }; 256 } // namespace RISCVISD 257 258 class RISCVTargetLowering : public TargetLowering { 259 const RISCVSubtarget &Subtarget; 260 261 public: 262 explicit RISCVTargetLowering(const TargetMachine &TM, 263 const RISCVSubtarget &STI); 264 265 const RISCVSubtarget &getSubtarget() const { return Subtarget; } 266 267 bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I, 268 MachineFunction &MF, 269 unsigned Intrinsic) const override; 270 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, 271 unsigned AS, 272 Instruction *I = nullptr) const override; 273 bool isLegalICmpImmediate(int64_t Imm) const override; 274 bool isLegalAddImmediate(int64_t Imm) const override; 275 bool isTruncateFree(Type *SrcTy, Type *DstTy) const override; 276 bool isTruncateFree(EVT SrcVT, EVT DstVT) const override; 277 bool isZExtFree(SDValue Val, EVT VT2) const override; 278 bool isSExtCheaperThanZExt(EVT SrcVT, EVT DstVT) const override; 279 bool isCheapToSpeculateCttz() const override; 280 bool isCheapToSpeculateCtlz() const override; 281 bool isFPImmLegal(const APFloat &Imm, EVT VT, 282 bool ForCodeSize) const override; 283 284 bool softPromoteHalfType() const override { return true; } 285 286 /// Return the register type for a given MVT, ensuring vectors are treated 287 /// as a series of gpr sized integers. 288 MVT getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC, 289 EVT VT) const override; 290 291 /// Return the number of registers for a given MVT, ensuring vectors are 292 /// treated as a series of gpr sized integers. 293 unsigned getNumRegistersForCallingConv(LLVMContext &Context, 294 CallingConv::ID CC, 295 EVT VT) const override; 296 297 /// Return true if the given shuffle mask can be codegen'd directly, or if it 298 /// should be stack expanded. 299 bool isShuffleMaskLegal(ArrayRef<int> M, EVT VT) const override; 300 301 bool hasBitPreservingFPLogic(EVT VT) const override; 302 bool 303 shouldExpandBuildVectorWithShuffles(EVT VT, 304 unsigned DefinedValues) const override; 305 306 // Provide custom lowering hooks for some operations. 307 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override; 308 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results, 309 SelectionDAG &DAG) const override; 310 311 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override; 312 313 bool targetShrinkDemandedConstant(SDValue Op, const APInt &DemandedBits, 314 const APInt &DemandedElts, 315 TargetLoweringOpt &TLO) const override; 316 317 void computeKnownBitsForTargetNode(const SDValue Op, 318 KnownBits &Known, 319 const APInt &DemandedElts, 320 const SelectionDAG &DAG, 321 unsigned Depth) const override; 322 unsigned ComputeNumSignBitsForTargetNode(SDValue Op, 323 const APInt &DemandedElts, 324 const SelectionDAG &DAG, 325 unsigned Depth) const override; 326 327 // This method returns the name of a target specific DAG node. 328 const char *getTargetNodeName(unsigned Opcode) const override; 329 330 ConstraintType getConstraintType(StringRef Constraint) const override; 331 332 unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override; 333 334 std::pair<unsigned, const TargetRegisterClass *> 335 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, 336 StringRef Constraint, MVT VT) const override; 337 338 void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, 339 std::vector<SDValue> &Ops, 340 SelectionDAG &DAG) const override; 341 342 MachineBasicBlock * 343 EmitInstrWithCustomInserter(MachineInstr &MI, 344 MachineBasicBlock *BB) const override; 345 346 EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, 347 EVT VT) const override; 348 349 bool convertSetCCLogicToBitwiseLogic(EVT VT) const override { 350 return VT.isScalarInteger(); 351 } 352 bool convertSelectOfConstantsToMath(EVT VT) const override { return true; } 353 354 bool shouldInsertFencesForAtomic(const Instruction *I) const override { 355 return isa<LoadInst>(I) || isa<StoreInst>(I); 356 } 357 Instruction *emitLeadingFence(IRBuilder<> &Builder, Instruction *Inst, 358 AtomicOrdering Ord) const override; 359 Instruction *emitTrailingFence(IRBuilder<> &Builder, Instruction *Inst, 360 AtomicOrdering Ord) const override; 361 362 bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF, 363 EVT VT) const override; 364 365 ISD::NodeType getExtendForAtomicOps() const override { 366 return ISD::SIGN_EXTEND; 367 } 368 369 ISD::NodeType getExtendForAtomicCmpSwapArg() const override { 370 return ISD::SIGN_EXTEND; 371 } 372 373 bool shouldExpandShift(SelectionDAG &DAG, SDNode *N) const override { 374 if (DAG.getMachineFunction().getFunction().hasMinSize()) 375 return false; 376 return true; 377 } 378 bool isDesirableToCommuteWithShift(const SDNode *N, 379 CombineLevel Level) const override; 380 381 /// If a physical register, this returns the register that receives the 382 /// exception address on entry to an EH pad. 383 Register 384 getExceptionPointerRegister(const Constant *PersonalityFn) const override; 385 386 /// If a physical register, this returns the register that receives the 387 /// exception typeid on entry to a landing pad. 388 Register 389 getExceptionSelectorRegister(const Constant *PersonalityFn) const override; 390 391 bool shouldExtendTypeInLibCall(EVT Type) const override; 392 bool shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const override; 393 394 /// Returns the register with the specified architectural or ABI name. This 395 /// method is necessary to lower the llvm.read_register.* and 396 /// llvm.write_register.* intrinsics. Allocatable registers must be reserved 397 /// with the clang -ffixed-xX flag for access to be allowed. 398 Register getRegisterByName(const char *RegName, LLT VT, 399 const MachineFunction &MF) const override; 400 401 // Lower incoming arguments, copy physregs into vregs 402 SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, 403 bool IsVarArg, 404 const SmallVectorImpl<ISD::InputArg> &Ins, 405 const SDLoc &DL, SelectionDAG &DAG, 406 SmallVectorImpl<SDValue> &InVals) const override; 407 bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, 408 bool IsVarArg, 409 const SmallVectorImpl<ISD::OutputArg> &Outs, 410 LLVMContext &Context) const override; 411 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, 412 const SmallVectorImpl<ISD::OutputArg> &Outs, 413 const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL, 414 SelectionDAG &DAG) const override; 415 SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI, 416 SmallVectorImpl<SDValue> &InVals) const override; 417 418 bool shouldConvertConstantLoadToIntImm(const APInt &Imm, 419 Type *Ty) const override { 420 return true; 421 } 422 bool mayBeEmittedAsTailCall(const CallInst *CI) const override; 423 bool shouldConsiderGEPOffsetSplit() const override { return true; } 424 425 bool decomposeMulByConstant(LLVMContext &Context, EVT VT, 426 SDValue C) const override; 427 428 TargetLowering::AtomicExpansionKind 429 shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override; 430 Value *emitMaskedAtomicRMWIntrinsic(IRBuilder<> &Builder, AtomicRMWInst *AI, 431 Value *AlignedAddr, Value *Incr, 432 Value *Mask, Value *ShiftAmt, 433 AtomicOrdering Ord) const override; 434 TargetLowering::AtomicExpansionKind 435 shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *CI) const override; 436 Value *emitMaskedAtomicCmpXchgIntrinsic(IRBuilder<> &Builder, 437 AtomicCmpXchgInst *CI, 438 Value *AlignedAddr, Value *CmpVal, 439 Value *NewVal, Value *Mask, 440 AtomicOrdering Ord) const override; 441 442 /// Returns true if the target allows unaligned memory accesses of the 443 /// specified type. 444 bool allowsMisalignedMemoryAccesses( 445 EVT VT, unsigned AddrSpace = 0, Align Alignment = Align(1), 446 MachineMemOperand::Flags Flags = MachineMemOperand::MONone, 447 bool *Fast = nullptr) const override; 448 449 bool splitValueIntoRegisterParts(SelectionDAG &DAG, const SDLoc &DL, 450 SDValue Val, SDValue *Parts, 451 unsigned NumParts, MVT PartVT, 452 Optional<CallingConv::ID> CC) const override; 453 454 SDValue 455 joinRegisterPartsIntoValue(SelectionDAG &DAG, const SDLoc &DL, 456 const SDValue *Parts, unsigned NumParts, 457 MVT PartVT, EVT ValueVT, 458 Optional<CallingConv::ID> CC) const override; 459 460 static RISCVVLMUL getLMUL(MVT VT); 461 static unsigned getRegClassIDForLMUL(RISCVVLMUL LMul); 462 static unsigned getSubregIndexByMVT(MVT VT, unsigned Index); 463 static unsigned getRegClassIDForVecVT(MVT VT); 464 static std::pair<unsigned, unsigned> 465 decomposeSubvectorInsertExtractToSubRegs(MVT VecVT, MVT SubVecVT, 466 unsigned InsertExtractIdx, 467 const RISCVRegisterInfo *TRI); 468 MVT getContainerForFixedLengthVector(MVT VT) const; 469 static MVT getContainerForFixedLengthVector(const TargetLowering &TLI, MVT VT, 470 const RISCVSubtarget &Subtarget); 471 static MVT getContainerForFixedLengthVector(SelectionDAG &DAG, MVT VT, 472 const RISCVSubtarget &Subtarget); 473 474 bool shouldRemoveExtendFromGSIndex(EVT VT) const override; 475 476 private: 477 void analyzeInputArgs(MachineFunction &MF, CCState &CCInfo, 478 const SmallVectorImpl<ISD::InputArg> &Ins, 479 bool IsRet) const; 480 void analyzeOutputArgs(MachineFunction &MF, CCState &CCInfo, 481 const SmallVectorImpl<ISD::OutputArg> &Outs, 482 bool IsRet, CallLoweringInfo *CLI) const; 483 484 template <class NodeTy> 485 SDValue getAddr(NodeTy *N, SelectionDAG &DAG, bool IsLocal = true) const; 486 487 SDValue getStaticTLSAddr(GlobalAddressSDNode *N, SelectionDAG &DAG, 488 bool UseGOT) const; 489 SDValue getDynamicTLSAddr(GlobalAddressSDNode *N, SelectionDAG &DAG) const; 490 491 SDValue lowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const; 492 SDValue lowerBlockAddress(SDValue Op, SelectionDAG &DAG) const; 493 SDValue lowerConstantPool(SDValue Op, SelectionDAG &DAG) const; 494 SDValue lowerJumpTable(SDValue Op, SelectionDAG &DAG) const; 495 SDValue lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const; 496 SDValue lowerSELECT(SDValue Op, SelectionDAG &DAG) const; 497 SDValue lowerBRCOND(SDValue Op, SelectionDAG &DAG) const; 498 SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const; 499 SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const; 500 SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const; 501 SDValue lowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const; 502 SDValue lowerShiftRightParts(SDValue Op, SelectionDAG &DAG, bool IsSRA) const; 503 SDValue lowerSPLAT_VECTOR_PARTS(SDValue Op, SelectionDAG &DAG) const; 504 SDValue lowerVectorMaskExt(SDValue Op, SelectionDAG &DAG, 505 int64_t ExtTrueVal) const; 506 SDValue lowerVectorMaskTrunc(SDValue Op, SelectionDAG &DAG) const; 507 SDValue lowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const; 508 SDValue lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const; 509 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const; 510 SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const; 511 SDValue lowerVECREDUCE(SDValue Op, SelectionDAG &DAG) const; 512 SDValue lowerVectorMaskVECREDUCE(SDValue Op, SelectionDAG &DAG) const; 513 SDValue lowerFPVECREDUCE(SDValue Op, SelectionDAG &DAG) const; 514 SDValue lowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const; 515 SDValue lowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const; 516 SDValue lowerSTEP_VECTOR(SDValue Op, SelectionDAG &DAG) const; 517 SDValue lowerVECTOR_REVERSE(SDValue Op, SelectionDAG &DAG) const; 518 SDValue lowerABS(SDValue Op, SelectionDAG &DAG) const; 519 SDValue lowerMLOAD(SDValue Op, SelectionDAG &DAG) const; 520 SDValue lowerMSTORE(SDValue Op, SelectionDAG &DAG) const; 521 SDValue lowerFixedLengthVectorFCOPYSIGNToRVV(SDValue Op, 522 SelectionDAG &DAG) const; 523 SDValue lowerMGATHER(SDValue Op, SelectionDAG &DAG) const; 524 SDValue lowerMSCATTER(SDValue Op, SelectionDAG &DAG) const; 525 SDValue lowerFixedLengthVectorLoadToRVV(SDValue Op, SelectionDAG &DAG) const; 526 SDValue lowerFixedLengthVectorStoreToRVV(SDValue Op, SelectionDAG &DAG) const; 527 SDValue lowerFixedLengthVectorSetccToRVV(SDValue Op, SelectionDAG &DAG) const; 528 SDValue lowerFixedLengthVectorLogicOpToRVV(SDValue Op, SelectionDAG &DAG, 529 unsigned MaskOpc, 530 unsigned VecOpc) const; 531 SDValue lowerFixedLengthVectorSelectToRVV(SDValue Op, 532 SelectionDAG &DAG) const; 533 SDValue lowerToScalableOp(SDValue Op, SelectionDAG &DAG, unsigned NewOpc, 534 bool HasMask = true) const; 535 SDValue lowerFixedLengthVectorExtendToRVV(SDValue Op, SelectionDAG &DAG, 536 unsigned ExtendOpc) const; 537 538 bool isEligibleForTailCallOptimization( 539 CCState &CCInfo, CallLoweringInfo &CLI, MachineFunction &MF, 540 const SmallVector<CCValAssign, 16> &ArgLocs) const; 541 542 /// Generate error diagnostics if any register used by CC has been marked 543 /// reserved. 544 void validateCCReservedRegs( 545 const SmallVectorImpl<std::pair<llvm::Register, llvm::SDValue>> &Regs, 546 MachineFunction &MF) const; 547 548 bool useRVVForFixedLengthVectorVT(MVT VT) const; 549 }; 550 551 namespace RISCV { 552 // We use 64 bits as the known part in the scalable vector types. 553 static constexpr unsigned RVVBitsPerBlock = 64; 554 } // namespace RISCV 555 556 namespace RISCVVIntrinsicsTable { 557 558 struct RISCVVIntrinsicInfo { 559 unsigned IntrinsicID; 560 uint8_t SplatOperand; 561 }; 562 563 using namespace RISCV; 564 565 #define GET_RISCVVIntrinsicsTable_DECL 566 #include "RISCVGenSearchableTables.inc" 567 568 } // end namespace RISCVVIntrinsicsTable 569 570 } // end namespace llvm 571 572 #endif 573