1 //===-- RISCVISelLowering.h - RISCV DAG Lowering Interface ------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file defines the interfaces that RISCV uses to lower LLVM code into a 10 // selection DAG. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #ifndef LLVM_LIB_TARGET_RISCV_RISCVISELLOWERING_H 15 #define LLVM_LIB_TARGET_RISCV_RISCVISELLOWERING_H 16 17 #include "RISCV.h" 18 #include "llvm/CodeGen/SelectionDAG.h" 19 #include "llvm/CodeGen/TargetLowering.h" 20 21 namespace llvm { 22 class RISCVSubtarget; 23 struct RISCVRegisterInfo; 24 namespace RISCVISD { 25 enum NodeType : unsigned { 26 FIRST_NUMBER = ISD::BUILTIN_OP_END, 27 RET_FLAG, 28 URET_FLAG, 29 SRET_FLAG, 30 MRET_FLAG, 31 CALL, 32 /// Select with condition operator - This selects between a true value and 33 /// a false value (ops #3 and #4) based on the boolean result of comparing 34 /// the lhs and rhs (ops #0 and #1) of a conditional expression with the 35 /// condition code in op #2, a XLenVT constant from the ISD::CondCode enum. 36 /// The lhs and rhs are XLenVT integers. The true and false values can be 37 /// integer or floating point. 38 SELECT_CC, 39 BR_CC, 40 BuildPairF64, 41 SplitF64, 42 TAIL, 43 // Multiply high for signedxunsigned. 44 MULHSU, 45 // RV64I shifts, directly matching the semantics of the named RISC-V 46 // instructions. 47 SLLW, 48 SRAW, 49 SRLW, 50 // 32-bit operations from RV64M that can't be simply matched with a pattern 51 // at instruction selection time. These have undefined behavior for division 52 // by 0 or overflow (divw) like their target independent counterparts. 53 DIVW, 54 DIVUW, 55 REMUW, 56 // RV64IB rotates, directly matching the semantics of the named RISC-V 57 // instructions. 58 ROLW, 59 RORW, 60 // RV64IZbb bit counting instructions directly matching the semantics of the 61 // named RISC-V instructions. 62 CLZW, 63 CTZW, 64 // RV64IB/RV32IB funnel shifts, with the semantics of the named RISC-V 65 // instructions, but the same operand order as fshl/fshr intrinsics. 66 FSR, 67 FSL, 68 // RV64IB funnel shifts, with the semantics of the named RISC-V instructions, 69 // but the same operand order as fshl/fshr intrinsics. 70 FSRW, 71 FSLW, 72 // FPR<->GPR transfer operations when the FPR is smaller than XLEN, needed as 73 // XLEN is the only legal integer width. 74 // 75 // FMV_H_X matches the semantics of the FMV.H.X. 76 // FMV_X_ANYEXTH is similar to FMV.X.H but has an any-extended result. 77 // FMV_W_X_RV64 matches the semantics of the FMV.W.X. 78 // FMV_X_ANYEXTW_RV64 is similar to FMV.X.W but has an any-extended result. 79 // 80 // This is a more convenient semantic for producing dagcombines that remove 81 // unnecessary GPR->FPR->GPR moves. 82 FMV_H_X, 83 FMV_X_ANYEXTH, 84 FMV_W_X_RV64, 85 FMV_X_ANYEXTW_RV64, 86 // READ_CYCLE_WIDE - A read of the 64-bit cycle CSR on a 32-bit target 87 // (returns (Lo, Hi)). It takes a chain operand. 88 READ_CYCLE_WIDE, 89 // Generalized Reverse and Generalized Or-Combine - directly matching the 90 // semantics of the named RISC-V instructions. Lowered as custom nodes as 91 // TableGen chokes when faced with commutative permutations in deeply-nested 92 // DAGs. Each node takes an input operand and a control operand and outputs a 93 // bit-manipulated version of input. All operands are i32 or XLenVT. 94 GREV, 95 GREVW, 96 GORC, 97 GORCW, 98 SHFL, 99 SHFLW, 100 UNSHFL, 101 UNSHFLW, 102 // Vector Extension 103 // VMV_V_X_VL matches the semantics of vmv.v.x but includes an extra operand 104 // for the VL value to be used for the operation. 105 VMV_V_X_VL, 106 // VFMV_V_F_VL matches the semantics of vfmv.v.f but includes an extra operand 107 // for the VL value to be used for the operation. 108 VFMV_V_F_VL, 109 // VMV_X_S matches the semantics of vmv.x.s. The result is always XLenVT sign 110 // extended from the vector element size. 111 VMV_X_S, 112 // VMV_S_X_VL matches the semantics of vmv.s.x. It carries a VL operand. 113 VMV_S_X_VL, 114 // VFMV_S_F_VL matches the semantics of vfmv.s.f. It carries a VL operand. 115 VFMV_S_F_VL, 116 // Splats an i64 scalar to a vector type (with element type i64) where the 117 // scalar is a sign-extended i32. 118 SPLAT_VECTOR_I64, 119 // Read VLENB CSR 120 READ_VLENB, 121 // Truncates a RVV integer vector by one power-of-two. Carries both an extra 122 // mask and VL operand. 123 TRUNCATE_VECTOR_VL, 124 // Unit-stride fault-only-first load 125 VLEFF, 126 VLEFF_MASK, 127 // Matches the semantics of vslideup/vslidedown. The first operand is the 128 // pass-thru operand, the second is the source vector, the third is the 129 // XLenVT index (either constant or non-constant), the fourth is the mask 130 // and the fifth the VL. 131 VSLIDEUP_VL, 132 VSLIDEDOWN_VL, 133 // Matches the semantics of vslide1up/slide1down. The first operand is the 134 // source vector, the second is the XLenVT scalar value. The third and fourth 135 // operands are the mask and VL operands. 136 VSLIDE1UP_VL, 137 VSLIDE1DOWN_VL, 138 // Matches the semantics of the vid.v instruction, with a mask and VL 139 // operand. 140 VID_VL, 141 // Matches the semantics of the vfcnvt.rod function (Convert double-width 142 // float to single-width float, rounding towards odd). Takes a double-width 143 // float vector and produces a single-width float vector. Also has a mask and 144 // VL operand. 145 VFNCVT_ROD_VL, 146 // These nodes match the semantics of the corresponding RVV vector reduction 147 // instructions. They produce a vector result which is the reduction 148 // performed over the first vector operand plus the first element of the 149 // second vector operand. The first operand is an unconstrained vector type, 150 // and the result and second operand's types are expected to be the 151 // corresponding full-width LMUL=1 type for the first operand: 152 // nxv8i8 = vecreduce_add nxv32i8, nxv8i8 153 // nxv2i32 = vecreduce_add nxv8i32, nxv2i32 154 // The different in types does introduce extra vsetvli instructions but 155 // similarly it reduces the number of registers consumed per reduction. 156 // Also has a mask and VL operand. 157 VECREDUCE_ADD_VL, 158 VECREDUCE_UMAX_VL, 159 VECREDUCE_SMAX_VL, 160 VECREDUCE_UMIN_VL, 161 VECREDUCE_SMIN_VL, 162 VECREDUCE_AND_VL, 163 VECREDUCE_OR_VL, 164 VECREDUCE_XOR_VL, 165 VECREDUCE_FADD_VL, 166 VECREDUCE_SEQ_FADD_VL, 167 168 // Vector binary and unary ops with a mask as a third operand, and VL as a 169 // fourth operand. 170 // FIXME: Can we replace these with ISD::VP_*? 171 ADD_VL, 172 AND_VL, 173 MUL_VL, 174 OR_VL, 175 SDIV_VL, 176 SHL_VL, 177 SREM_VL, 178 SRA_VL, 179 SRL_VL, 180 SUB_VL, 181 UDIV_VL, 182 UREM_VL, 183 XOR_VL, 184 FADD_VL, 185 FSUB_VL, 186 FMUL_VL, 187 FDIV_VL, 188 FNEG_VL, 189 FABS_VL, 190 FSQRT_VL, 191 FMA_VL, 192 FCOPYSIGN_VL, 193 SMIN_VL, 194 SMAX_VL, 195 UMIN_VL, 196 UMAX_VL, 197 MULHS_VL, 198 MULHU_VL, 199 FP_TO_SINT_VL, 200 FP_TO_UINT_VL, 201 SINT_TO_FP_VL, 202 UINT_TO_FP_VL, 203 FP_ROUND_VL, 204 FP_EXTEND_VL, 205 206 // Vector compare producing a mask. Fourth operand is input mask. Fifth 207 // operand is VL. 208 SETCC_VL, 209 210 // Vector select with an additional VL operand. This operation is unmasked. 211 VSELECT_VL, 212 213 // Mask binary operators. 214 VMAND_VL, 215 VMOR_VL, 216 VMXOR_VL, 217 218 // Set mask vector to all zeros or ones. 219 VMCLR_VL, 220 VMSET_VL, 221 222 // Matches the semantics of vrgather.vx and vrgather.vv with an extra operand 223 // for VL. 224 VRGATHER_VX_VL, 225 VRGATHER_VV_VL, 226 VRGATHEREI16_VV_VL, 227 228 // Vector sign/zero extend with additional mask & VL operands. 229 VSEXT_VL, 230 VZEXT_VL, 231 // vpopc.m with additional mask and VL operands. 232 VPOPC_VL, 233 234 // Reads value of CSR. 235 // The first operand is a chain pointer. The second specifies address of the 236 // required CSR. Two results are produced, the read value and the new chain 237 // pointer. 238 READ_CSR, 239 // Write value to CSR. 240 // The first operand is a chain pointer, the second specifies address of the 241 // required CSR and the third is the value to write. The result is the new 242 // chain pointer. 243 WRITE_CSR, 244 // Read and write value of CSR. 245 // The first operand is a chain pointer, the second specifies address of the 246 // required CSR and the third is the value to write. Two results are produced, 247 // the value read before the modification and the new chain pointer. 248 SWAP_CSR, 249 250 // Memory opcodes start here. 251 VLE_VL = ISD::FIRST_TARGET_MEMORY_OPCODE, 252 VSE_VL, 253 254 // WARNING: Do not add anything in the end unless you want the node to 255 // have memop! In fact, starting from FIRST_TARGET_MEMORY_OPCODE all 256 // opcodes will be thought as target memory ops! 257 }; 258 } // namespace RISCVISD 259 260 class RISCVTargetLowering : public TargetLowering { 261 const RISCVSubtarget &Subtarget; 262 263 public: 264 explicit RISCVTargetLowering(const TargetMachine &TM, 265 const RISCVSubtarget &STI); 266 267 const RISCVSubtarget &getSubtarget() const { return Subtarget; } 268 269 bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I, 270 MachineFunction &MF, 271 unsigned Intrinsic) const override; 272 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, 273 unsigned AS, 274 Instruction *I = nullptr) const override; 275 bool isLegalICmpImmediate(int64_t Imm) const override; 276 bool isLegalAddImmediate(int64_t Imm) const override; 277 bool isTruncateFree(Type *SrcTy, Type *DstTy) const override; 278 bool isTruncateFree(EVT SrcVT, EVT DstVT) const override; 279 bool isZExtFree(SDValue Val, EVT VT2) const override; 280 bool isSExtCheaperThanZExt(EVT SrcVT, EVT DstVT) const override; 281 bool isCheapToSpeculateCttz() const override; 282 bool isCheapToSpeculateCtlz() const override; 283 bool isFPImmLegal(const APFloat &Imm, EVT VT, 284 bool ForCodeSize) const override; 285 286 bool softPromoteHalfType() const override { return true; } 287 288 /// Return the register type for a given MVT, ensuring vectors are treated 289 /// as a series of gpr sized integers. 290 MVT getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC, 291 EVT VT) const override; 292 293 /// Return the number of registers for a given MVT, ensuring vectors are 294 /// treated as a series of gpr sized integers. 295 unsigned getNumRegistersForCallingConv(LLVMContext &Context, 296 CallingConv::ID CC, 297 EVT VT) const override; 298 299 /// Return true if the given shuffle mask can be codegen'd directly, or if it 300 /// should be stack expanded. 301 bool isShuffleMaskLegal(ArrayRef<int> M, EVT VT) const override; 302 303 bool hasBitPreservingFPLogic(EVT VT) const override; 304 bool 305 shouldExpandBuildVectorWithShuffles(EVT VT, 306 unsigned DefinedValues) const override; 307 308 // Provide custom lowering hooks for some operations. 309 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override; 310 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results, 311 SelectionDAG &DAG) const override; 312 313 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override; 314 315 bool targetShrinkDemandedConstant(SDValue Op, const APInt &DemandedBits, 316 const APInt &DemandedElts, 317 TargetLoweringOpt &TLO) const override; 318 319 void computeKnownBitsForTargetNode(const SDValue Op, 320 KnownBits &Known, 321 const APInt &DemandedElts, 322 const SelectionDAG &DAG, 323 unsigned Depth) const override; 324 unsigned ComputeNumSignBitsForTargetNode(SDValue Op, 325 const APInt &DemandedElts, 326 const SelectionDAG &DAG, 327 unsigned Depth) const override; 328 329 // This method returns the name of a target specific DAG node. 330 const char *getTargetNodeName(unsigned Opcode) const override; 331 332 ConstraintType getConstraintType(StringRef Constraint) const override; 333 334 unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override; 335 336 std::pair<unsigned, const TargetRegisterClass *> 337 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, 338 StringRef Constraint, MVT VT) const override; 339 340 void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, 341 std::vector<SDValue> &Ops, 342 SelectionDAG &DAG) const override; 343 344 MachineBasicBlock * 345 EmitInstrWithCustomInserter(MachineInstr &MI, 346 MachineBasicBlock *BB) const override; 347 348 EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, 349 EVT VT) const override; 350 351 bool convertSetCCLogicToBitwiseLogic(EVT VT) const override { 352 return VT.isScalarInteger(); 353 } 354 bool convertSelectOfConstantsToMath(EVT VT) const override { return true; } 355 356 bool shouldInsertFencesForAtomic(const Instruction *I) const override { 357 return isa<LoadInst>(I) || isa<StoreInst>(I); 358 } 359 Instruction *emitLeadingFence(IRBuilder<> &Builder, Instruction *Inst, 360 AtomicOrdering Ord) const override; 361 Instruction *emitTrailingFence(IRBuilder<> &Builder, Instruction *Inst, 362 AtomicOrdering Ord) const override; 363 364 bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF, 365 EVT VT) const override; 366 367 ISD::NodeType getExtendForAtomicOps() const override { 368 return ISD::SIGN_EXTEND; 369 } 370 371 ISD::NodeType getExtendForAtomicCmpSwapArg() const override { 372 return ISD::SIGN_EXTEND; 373 } 374 375 bool shouldExpandShift(SelectionDAG &DAG, SDNode *N) const override { 376 if (DAG.getMachineFunction().getFunction().hasMinSize()) 377 return false; 378 return true; 379 } 380 bool isDesirableToCommuteWithShift(const SDNode *N, 381 CombineLevel Level) const override; 382 383 /// If a physical register, this returns the register that receives the 384 /// exception address on entry to an EH pad. 385 Register 386 getExceptionPointerRegister(const Constant *PersonalityFn) const override; 387 388 /// If a physical register, this returns the register that receives the 389 /// exception typeid on entry to a landing pad. 390 Register 391 getExceptionSelectorRegister(const Constant *PersonalityFn) const override; 392 393 bool shouldExtendTypeInLibCall(EVT Type) const override; 394 bool shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const override; 395 396 /// Returns the register with the specified architectural or ABI name. This 397 /// method is necessary to lower the llvm.read_register.* and 398 /// llvm.write_register.* intrinsics. Allocatable registers must be reserved 399 /// with the clang -ffixed-xX flag for access to be allowed. 400 Register getRegisterByName(const char *RegName, LLT VT, 401 const MachineFunction &MF) const override; 402 403 // Lower incoming arguments, copy physregs into vregs 404 SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, 405 bool IsVarArg, 406 const SmallVectorImpl<ISD::InputArg> &Ins, 407 const SDLoc &DL, SelectionDAG &DAG, 408 SmallVectorImpl<SDValue> &InVals) const override; 409 bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, 410 bool IsVarArg, 411 const SmallVectorImpl<ISD::OutputArg> &Outs, 412 LLVMContext &Context) const override; 413 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, 414 const SmallVectorImpl<ISD::OutputArg> &Outs, 415 const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL, 416 SelectionDAG &DAG) const override; 417 SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI, 418 SmallVectorImpl<SDValue> &InVals) const override; 419 420 bool shouldConvertConstantLoadToIntImm(const APInt &Imm, 421 Type *Ty) const override { 422 return true; 423 } 424 bool mayBeEmittedAsTailCall(const CallInst *CI) const override; 425 bool shouldConsiderGEPOffsetSplit() const override { return true; } 426 427 bool decomposeMulByConstant(LLVMContext &Context, EVT VT, 428 SDValue C) const override; 429 430 TargetLowering::AtomicExpansionKind 431 shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override; 432 Value *emitMaskedAtomicRMWIntrinsic(IRBuilder<> &Builder, AtomicRMWInst *AI, 433 Value *AlignedAddr, Value *Incr, 434 Value *Mask, Value *ShiftAmt, 435 AtomicOrdering Ord) const override; 436 TargetLowering::AtomicExpansionKind 437 shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *CI) const override; 438 Value *emitMaskedAtomicCmpXchgIntrinsic(IRBuilder<> &Builder, 439 AtomicCmpXchgInst *CI, 440 Value *AlignedAddr, Value *CmpVal, 441 Value *NewVal, Value *Mask, 442 AtomicOrdering Ord) const override; 443 444 /// Returns true if the target allows unaligned memory accesses of the 445 /// specified type. 446 bool allowsMisalignedMemoryAccesses( 447 EVT VT, unsigned AddrSpace = 0, Align Alignment = Align(1), 448 MachineMemOperand::Flags Flags = MachineMemOperand::MONone, 449 bool *Fast = nullptr) const override; 450 451 bool splitValueIntoRegisterParts(SelectionDAG &DAG, const SDLoc &DL, 452 SDValue Val, SDValue *Parts, 453 unsigned NumParts, MVT PartVT, 454 Optional<CallingConv::ID> CC) const override; 455 456 SDValue 457 joinRegisterPartsIntoValue(SelectionDAG &DAG, const SDLoc &DL, 458 const SDValue *Parts, unsigned NumParts, 459 MVT PartVT, EVT ValueVT, 460 Optional<CallingConv::ID> CC) const override; 461 462 static RISCVVLMUL getLMUL(MVT VT); 463 static unsigned getRegClassIDForLMUL(RISCVVLMUL LMul); 464 static unsigned getSubregIndexByMVT(MVT VT, unsigned Index); 465 static unsigned getRegClassIDForVecVT(MVT VT); 466 static std::pair<unsigned, unsigned> 467 decomposeSubvectorInsertExtractToSubRegs(MVT VecVT, MVT SubVecVT, 468 unsigned InsertExtractIdx, 469 const RISCVRegisterInfo *TRI); 470 MVT getContainerForFixedLengthVector(MVT VT) const; 471 static MVT getContainerForFixedLengthVector(const TargetLowering &TLI, MVT VT, 472 const RISCVSubtarget &Subtarget); 473 static MVT getContainerForFixedLengthVector(SelectionDAG &DAG, MVT VT, 474 const RISCVSubtarget &Subtarget); 475 476 bool shouldRemoveExtendFromGSIndex(EVT VT) const override; 477 478 private: 479 void analyzeInputArgs(MachineFunction &MF, CCState &CCInfo, 480 const SmallVectorImpl<ISD::InputArg> &Ins, 481 bool IsRet) const; 482 void analyzeOutputArgs(MachineFunction &MF, CCState &CCInfo, 483 const SmallVectorImpl<ISD::OutputArg> &Outs, 484 bool IsRet, CallLoweringInfo *CLI) const; 485 486 template <class NodeTy> 487 SDValue getAddr(NodeTy *N, SelectionDAG &DAG, bool IsLocal = true) const; 488 489 SDValue getStaticTLSAddr(GlobalAddressSDNode *N, SelectionDAG &DAG, 490 bool UseGOT) const; 491 SDValue getDynamicTLSAddr(GlobalAddressSDNode *N, SelectionDAG &DAG) const; 492 493 SDValue lowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const; 494 SDValue lowerBlockAddress(SDValue Op, SelectionDAG &DAG) const; 495 SDValue lowerConstantPool(SDValue Op, SelectionDAG &DAG) const; 496 SDValue lowerJumpTable(SDValue Op, SelectionDAG &DAG) const; 497 SDValue lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const; 498 SDValue lowerSELECT(SDValue Op, SelectionDAG &DAG) const; 499 SDValue lowerBRCOND(SDValue Op, SelectionDAG &DAG) const; 500 SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const; 501 SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const; 502 SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const; 503 SDValue lowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const; 504 SDValue lowerShiftRightParts(SDValue Op, SelectionDAG &DAG, bool IsSRA) const; 505 SDValue lowerSPLAT_VECTOR_PARTS(SDValue Op, SelectionDAG &DAG) const; 506 SDValue lowerVectorMaskExt(SDValue Op, SelectionDAG &DAG, 507 int64_t ExtTrueVal) const; 508 SDValue lowerVectorMaskTrunc(SDValue Op, SelectionDAG &DAG) const; 509 SDValue lowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const; 510 SDValue lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const; 511 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const; 512 SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const; 513 SDValue lowerVECREDUCE(SDValue Op, SelectionDAG &DAG) const; 514 SDValue lowerVectorMaskVECREDUCE(SDValue Op, SelectionDAG &DAG) const; 515 SDValue lowerFPVECREDUCE(SDValue Op, SelectionDAG &DAG) const; 516 SDValue lowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const; 517 SDValue lowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const; 518 SDValue lowerSTEP_VECTOR(SDValue Op, SelectionDAG &DAG) const; 519 SDValue lowerVECTOR_REVERSE(SDValue Op, SelectionDAG &DAG) const; 520 SDValue lowerABS(SDValue Op, SelectionDAG &DAG) const; 521 SDValue lowerMLOAD(SDValue Op, SelectionDAG &DAG) const; 522 SDValue lowerMSTORE(SDValue Op, SelectionDAG &DAG) const; 523 SDValue lowerFixedLengthVectorFCOPYSIGNToRVV(SDValue Op, 524 SelectionDAG &DAG) const; 525 SDValue lowerMGATHER(SDValue Op, SelectionDAG &DAG) const; 526 SDValue lowerMSCATTER(SDValue Op, SelectionDAG &DAG) const; 527 SDValue lowerFixedLengthVectorLoadToRVV(SDValue Op, SelectionDAG &DAG) const; 528 SDValue lowerFixedLengthVectorStoreToRVV(SDValue Op, SelectionDAG &DAG) const; 529 SDValue lowerFixedLengthVectorSetccToRVV(SDValue Op, SelectionDAG &DAG) const; 530 SDValue lowerFixedLengthVectorLogicOpToRVV(SDValue Op, SelectionDAG &DAG, 531 unsigned MaskOpc, 532 unsigned VecOpc) const; 533 SDValue lowerFixedLengthVectorSelectToRVV(SDValue Op, 534 SelectionDAG &DAG) const; 535 SDValue lowerToScalableOp(SDValue Op, SelectionDAG &DAG, unsigned NewOpc, 536 bool HasMask = true) const; 537 SDValue lowerFixedLengthVectorExtendToRVV(SDValue Op, SelectionDAG &DAG, 538 unsigned ExtendOpc) const; 539 SDValue lowerGET_ROUNDING(SDValue Op, SelectionDAG &DAG) const; 540 SDValue lowerSET_ROUNDING(SDValue Op, SelectionDAG &DAG) const; 541 542 bool isEligibleForTailCallOptimization( 543 CCState &CCInfo, CallLoweringInfo &CLI, MachineFunction &MF, 544 const SmallVector<CCValAssign, 16> &ArgLocs) const; 545 546 /// Generate error diagnostics if any register used by CC has been marked 547 /// reserved. 548 void validateCCReservedRegs( 549 const SmallVectorImpl<std::pair<llvm::Register, llvm::SDValue>> &Regs, 550 MachineFunction &MF) const; 551 552 bool useRVVForFixedLengthVectorVT(MVT VT) const; 553 }; 554 555 namespace RISCV { 556 // We use 64 bits as the known part in the scalable vector types. 557 static constexpr unsigned RVVBitsPerBlock = 64; 558 } // namespace RISCV 559 560 namespace RISCVVIntrinsicsTable { 561 562 struct RISCVVIntrinsicInfo { 563 unsigned IntrinsicID; 564 uint8_t SplatOperand; 565 }; 566 567 using namespace RISCV; 568 569 #define GET_RISCVVIntrinsicsTable_DECL 570 #include "RISCVGenSearchableTables.inc" 571 572 } // end namespace RISCVVIntrinsicsTable 573 574 } // end namespace llvm 575 576 #endif 577