1 //===----- RISCVCodeGenPrepare.cpp ----------------------------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This is a RISCV specific version of CodeGenPrepare.
10 // It munges the code in the input function to better prepare it for
11 // SelectionDAG-based code generation. This works around limitations in it's
12 // basic-block-at-a-time approach.
13 //
14 //===----------------------------------------------------------------------===//
15 
16 #include "RISCV.h"
17 #include "RISCVTargetMachine.h"
18 #include "llvm/ADT/Statistic.h"
19 #include "llvm/Analysis/ValueTracking.h"
20 #include "llvm/CodeGen/TargetPassConfig.h"
21 #include "llvm/InitializePasses.h"
22 #include "llvm/Pass.h"
23 
24 using namespace llvm;
25 
26 #define DEBUG_TYPE "riscv-codegenprepare"
27 #define PASS_NAME "RISCV CodeGenPrepare"
28 
29 STATISTIC(NumZExtToSExt, "Number of SExt instructions converted to ZExt");
30 
31 namespace {
32 
33 class RISCVCodeGenPrepare : public FunctionPass {
34   const DataLayout *DL;
35   const RISCVSubtarget *ST;
36 
37 public:
38   static char ID;
39 
40   RISCVCodeGenPrepare() : FunctionPass(ID) {}
41 
42   bool runOnFunction(Function &F) override;
43 
44   StringRef getPassName() const override { return PASS_NAME; }
45 
46   void getAnalysisUsage(AnalysisUsage &AU) const override {
47     AU.setPreservesCFG();
48     AU.addRequired<TargetPassConfig>();
49   }
50 
51 private:
52   bool optimizeZExt(ZExtInst *I);
53 };
54 
55 } // end anonymous namespace
56 
57 bool RISCVCodeGenPrepare::optimizeZExt(ZExtInst *ZExt) {
58   if (!ST->is64Bit())
59     return false;
60 
61   Value *Src = ZExt->getOperand(0);
62 
63   // We only care about ZExt from i32 to i64.
64   if (!ZExt->getType()->isIntegerTy(64) || !Src->getType()->isIntegerTy(32))
65     return false;
66 
67   // Look for an opportunity to replace (i64 (zext (i32 X))) with a sext if we
68   // can determine that the sign bit of X is zero via a dominating condition.
69   // This often occurs with widened induction variables.
70   if (isImpliedByDomCondition(ICmpInst::ICMP_SGE, Src,
71                               Constant::getNullValue(Src->getType()), ZExt,
72                               *DL)) {
73     auto *SExt = new SExtInst(Src, ZExt->getType(), "", ZExt);
74     SExt->takeName(ZExt);
75     SExt->setDebugLoc(ZExt->getDebugLoc());
76 
77     ZExt->replaceAllUsesWith(SExt);
78     ZExt->eraseFromParent();
79     ++NumZExtToSExt;
80     return true;
81   }
82 
83   return false;
84 }
85 
86 bool RISCVCodeGenPrepare::runOnFunction(Function &F) {
87   if (skipFunction(F))
88     return false;
89 
90   auto &TPC = getAnalysis<TargetPassConfig>();
91   auto &TM = TPC.getTM<RISCVTargetMachine>();
92   ST = &TM.getSubtarget<RISCVSubtarget>(F);
93 
94   DL = &F.getParent()->getDataLayout();
95 
96   bool MadeChange = false;
97   for (auto &BB : F) {
98     for (Instruction &I : llvm::make_early_inc_range(BB)) {
99       if (auto *ZExt = dyn_cast<ZExtInst>(&I))
100         MadeChange |= optimizeZExt(ZExt);
101     }
102   }
103 
104   return MadeChange;
105 }
106 
107 INITIALIZE_PASS_BEGIN(RISCVCodeGenPrepare, DEBUG_TYPE, PASS_NAME, false, false)
108 INITIALIZE_PASS_DEPENDENCY(TargetPassConfig)
109 INITIALIZE_PASS_END(RISCVCodeGenPrepare, DEBUG_TYPE, PASS_NAME, false, false)
110 
111 char RISCVCodeGenPrepare::ID = 0;
112 
113 FunctionPass *llvm::createRISCVCodeGenPreparePass() {
114   return new RISCVCodeGenPrepare();
115 }
116