1 //===-- RISCVTargetStreamer.cpp - RISCV Target Streamer Methods -----------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file provides RISCV specific target streamer methods.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "RISCVTargetStreamer.h"
14 #include "RISCVMCTargetDesc.h"
15 #include "llvm/Support/FormattedStream.h"
16 #include "llvm/Support/RISCVAttributes.h"
17 
18 using namespace llvm;
19 
20 RISCVTargetStreamer::RISCVTargetStreamer(MCStreamer &S) : MCTargetStreamer(S) {}
21 
22 void RISCVTargetStreamer::finish() { finishAttributeSection(); }
23 
24 void RISCVTargetStreamer::emitDirectiveOptionPush() {}
25 void RISCVTargetStreamer::emitDirectiveOptionPop() {}
26 void RISCVTargetStreamer::emitDirectiveOptionPIC() {}
27 void RISCVTargetStreamer::emitDirectiveOptionNoPIC() {}
28 void RISCVTargetStreamer::emitDirectiveOptionRVC() {}
29 void RISCVTargetStreamer::emitDirectiveOptionNoRVC() {}
30 void RISCVTargetStreamer::emitDirectiveOptionRelax() {}
31 void RISCVTargetStreamer::emitDirectiveOptionNoRelax() {}
32 void RISCVTargetStreamer::emitAttribute(unsigned Attribute, unsigned Value) {}
33 void RISCVTargetStreamer::finishAttributeSection() {}
34 void RISCVTargetStreamer::emitTextAttribute(unsigned Attribute,
35                                             StringRef String) {}
36 void RISCVTargetStreamer::emitIntTextAttribute(unsigned Attribute,
37                                                unsigned IntValue,
38                                                StringRef StringValue) {}
39 
40 void RISCVTargetStreamer::emitTargetAttributes(const MCSubtargetInfo &STI) {
41   if (STI.hasFeature(RISCV::FeatureRV32E))
42     emitAttribute(RISCVAttrs::STACK_ALIGN, RISCVAttrs::ALIGN_4);
43   else
44     emitAttribute(RISCVAttrs::STACK_ALIGN, RISCVAttrs::ALIGN_16);
45 
46   std::string Arch = "rv32";
47   if (STI.hasFeature(RISCV::Feature64Bit))
48     Arch = "rv64";
49   if (STI.hasFeature(RISCV::FeatureRV32E))
50     Arch += "e1p9";
51   else
52     Arch += "i2p0";
53   if (STI.hasFeature(RISCV::FeatureStdExtM))
54     Arch += "_m2p0";
55   if (STI.hasFeature(RISCV::FeatureStdExtA))
56     Arch += "_a2p0";
57   if (STI.hasFeature(RISCV::FeatureStdExtF))
58     Arch += "_f2p0";
59   if (STI.hasFeature(RISCV::FeatureStdExtD))
60     Arch += "_d2p0";
61   if (STI.hasFeature(RISCV::FeatureStdExtC))
62     Arch += "_c2p0";
63   if (STI.hasFeature(RISCV::FeatureStdExtB))
64     Arch += "_b0p93";
65   if (STI.hasFeature(RISCV::FeatureStdExtV))
66     Arch += "_v0p10";
67   if (STI.hasFeature(RISCV::FeatureStdExtZfh))
68     Arch += "_zfh0p1";
69   if (STI.hasFeature(RISCV::FeatureStdExtZba))
70     Arch += "_zba0p93";
71   if (STI.hasFeature(RISCV::FeatureStdExtZbb))
72     Arch += "_zbb0p93";
73   if (STI.hasFeature(RISCV::FeatureStdExtZbc))
74     Arch += "_zbc0p93";
75   if (STI.hasFeature(RISCV::FeatureStdExtZbe))
76     Arch += "_zbe0p93";
77   if (STI.hasFeature(RISCV::FeatureStdExtZbf))
78     Arch += "_zbf0p93";
79   if (STI.hasFeature(RISCV::FeatureStdExtZbm))
80     Arch += "_zbm0p93";
81   if (STI.hasFeature(RISCV::FeatureStdExtZbp))
82     Arch += "_zbp0p93";
83   if (STI.hasFeature(RISCV::FeatureStdExtZbr))
84     Arch += "_zbr0p93";
85   if (STI.hasFeature(RISCV::FeatureStdExtZbs))
86     Arch += "_zbs0p93";
87   if (STI.hasFeature(RISCV::FeatureStdExtZbt))
88     Arch += "_zbt0p93";
89   if (STI.hasFeature(RISCV::FeatureStdExtZvamo))
90     Arch += "_zvamo0p10";
91   if (STI.hasFeature(RISCV::FeatureStdExtZvlsseg))
92     Arch += "_zvlsseg0p10";
93 
94   emitTextAttribute(RISCVAttrs::ARCH, Arch);
95 }
96 
97 // This part is for ascii assembly output
98 RISCVTargetAsmStreamer::RISCVTargetAsmStreamer(MCStreamer &S,
99                                                formatted_raw_ostream &OS)
100     : RISCVTargetStreamer(S), OS(OS) {}
101 
102 void RISCVTargetAsmStreamer::emitDirectiveOptionPush() {
103   OS << "\t.option\tpush\n";
104 }
105 
106 void RISCVTargetAsmStreamer::emitDirectiveOptionPop() {
107   OS << "\t.option\tpop\n";
108 }
109 
110 void RISCVTargetAsmStreamer::emitDirectiveOptionPIC() {
111   OS << "\t.option\tpic\n";
112 }
113 
114 void RISCVTargetAsmStreamer::emitDirectiveOptionNoPIC() {
115   OS << "\t.option\tnopic\n";
116 }
117 
118 void RISCVTargetAsmStreamer::emitDirectiveOptionRVC() {
119   OS << "\t.option\trvc\n";
120 }
121 
122 void RISCVTargetAsmStreamer::emitDirectiveOptionNoRVC() {
123   OS << "\t.option\tnorvc\n";
124 }
125 
126 void RISCVTargetAsmStreamer::emitDirectiveOptionRelax() {
127   OS << "\t.option\trelax\n";
128 }
129 
130 void RISCVTargetAsmStreamer::emitDirectiveOptionNoRelax() {
131   OS << "\t.option\tnorelax\n";
132 }
133 
134 void RISCVTargetAsmStreamer::emitAttribute(unsigned Attribute, unsigned Value) {
135   OS << "\t.attribute\t" << Attribute << ", " << Twine(Value) << "\n";
136 }
137 
138 void RISCVTargetAsmStreamer::emitTextAttribute(unsigned Attribute,
139                                                StringRef String) {
140   OS << "\t.attribute\t" << Attribute << ", \"" << String << "\"\n";
141 }
142 
143 void RISCVTargetAsmStreamer::emitIntTextAttribute(unsigned Attribute,
144                                                   unsigned IntValue,
145                                                   StringRef StringValue) {}
146 
147 void RISCVTargetAsmStreamer::finishAttributeSection() {}
148