1 //===-- RISCVMCCodeEmitter.cpp - Convert RISCV code to machine code -------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file implements the RISCVMCCodeEmitter class. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "MCTargetDesc/RISCVBaseInfo.h" 14 #include "MCTargetDesc/RISCVFixupKinds.h" 15 #include "MCTargetDesc/RISCVMCExpr.h" 16 #include "MCTargetDesc/RISCVMCTargetDesc.h" 17 #include "llvm/ADT/Statistic.h" 18 #include "llvm/MC/MCAsmInfo.h" 19 #include "llvm/MC/MCCodeEmitter.h" 20 #include "llvm/MC/MCContext.h" 21 #include "llvm/MC/MCExpr.h" 22 #include "llvm/MC/MCInst.h" 23 #include "llvm/MC/MCInstBuilder.h" 24 #include "llvm/MC/MCInstrInfo.h" 25 #include "llvm/MC/MCRegisterInfo.h" 26 #include "llvm/MC/MCSubtargetInfo.h" 27 #include "llvm/MC/MCSymbol.h" 28 #include "llvm/Support/Casting.h" 29 #include "llvm/Support/EndianStream.h" 30 #include "llvm/Support/raw_ostream.h" 31 32 using namespace llvm; 33 34 #define DEBUG_TYPE "mccodeemitter" 35 36 STATISTIC(MCNumEmitted, "Number of MC instructions emitted"); 37 STATISTIC(MCNumFixups, "Number of MC fixups created"); 38 39 namespace { 40 class RISCVMCCodeEmitter : public MCCodeEmitter { 41 RISCVMCCodeEmitter(const RISCVMCCodeEmitter &) = delete; 42 void operator=(const RISCVMCCodeEmitter &) = delete; 43 MCContext &Ctx; 44 MCInstrInfo const &MCII; 45 46 public: 47 RISCVMCCodeEmitter(MCContext &ctx, MCInstrInfo const &MCII) 48 : Ctx(ctx), MCII(MCII) {} 49 50 ~RISCVMCCodeEmitter() override = default; 51 52 void encodeInstruction(const MCInst &MI, raw_ostream &OS, 53 SmallVectorImpl<MCFixup> &Fixups, 54 const MCSubtargetInfo &STI) const override; 55 56 void expandFunctionCall(const MCInst &MI, raw_ostream &OS, 57 SmallVectorImpl<MCFixup> &Fixups, 58 const MCSubtargetInfo &STI) const; 59 60 void expandAddTPRel(const MCInst &MI, raw_ostream &OS, 61 SmallVectorImpl<MCFixup> &Fixups, 62 const MCSubtargetInfo &STI) const; 63 64 /// TableGen'erated function for getting the binary encoding for an 65 /// instruction. 66 uint64_t getBinaryCodeForInstr(const MCInst &MI, 67 SmallVectorImpl<MCFixup> &Fixups, 68 const MCSubtargetInfo &STI) const; 69 70 /// Return binary encoding of operand. If the machine operand requires 71 /// relocation, record the relocation and return zero. 72 unsigned getMachineOpValue(const MCInst &MI, const MCOperand &MO, 73 SmallVectorImpl<MCFixup> &Fixups, 74 const MCSubtargetInfo &STI) const; 75 76 unsigned getImmOpValueAsr1(const MCInst &MI, unsigned OpNo, 77 SmallVectorImpl<MCFixup> &Fixups, 78 const MCSubtargetInfo &STI) const; 79 80 unsigned getImmOpValue(const MCInst &MI, unsigned OpNo, 81 SmallVectorImpl<MCFixup> &Fixups, 82 const MCSubtargetInfo &STI) const; 83 84 unsigned getVMaskReg(const MCInst &MI, unsigned OpNo, 85 SmallVectorImpl<MCFixup> &Fixups, 86 const MCSubtargetInfo &STI) const; 87 88 private: 89 FeatureBitset computeAvailableFeatures(const FeatureBitset &FB) const; 90 void 91 verifyInstructionPredicates(const MCInst &MI, 92 const FeatureBitset &AvailableFeatures) const; 93 }; 94 } // end anonymous namespace 95 96 MCCodeEmitter *llvm::createRISCVMCCodeEmitter(const MCInstrInfo &MCII, 97 MCContext &Ctx) { 98 return new RISCVMCCodeEmitter(Ctx, MCII); 99 } 100 101 // Expand PseudoCALL(Reg), PseudoTAIL and PseudoJump to AUIPC and JALR with 102 // relocation types. We expand those pseudo-instructions while encoding them, 103 // meaning AUIPC and JALR won't go through RISCV MC to MC compressed 104 // instruction transformation. This is acceptable because AUIPC has no 16-bit 105 // form and C_JALR has no immediate operand field. We let linker relaxation 106 // deal with it. When linker relaxation is enabled, AUIPC and JALR have a 107 // chance to relax to JAL. 108 // If the C extension is enabled, JAL has a chance relax to C_JAL. 109 void RISCVMCCodeEmitter::expandFunctionCall(const MCInst &MI, raw_ostream &OS, 110 SmallVectorImpl<MCFixup> &Fixups, 111 const MCSubtargetInfo &STI) const { 112 MCInst TmpInst; 113 MCOperand Func; 114 MCRegister Ra; 115 if (MI.getOpcode() == RISCV::PseudoTAIL) { 116 Func = MI.getOperand(0); 117 Ra = RISCV::X6; 118 } else if (MI.getOpcode() == RISCV::PseudoCALLReg) { 119 Func = MI.getOperand(1); 120 Ra = MI.getOperand(0).getReg(); 121 } else if (MI.getOpcode() == RISCV::PseudoCALL) { 122 Func = MI.getOperand(0); 123 Ra = RISCV::X1; 124 } else if (MI.getOpcode() == RISCV::PseudoJump) { 125 Func = MI.getOperand(1); 126 Ra = MI.getOperand(0).getReg(); 127 } 128 uint32_t Binary; 129 130 assert(Func.isExpr() && "Expected expression"); 131 132 const MCExpr *CallExpr = Func.getExpr(); 133 134 // Emit AUIPC Ra, Func with R_RISCV_CALL relocation type. 135 TmpInst = MCInstBuilder(RISCV::AUIPC).addReg(Ra).addExpr(CallExpr); 136 Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI); 137 support::endian::write(OS, Binary, support::little); 138 139 if (MI.getOpcode() == RISCV::PseudoTAIL || 140 MI.getOpcode() == RISCV::PseudoJump) 141 // Emit JALR X0, Ra, 0 142 TmpInst = MCInstBuilder(RISCV::JALR).addReg(RISCV::X0).addReg(Ra).addImm(0); 143 else 144 // Emit JALR Ra, Ra, 0 145 TmpInst = MCInstBuilder(RISCV::JALR).addReg(Ra).addReg(Ra).addImm(0); 146 Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI); 147 support::endian::write(OS, Binary, support::little); 148 } 149 150 // Expand PseudoAddTPRel to a simple ADD with the correct relocation. 151 void RISCVMCCodeEmitter::expandAddTPRel(const MCInst &MI, raw_ostream &OS, 152 SmallVectorImpl<MCFixup> &Fixups, 153 const MCSubtargetInfo &STI) const { 154 MCOperand DestReg = MI.getOperand(0); 155 MCOperand SrcReg = MI.getOperand(1); 156 MCOperand TPReg = MI.getOperand(2); 157 assert(TPReg.isReg() && TPReg.getReg() == RISCV::X4 && 158 "Expected thread pointer as second input to TP-relative add"); 159 160 MCOperand SrcSymbol = MI.getOperand(3); 161 assert(SrcSymbol.isExpr() && 162 "Expected expression as third input to TP-relative add"); 163 164 const RISCVMCExpr *Expr = dyn_cast<RISCVMCExpr>(SrcSymbol.getExpr()); 165 assert(Expr && Expr->getKind() == RISCVMCExpr::VK_RISCV_TPREL_ADD && 166 "Expected tprel_add relocation on TP-relative symbol"); 167 168 // Emit the correct tprel_add relocation for the symbol. 169 Fixups.push_back(MCFixup::create( 170 0, Expr, MCFixupKind(RISCV::fixup_riscv_tprel_add), MI.getLoc())); 171 172 // Emit fixup_riscv_relax for tprel_add where the relax feature is enabled. 173 if (STI.getFeatureBits()[RISCV::FeatureRelax]) { 174 const MCConstantExpr *Dummy = MCConstantExpr::create(0, Ctx); 175 Fixups.push_back(MCFixup::create( 176 0, Dummy, MCFixupKind(RISCV::fixup_riscv_relax), MI.getLoc())); 177 } 178 179 // Emit a normal ADD instruction with the given operands. 180 MCInst TmpInst = MCInstBuilder(RISCV::ADD) 181 .addOperand(DestReg) 182 .addOperand(SrcReg) 183 .addOperand(TPReg); 184 uint32_t Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI); 185 support::endian::write(OS, Binary, support::little); 186 } 187 188 void RISCVMCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS, 189 SmallVectorImpl<MCFixup> &Fixups, 190 const MCSubtargetInfo &STI) const { 191 verifyInstructionPredicates(MI, 192 computeAvailableFeatures(STI.getFeatureBits())); 193 194 const MCInstrDesc &Desc = MCII.get(MI.getOpcode()); 195 // Get byte count of instruction. 196 unsigned Size = Desc.getSize(); 197 198 // RISCVInstrInfo::getInstSizeInBytes expects that the total size of the 199 // expanded instructions for each pseudo is correct in the Size field of the 200 // tablegen definition for the pseudo. 201 if (MI.getOpcode() == RISCV::PseudoCALLReg || 202 MI.getOpcode() == RISCV::PseudoCALL || 203 MI.getOpcode() == RISCV::PseudoTAIL || 204 MI.getOpcode() == RISCV::PseudoJump) { 205 expandFunctionCall(MI, OS, Fixups, STI); 206 MCNumEmitted += 2; 207 return; 208 } 209 210 if (MI.getOpcode() == RISCV::PseudoAddTPRel) { 211 expandAddTPRel(MI, OS, Fixups, STI); 212 MCNumEmitted += 1; 213 return; 214 } 215 216 switch (Size) { 217 default: 218 llvm_unreachable("Unhandled encodeInstruction length!"); 219 case 2: { 220 uint16_t Bits = getBinaryCodeForInstr(MI, Fixups, STI); 221 support::endian::write<uint16_t>(OS, Bits, support::little); 222 break; 223 } 224 case 4: { 225 uint32_t Bits = getBinaryCodeForInstr(MI, Fixups, STI); 226 support::endian::write(OS, Bits, support::little); 227 break; 228 } 229 } 230 231 ++MCNumEmitted; // Keep track of the # of mi's emitted. 232 } 233 234 unsigned 235 RISCVMCCodeEmitter::getMachineOpValue(const MCInst &MI, const MCOperand &MO, 236 SmallVectorImpl<MCFixup> &Fixups, 237 const MCSubtargetInfo &STI) const { 238 239 if (MO.isReg()) 240 return Ctx.getRegisterInfo()->getEncodingValue(MO.getReg()); 241 242 if (MO.isImm()) 243 return static_cast<unsigned>(MO.getImm()); 244 245 llvm_unreachable("Unhandled expression!"); 246 return 0; 247 } 248 249 unsigned 250 RISCVMCCodeEmitter::getImmOpValueAsr1(const MCInst &MI, unsigned OpNo, 251 SmallVectorImpl<MCFixup> &Fixups, 252 const MCSubtargetInfo &STI) const { 253 const MCOperand &MO = MI.getOperand(OpNo); 254 255 if (MO.isImm()) { 256 unsigned Res = MO.getImm(); 257 assert((Res & 1) == 0 && "LSB is non-zero"); 258 return Res >> 1; 259 } 260 261 return getImmOpValue(MI, OpNo, Fixups, STI); 262 } 263 264 unsigned RISCVMCCodeEmitter::getImmOpValue(const MCInst &MI, unsigned OpNo, 265 SmallVectorImpl<MCFixup> &Fixups, 266 const MCSubtargetInfo &STI) const { 267 bool EnableRelax = STI.getFeatureBits()[RISCV::FeatureRelax]; 268 const MCOperand &MO = MI.getOperand(OpNo); 269 270 MCInstrDesc const &Desc = MCII.get(MI.getOpcode()); 271 unsigned MIFrm = RISCVII::getFormat(Desc.TSFlags); 272 273 // If the destination is an immediate, there is nothing to do. 274 if (MO.isImm()) 275 return MO.getImm(); 276 277 assert(MO.isExpr() && 278 "getImmOpValue expects only expressions or immediates"); 279 const MCExpr *Expr = MO.getExpr(); 280 MCExpr::ExprKind Kind = Expr->getKind(); 281 RISCV::Fixups FixupKind = RISCV::fixup_riscv_invalid; 282 bool RelaxCandidate = false; 283 if (Kind == MCExpr::Target) { 284 const RISCVMCExpr *RVExpr = cast<RISCVMCExpr>(Expr); 285 286 switch (RVExpr->getKind()) { 287 case RISCVMCExpr::VK_RISCV_None: 288 case RISCVMCExpr::VK_RISCV_Invalid: 289 case RISCVMCExpr::VK_RISCV_32_PCREL: 290 llvm_unreachable("Unhandled fixup kind!"); 291 case RISCVMCExpr::VK_RISCV_TPREL_ADD: 292 // tprel_add is only used to indicate that a relocation should be emitted 293 // for an add instruction used in TP-relative addressing. It should not be 294 // expanded as if representing an actual instruction operand and so to 295 // encounter it here is an error. 296 llvm_unreachable( 297 "VK_RISCV_TPREL_ADD should not represent an instruction operand"); 298 case RISCVMCExpr::VK_RISCV_LO: 299 if (MIFrm == RISCVII::InstFormatI) 300 FixupKind = RISCV::fixup_riscv_lo12_i; 301 else if (MIFrm == RISCVII::InstFormatS) 302 FixupKind = RISCV::fixup_riscv_lo12_s; 303 else 304 llvm_unreachable("VK_RISCV_LO used with unexpected instruction format"); 305 RelaxCandidate = true; 306 break; 307 case RISCVMCExpr::VK_RISCV_HI: 308 FixupKind = RISCV::fixup_riscv_hi20; 309 RelaxCandidate = true; 310 break; 311 case RISCVMCExpr::VK_RISCV_PCREL_LO: 312 if (MIFrm == RISCVII::InstFormatI) 313 FixupKind = RISCV::fixup_riscv_pcrel_lo12_i; 314 else if (MIFrm == RISCVII::InstFormatS) 315 FixupKind = RISCV::fixup_riscv_pcrel_lo12_s; 316 else 317 llvm_unreachable( 318 "VK_RISCV_PCREL_LO used with unexpected instruction format"); 319 RelaxCandidate = true; 320 break; 321 case RISCVMCExpr::VK_RISCV_PCREL_HI: 322 FixupKind = RISCV::fixup_riscv_pcrel_hi20; 323 RelaxCandidate = true; 324 break; 325 case RISCVMCExpr::VK_RISCV_GOT_HI: 326 FixupKind = RISCV::fixup_riscv_got_hi20; 327 break; 328 case RISCVMCExpr::VK_RISCV_TPREL_LO: 329 if (MIFrm == RISCVII::InstFormatI) 330 FixupKind = RISCV::fixup_riscv_tprel_lo12_i; 331 else if (MIFrm == RISCVII::InstFormatS) 332 FixupKind = RISCV::fixup_riscv_tprel_lo12_s; 333 else 334 llvm_unreachable( 335 "VK_RISCV_TPREL_LO used with unexpected instruction format"); 336 RelaxCandidate = true; 337 break; 338 case RISCVMCExpr::VK_RISCV_TPREL_HI: 339 FixupKind = RISCV::fixup_riscv_tprel_hi20; 340 RelaxCandidate = true; 341 break; 342 case RISCVMCExpr::VK_RISCV_TLS_GOT_HI: 343 FixupKind = RISCV::fixup_riscv_tls_got_hi20; 344 break; 345 case RISCVMCExpr::VK_RISCV_TLS_GD_HI: 346 FixupKind = RISCV::fixup_riscv_tls_gd_hi20; 347 break; 348 case RISCVMCExpr::VK_RISCV_CALL: 349 FixupKind = RISCV::fixup_riscv_call; 350 RelaxCandidate = true; 351 break; 352 case RISCVMCExpr::VK_RISCV_CALL_PLT: 353 FixupKind = RISCV::fixup_riscv_call_plt; 354 RelaxCandidate = true; 355 break; 356 } 357 } else if (Kind == MCExpr::SymbolRef && 358 cast<MCSymbolRefExpr>(Expr)->getKind() == MCSymbolRefExpr::VK_None) { 359 if (MIFrm == RISCVII::InstFormatJ) { 360 FixupKind = RISCV::fixup_riscv_jal; 361 } else if (MIFrm == RISCVII::InstFormatB) { 362 FixupKind = RISCV::fixup_riscv_branch; 363 } else if (MIFrm == RISCVII::InstFormatCJ) { 364 FixupKind = RISCV::fixup_riscv_rvc_jump; 365 } else if (MIFrm == RISCVII::InstFormatCB) { 366 FixupKind = RISCV::fixup_riscv_rvc_branch; 367 } 368 } 369 370 assert(FixupKind != RISCV::fixup_riscv_invalid && "Unhandled expression!"); 371 372 Fixups.push_back( 373 MCFixup::create(0, Expr, MCFixupKind(FixupKind), MI.getLoc())); 374 ++MCNumFixups; 375 376 // Ensure an R_RISCV_RELAX relocation will be emitted if linker relaxation is 377 // enabled and the current fixup will result in a relocation that may be 378 // relaxed. 379 if (EnableRelax && RelaxCandidate) { 380 const MCConstantExpr *Dummy = MCConstantExpr::create(0, Ctx); 381 Fixups.push_back( 382 MCFixup::create(0, Dummy, MCFixupKind(RISCV::fixup_riscv_relax), 383 MI.getLoc())); 384 ++MCNumFixups; 385 } 386 387 return 0; 388 } 389 390 unsigned RISCVMCCodeEmitter::getVMaskReg(const MCInst &MI, unsigned OpNo, 391 SmallVectorImpl<MCFixup> &Fixups, 392 const MCSubtargetInfo &STI) const { 393 MCOperand MO = MI.getOperand(OpNo); 394 assert(MO.isReg() && "Expected a register."); 395 396 switch (MO.getReg()) { 397 default: 398 llvm_unreachable("Invalid mask register."); 399 case RISCV::V0: 400 return 0; 401 case RISCV::NoRegister: 402 return 1; 403 } 404 } 405 406 #define ENABLE_INSTR_PREDICATE_VERIFIER 407 #include "RISCVGenMCCodeEmitter.inc" 408