1 //===-- RISCVMCCodeEmitter.cpp - Convert RISCV code to machine code -------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements the RISCVMCCodeEmitter class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "MCTargetDesc/RISCVFixupKinds.h"
14 #include "MCTargetDesc/RISCVMCExpr.h"
15 #include "MCTargetDesc/RISCVMCTargetDesc.h"
16 #include "Utils/RISCVBaseInfo.h"
17 #include "llvm/ADT/Statistic.h"
18 #include "llvm/CodeGen/Register.h"
19 #include "llvm/MC/MCAsmInfo.h"
20 #include "llvm/MC/MCCodeEmitter.h"
21 #include "llvm/MC/MCContext.h"
22 #include "llvm/MC/MCExpr.h"
23 #include "llvm/MC/MCInst.h"
24 #include "llvm/MC/MCInstBuilder.h"
25 #include "llvm/MC/MCInstrInfo.h"
26 #include "llvm/MC/MCRegisterInfo.h"
27 #include "llvm/MC/MCSymbol.h"
28 #include "llvm/Support/Casting.h"
29 #include "llvm/Support/EndianStream.h"
30 #include "llvm/Support/raw_ostream.h"
31 
32 using namespace llvm;
33 
34 #define DEBUG_TYPE "mccodeemitter"
35 
36 STATISTIC(MCNumEmitted, "Number of MC instructions emitted");
37 STATISTIC(MCNumFixups, "Number of MC fixups created");
38 
39 namespace {
40 class RISCVMCCodeEmitter : public MCCodeEmitter {
41   RISCVMCCodeEmitter(const RISCVMCCodeEmitter &) = delete;
42   void operator=(const RISCVMCCodeEmitter &) = delete;
43   MCContext &Ctx;
44   MCInstrInfo const &MCII;
45 
46 public:
47   RISCVMCCodeEmitter(MCContext &ctx, MCInstrInfo const &MCII)
48       : Ctx(ctx), MCII(MCII) {}
49 
50   ~RISCVMCCodeEmitter() override {}
51 
52   void encodeInstruction(const MCInst &MI, raw_ostream &OS,
53                          SmallVectorImpl<MCFixup> &Fixups,
54                          const MCSubtargetInfo &STI) const override;
55 
56   void expandFunctionCall(const MCInst &MI, raw_ostream &OS,
57                           SmallVectorImpl<MCFixup> &Fixups,
58                           const MCSubtargetInfo &STI) const;
59 
60   void expandAddTPRel(const MCInst &MI, raw_ostream &OS,
61                       SmallVectorImpl<MCFixup> &Fixups,
62                       const MCSubtargetInfo &STI) const;
63 
64   /// TableGen'erated function for getting the binary encoding for an
65   /// instruction.
66   uint64_t getBinaryCodeForInstr(const MCInst &MI,
67                                  SmallVectorImpl<MCFixup> &Fixups,
68                                  const MCSubtargetInfo &STI) const;
69 
70   /// Return binary encoding of operand. If the machine operand requires
71   /// relocation, record the relocation and return zero.
72   unsigned getMachineOpValue(const MCInst &MI, const MCOperand &MO,
73                              SmallVectorImpl<MCFixup> &Fixups,
74                              const MCSubtargetInfo &STI) const;
75 
76   unsigned getImmOpValueAsr1(const MCInst &MI, unsigned OpNo,
77                              SmallVectorImpl<MCFixup> &Fixups,
78                              const MCSubtargetInfo &STI) const;
79 
80   unsigned getImmOpValue(const MCInst &MI, unsigned OpNo,
81                          SmallVectorImpl<MCFixup> &Fixups,
82                          const MCSubtargetInfo &STI) const;
83 };
84 } // end anonymous namespace
85 
86 MCCodeEmitter *llvm::createRISCVMCCodeEmitter(const MCInstrInfo &MCII,
87                                               const MCRegisterInfo &MRI,
88                                               MCContext &Ctx) {
89   return new RISCVMCCodeEmitter(Ctx, MCII);
90 }
91 
92 // Expand PseudoCALL(Reg) and PseudoTAIL to AUIPC and JALR with relocation
93 // types. We expand PseudoCALL(Reg) and PseudoTAIL while encoding, meaning AUIPC
94 // and JALR won't go through RISCV MC to MC compressed instruction
95 // transformation. This is acceptable because AUIPC has no 16-bit form and
96 // C_JALR have no immediate operand field.  We let linker relaxation deal with
97 // it. When linker relaxation enabled, AUIPC and JALR have chance relax to JAL.
98 // If C extension is enabled, JAL has chance relax to C_JAL.
99 void RISCVMCCodeEmitter::expandFunctionCall(const MCInst &MI, raw_ostream &OS,
100                                             SmallVectorImpl<MCFixup> &Fixups,
101                                             const MCSubtargetInfo &STI) const {
102   MCInst TmpInst;
103   MCOperand Func;
104   Register Ra;
105   if (MI.getOpcode() == RISCV::PseudoTAIL) {
106     Func = MI.getOperand(0);
107     Ra = RISCV::X6;
108   } else if (MI.getOpcode() == RISCV::PseudoCALLReg) {
109     Func = MI.getOperand(1);
110     Ra = MI.getOperand(0).getReg();
111   } else {
112     Func = MI.getOperand(0);
113     Ra = RISCV::X1;
114   }
115   uint32_t Binary;
116 
117   assert(Func.isExpr() && "Expected expression");
118 
119   const MCExpr *CallExpr = Func.getExpr();
120 
121   // Emit AUIPC Ra, Func with R_RISCV_CALL relocation type.
122   TmpInst = MCInstBuilder(RISCV::AUIPC)
123                 .addReg(Ra)
124                 .addOperand(MCOperand::createExpr(CallExpr));
125   Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI);
126   support::endian::write(OS, Binary, support::little);
127 
128   if (MI.getOpcode() == RISCV::PseudoTAIL)
129     // Emit JALR X0, X6, 0
130     TmpInst = MCInstBuilder(RISCV::JALR).addReg(RISCV::X0).addReg(Ra).addImm(0);
131   else
132     // Emit JALR Ra, Ra, 0
133     TmpInst = MCInstBuilder(RISCV::JALR).addReg(Ra).addReg(Ra).addImm(0);
134   Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI);
135   support::endian::write(OS, Binary, support::little);
136 }
137 
138 // Expand PseudoAddTPRel to a simple ADD with the correct relocation.
139 void RISCVMCCodeEmitter::expandAddTPRel(const MCInst &MI, raw_ostream &OS,
140                                         SmallVectorImpl<MCFixup> &Fixups,
141                                         const MCSubtargetInfo &STI) const {
142   MCOperand DestReg = MI.getOperand(0);
143   MCOperand SrcReg = MI.getOperand(1);
144   MCOperand TPReg = MI.getOperand(2);
145   assert(TPReg.isReg() && TPReg.getReg() == RISCV::X4 &&
146          "Expected thread pointer as second input to TP-relative add");
147 
148   MCOperand SrcSymbol = MI.getOperand(3);
149   assert(SrcSymbol.isExpr() &&
150          "Expected expression as third input to TP-relative add");
151 
152   const RISCVMCExpr *Expr = dyn_cast<RISCVMCExpr>(SrcSymbol.getExpr());
153   assert(Expr && Expr->getKind() == RISCVMCExpr::VK_RISCV_TPREL_ADD &&
154          "Expected tprel_add relocation on TP-relative symbol");
155 
156   // Emit the correct tprel_add relocation for the symbol.
157   Fixups.push_back(MCFixup::create(
158       0, Expr, MCFixupKind(RISCV::fixup_riscv_tprel_add), MI.getLoc()));
159 
160   // Emit fixup_riscv_relax for tprel_add where the relax feature is enabled.
161   if (STI.getFeatureBits()[RISCV::FeatureRelax]) {
162     const MCConstantExpr *Dummy = MCConstantExpr::create(0, Ctx);
163     Fixups.push_back(MCFixup::create(
164         0, Dummy, MCFixupKind(RISCV::fixup_riscv_relax), MI.getLoc()));
165   }
166 
167   // Emit a normal ADD instruction with the given operands.
168   MCInst TmpInst = MCInstBuilder(RISCV::ADD)
169                        .addOperand(DestReg)
170                        .addOperand(SrcReg)
171                        .addOperand(TPReg);
172   uint32_t Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI);
173   support::endian::write(OS, Binary, support::little);
174 }
175 
176 void RISCVMCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,
177                                            SmallVectorImpl<MCFixup> &Fixups,
178                                            const MCSubtargetInfo &STI) const {
179   const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
180   // Get byte count of instruction.
181   unsigned Size = Desc.getSize();
182 
183   if (MI.getOpcode() == RISCV::PseudoCALLReg ||
184       MI.getOpcode() == RISCV::PseudoCALL ||
185       MI.getOpcode() == RISCV::PseudoTAIL) {
186     expandFunctionCall(MI, OS, Fixups, STI);
187     MCNumEmitted += 2;
188     return;
189   }
190 
191   if (MI.getOpcode() == RISCV::PseudoAddTPRel) {
192     expandAddTPRel(MI, OS, Fixups, STI);
193     MCNumEmitted += 1;
194     return;
195   }
196 
197   switch (Size) {
198   default:
199     llvm_unreachable("Unhandled encodeInstruction length!");
200   case 2: {
201     uint16_t Bits = getBinaryCodeForInstr(MI, Fixups, STI);
202     support::endian::write<uint16_t>(OS, Bits, support::little);
203     break;
204   }
205   case 4: {
206     uint32_t Bits = getBinaryCodeForInstr(MI, Fixups, STI);
207     support::endian::write(OS, Bits, support::little);
208     break;
209   }
210   }
211 
212   ++MCNumEmitted; // Keep track of the # of mi's emitted.
213 }
214 
215 unsigned
216 RISCVMCCodeEmitter::getMachineOpValue(const MCInst &MI, const MCOperand &MO,
217                                       SmallVectorImpl<MCFixup> &Fixups,
218                                       const MCSubtargetInfo &STI) const {
219 
220   if (MO.isReg())
221     return Ctx.getRegisterInfo()->getEncodingValue(MO.getReg());
222 
223   if (MO.isImm())
224     return static_cast<unsigned>(MO.getImm());
225 
226   llvm_unreachable("Unhandled expression!");
227   return 0;
228 }
229 
230 unsigned
231 RISCVMCCodeEmitter::getImmOpValueAsr1(const MCInst &MI, unsigned OpNo,
232                                       SmallVectorImpl<MCFixup> &Fixups,
233                                       const MCSubtargetInfo &STI) const {
234   const MCOperand &MO = MI.getOperand(OpNo);
235 
236   if (MO.isImm()) {
237     unsigned Res = MO.getImm();
238     assert((Res & 1) == 0 && "LSB is non-zero");
239     return Res >> 1;
240   }
241 
242   return getImmOpValue(MI, OpNo, Fixups, STI);
243 }
244 
245 unsigned RISCVMCCodeEmitter::getImmOpValue(const MCInst &MI, unsigned OpNo,
246                                            SmallVectorImpl<MCFixup> &Fixups,
247                                            const MCSubtargetInfo &STI) const {
248   bool EnableRelax = STI.getFeatureBits()[RISCV::FeatureRelax];
249   const MCOperand &MO = MI.getOperand(OpNo);
250 
251   MCInstrDesc const &Desc = MCII.get(MI.getOpcode());
252   unsigned MIFrm = Desc.TSFlags & RISCVII::InstFormatMask;
253 
254   // If the destination is an immediate, there is nothing to do.
255   if (MO.isImm())
256     return MO.getImm();
257 
258   assert(MO.isExpr() &&
259          "getImmOpValue expects only expressions or immediates");
260   const MCExpr *Expr = MO.getExpr();
261   MCExpr::ExprKind Kind = Expr->getKind();
262   RISCV::Fixups FixupKind = RISCV::fixup_riscv_invalid;
263   bool RelaxCandidate = false;
264   if (Kind == MCExpr::Target) {
265     const RISCVMCExpr *RVExpr = cast<RISCVMCExpr>(Expr);
266 
267     switch (RVExpr->getKind()) {
268     case RISCVMCExpr::VK_RISCV_None:
269     case RISCVMCExpr::VK_RISCV_Invalid:
270       llvm_unreachable("Unhandled fixup kind!");
271     case RISCVMCExpr::VK_RISCV_TPREL_ADD:
272       // tprel_add is only used to indicate that a relocation should be emitted
273       // for an add instruction used in TP-relative addressing. It should not be
274       // expanded as if representing an actual instruction operand and so to
275       // encounter it here is an error.
276       llvm_unreachable(
277           "VK_RISCV_TPREL_ADD should not represent an instruction operand");
278     case RISCVMCExpr::VK_RISCV_LO:
279       if (MIFrm == RISCVII::InstFormatI)
280         FixupKind = RISCV::fixup_riscv_lo12_i;
281       else if (MIFrm == RISCVII::InstFormatS)
282         FixupKind = RISCV::fixup_riscv_lo12_s;
283       else
284         llvm_unreachable("VK_RISCV_LO used with unexpected instruction format");
285       RelaxCandidate = true;
286       break;
287     case RISCVMCExpr::VK_RISCV_HI:
288       FixupKind = RISCV::fixup_riscv_hi20;
289       RelaxCandidate = true;
290       break;
291     case RISCVMCExpr::VK_RISCV_PCREL_LO:
292       if (MIFrm == RISCVII::InstFormatI)
293         FixupKind = RISCV::fixup_riscv_pcrel_lo12_i;
294       else if (MIFrm == RISCVII::InstFormatS)
295         FixupKind = RISCV::fixup_riscv_pcrel_lo12_s;
296       else
297         llvm_unreachable(
298             "VK_RISCV_PCREL_LO used with unexpected instruction format");
299       RelaxCandidate = true;
300       break;
301     case RISCVMCExpr::VK_RISCV_PCREL_HI:
302       FixupKind = RISCV::fixup_riscv_pcrel_hi20;
303       RelaxCandidate = true;
304       break;
305     case RISCVMCExpr::VK_RISCV_GOT_HI:
306       FixupKind = RISCV::fixup_riscv_got_hi20;
307       break;
308     case RISCVMCExpr::VK_RISCV_TPREL_LO:
309       if (MIFrm == RISCVII::InstFormatI)
310         FixupKind = RISCV::fixup_riscv_tprel_lo12_i;
311       else if (MIFrm == RISCVII::InstFormatS)
312         FixupKind = RISCV::fixup_riscv_tprel_lo12_s;
313       else
314         llvm_unreachable(
315             "VK_RISCV_TPREL_LO used with unexpected instruction format");
316       RelaxCandidate = true;
317       break;
318     case RISCVMCExpr::VK_RISCV_TPREL_HI:
319       FixupKind = RISCV::fixup_riscv_tprel_hi20;
320       RelaxCandidate = true;
321       break;
322     case RISCVMCExpr::VK_RISCV_TLS_GOT_HI:
323       FixupKind = RISCV::fixup_riscv_tls_got_hi20;
324       break;
325     case RISCVMCExpr::VK_RISCV_TLS_GD_HI:
326       FixupKind = RISCV::fixup_riscv_tls_gd_hi20;
327       break;
328     case RISCVMCExpr::VK_RISCV_CALL:
329       FixupKind = RISCV::fixup_riscv_call;
330       RelaxCandidate = true;
331       break;
332     case RISCVMCExpr::VK_RISCV_CALL_PLT:
333       FixupKind = RISCV::fixup_riscv_call_plt;
334       RelaxCandidate = true;
335       break;
336     }
337   } else if (Kind == MCExpr::SymbolRef &&
338              cast<MCSymbolRefExpr>(Expr)->getKind() == MCSymbolRefExpr::VK_None) {
339     if (Desc.getOpcode() == RISCV::JAL) {
340       FixupKind = RISCV::fixup_riscv_jal;
341     } else if (MIFrm == RISCVII::InstFormatB) {
342       FixupKind = RISCV::fixup_riscv_branch;
343     } else if (MIFrm == RISCVII::InstFormatCJ) {
344       FixupKind = RISCV::fixup_riscv_rvc_jump;
345     } else if (MIFrm == RISCVII::InstFormatCB) {
346       FixupKind = RISCV::fixup_riscv_rvc_branch;
347     }
348   }
349 
350   assert(FixupKind != RISCV::fixup_riscv_invalid && "Unhandled expression!");
351 
352   Fixups.push_back(
353       MCFixup::create(0, Expr, MCFixupKind(FixupKind), MI.getLoc()));
354   ++MCNumFixups;
355 
356   // Ensure an R_RISCV_RELAX relocation will be emitted if linker relaxation is
357   // enabled and the current fixup will result in a relocation that may be
358   // relaxed.
359   if (EnableRelax && RelaxCandidate) {
360     const MCConstantExpr *Dummy = MCConstantExpr::create(0, Ctx);
361     Fixups.push_back(
362     MCFixup::create(0, Dummy, MCFixupKind(RISCV::fixup_riscv_relax),
363                     MI.getLoc()));
364     ++MCNumFixups;
365   }
366 
367   return 0;
368 }
369 
370 #include "RISCVGenMCCodeEmitter.inc"
371