1 //===-- RISCVMCCodeEmitter.cpp - Convert RISCV code to machine code -------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file implements the RISCVMCCodeEmitter class. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "MCTargetDesc/RISCVBaseInfo.h" 14 #include "MCTargetDesc/RISCVFixupKinds.h" 15 #include "MCTargetDesc/RISCVMCExpr.h" 16 #include "MCTargetDesc/RISCVMCTargetDesc.h" 17 #include "llvm/ADT/Statistic.h" 18 #include "llvm/MC/MCAsmInfo.h" 19 #include "llvm/MC/MCCodeEmitter.h" 20 #include "llvm/MC/MCContext.h" 21 #include "llvm/MC/MCExpr.h" 22 #include "llvm/MC/MCInst.h" 23 #include "llvm/MC/MCInstBuilder.h" 24 #include "llvm/MC/MCInstrInfo.h" 25 #include "llvm/MC/MCRegisterInfo.h" 26 #include "llvm/MC/MCSubtargetInfo.h" 27 #include "llvm/MC/MCSymbol.h" 28 #include "llvm/Support/Casting.h" 29 #include "llvm/Support/EndianStream.h" 30 #include "llvm/Support/raw_ostream.h" 31 32 using namespace llvm; 33 34 #define DEBUG_TYPE "mccodeemitter" 35 36 STATISTIC(MCNumEmitted, "Number of MC instructions emitted"); 37 STATISTIC(MCNumFixups, "Number of MC fixups created"); 38 39 namespace { 40 class RISCVMCCodeEmitter : public MCCodeEmitter { 41 RISCVMCCodeEmitter(const RISCVMCCodeEmitter &) = delete; 42 void operator=(const RISCVMCCodeEmitter &) = delete; 43 MCContext &Ctx; 44 MCInstrInfo const &MCII; 45 46 public: 47 RISCVMCCodeEmitter(MCContext &ctx, MCInstrInfo const &MCII) 48 : Ctx(ctx), MCII(MCII) {} 49 50 ~RISCVMCCodeEmitter() override = default; 51 52 void encodeInstruction(const MCInst &MI, raw_ostream &OS, 53 SmallVectorImpl<MCFixup> &Fixups, 54 const MCSubtargetInfo &STI) const override; 55 56 void expandFunctionCall(const MCInst &MI, raw_ostream &OS, 57 SmallVectorImpl<MCFixup> &Fixups, 58 const MCSubtargetInfo &STI) const; 59 60 void expandAddTPRel(const MCInst &MI, raw_ostream &OS, 61 SmallVectorImpl<MCFixup> &Fixups, 62 const MCSubtargetInfo &STI) const; 63 64 /// TableGen'erated function for getting the binary encoding for an 65 /// instruction. 66 uint64_t getBinaryCodeForInstr(const MCInst &MI, 67 SmallVectorImpl<MCFixup> &Fixups, 68 const MCSubtargetInfo &STI) const; 69 70 /// Return binary encoding of operand. If the machine operand requires 71 /// relocation, record the relocation and return zero. 72 unsigned getMachineOpValue(const MCInst &MI, const MCOperand &MO, 73 SmallVectorImpl<MCFixup> &Fixups, 74 const MCSubtargetInfo &STI) const; 75 76 unsigned getImmOpValueAsr1(const MCInst &MI, unsigned OpNo, 77 SmallVectorImpl<MCFixup> &Fixups, 78 const MCSubtargetInfo &STI) const; 79 80 unsigned getImmOpValue(const MCInst &MI, unsigned OpNo, 81 SmallVectorImpl<MCFixup> &Fixups, 82 const MCSubtargetInfo &STI) const; 83 84 unsigned getVMaskReg(const MCInst &MI, unsigned OpNo, 85 SmallVectorImpl<MCFixup> &Fixups, 86 const MCSubtargetInfo &STI) const; 87 88 private: 89 FeatureBitset computeAvailableFeatures(const FeatureBitset &FB) const; 90 void 91 verifyInstructionPredicates(const MCInst &MI, 92 const FeatureBitset &AvailableFeatures) const; 93 }; 94 } // end anonymous namespace 95 96 MCCodeEmitter *llvm::createRISCVMCCodeEmitter(const MCInstrInfo &MCII, 97 const MCRegisterInfo &MRI, 98 MCContext &Ctx) { 99 return new RISCVMCCodeEmitter(Ctx, MCII); 100 } 101 102 // Expand PseudoCALL(Reg), PseudoTAIL and PseudoJump to AUIPC and JALR with 103 // relocation types. We expand those pseudo-instructions while encoding them, 104 // meaning AUIPC and JALR won't go through RISCV MC to MC compressed 105 // instruction transformation. This is acceptable because AUIPC has no 16-bit 106 // form and C_JALR has no immediate operand field. We let linker relaxation 107 // deal with it. When linker relaxation is enabled, AUIPC and JALR have a 108 // chance to relax to JAL. 109 // If the C extension is enabled, JAL has a chance relax to C_JAL. 110 void RISCVMCCodeEmitter::expandFunctionCall(const MCInst &MI, raw_ostream &OS, 111 SmallVectorImpl<MCFixup> &Fixups, 112 const MCSubtargetInfo &STI) const { 113 MCInst TmpInst; 114 MCOperand Func; 115 MCRegister Ra; 116 if (MI.getOpcode() == RISCV::PseudoTAIL) { 117 Func = MI.getOperand(0); 118 Ra = RISCV::X6; 119 } else if (MI.getOpcode() == RISCV::PseudoCALLReg) { 120 Func = MI.getOperand(1); 121 Ra = MI.getOperand(0).getReg(); 122 } else if (MI.getOpcode() == RISCV::PseudoCALL) { 123 Func = MI.getOperand(0); 124 Ra = RISCV::X1; 125 } else if (MI.getOpcode() == RISCV::PseudoJump) { 126 Func = MI.getOperand(1); 127 Ra = MI.getOperand(0).getReg(); 128 } 129 uint32_t Binary; 130 131 assert(Func.isExpr() && "Expected expression"); 132 133 const MCExpr *CallExpr = Func.getExpr(); 134 135 // Emit AUIPC Ra, Func with R_RISCV_CALL relocation type. 136 TmpInst = MCInstBuilder(RISCV::AUIPC) 137 .addReg(Ra) 138 .addOperand(MCOperand::createExpr(CallExpr)); 139 Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI); 140 support::endian::write(OS, Binary, support::little); 141 142 if (MI.getOpcode() == RISCV::PseudoTAIL || 143 MI.getOpcode() == RISCV::PseudoJump) 144 // Emit JALR X0, Ra, 0 145 TmpInst = MCInstBuilder(RISCV::JALR).addReg(RISCV::X0).addReg(Ra).addImm(0); 146 else 147 // Emit JALR Ra, Ra, 0 148 TmpInst = MCInstBuilder(RISCV::JALR).addReg(Ra).addReg(Ra).addImm(0); 149 Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI); 150 support::endian::write(OS, Binary, support::little); 151 } 152 153 // Expand PseudoAddTPRel to a simple ADD with the correct relocation. 154 void RISCVMCCodeEmitter::expandAddTPRel(const MCInst &MI, raw_ostream &OS, 155 SmallVectorImpl<MCFixup> &Fixups, 156 const MCSubtargetInfo &STI) const { 157 MCOperand DestReg = MI.getOperand(0); 158 MCOperand SrcReg = MI.getOperand(1); 159 MCOperand TPReg = MI.getOperand(2); 160 assert(TPReg.isReg() && TPReg.getReg() == RISCV::X4 && 161 "Expected thread pointer as second input to TP-relative add"); 162 163 MCOperand SrcSymbol = MI.getOperand(3); 164 assert(SrcSymbol.isExpr() && 165 "Expected expression as third input to TP-relative add"); 166 167 const RISCVMCExpr *Expr = dyn_cast<RISCVMCExpr>(SrcSymbol.getExpr()); 168 assert(Expr && Expr->getKind() == RISCVMCExpr::VK_RISCV_TPREL_ADD && 169 "Expected tprel_add relocation on TP-relative symbol"); 170 171 // Emit the correct tprel_add relocation for the symbol. 172 Fixups.push_back(MCFixup::create( 173 0, Expr, MCFixupKind(RISCV::fixup_riscv_tprel_add), MI.getLoc())); 174 175 // Emit fixup_riscv_relax for tprel_add where the relax feature is enabled. 176 if (STI.getFeatureBits()[RISCV::FeatureRelax]) { 177 const MCConstantExpr *Dummy = MCConstantExpr::create(0, Ctx); 178 Fixups.push_back(MCFixup::create( 179 0, Dummy, MCFixupKind(RISCV::fixup_riscv_relax), MI.getLoc())); 180 } 181 182 // Emit a normal ADD instruction with the given operands. 183 MCInst TmpInst = MCInstBuilder(RISCV::ADD) 184 .addOperand(DestReg) 185 .addOperand(SrcReg) 186 .addOperand(TPReg); 187 uint32_t Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI); 188 support::endian::write(OS, Binary, support::little); 189 } 190 191 void RISCVMCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS, 192 SmallVectorImpl<MCFixup> &Fixups, 193 const MCSubtargetInfo &STI) const { 194 verifyInstructionPredicates(MI, 195 computeAvailableFeatures(STI.getFeatureBits())); 196 197 const MCInstrDesc &Desc = MCII.get(MI.getOpcode()); 198 // Get byte count of instruction. 199 unsigned Size = Desc.getSize(); 200 201 // RISCVInstrInfo::getInstSizeInBytes expects that the total size of the 202 // expanded instructions for each pseudo is correct in the Size field of the 203 // tablegen definition for the pseudo. 204 if (MI.getOpcode() == RISCV::PseudoCALLReg || 205 MI.getOpcode() == RISCV::PseudoCALL || 206 MI.getOpcode() == RISCV::PseudoTAIL || 207 MI.getOpcode() == RISCV::PseudoJump) { 208 expandFunctionCall(MI, OS, Fixups, STI); 209 MCNumEmitted += 2; 210 return; 211 } 212 213 if (MI.getOpcode() == RISCV::PseudoAddTPRel) { 214 expandAddTPRel(MI, OS, Fixups, STI); 215 MCNumEmitted += 1; 216 return; 217 } 218 219 switch (Size) { 220 default: 221 llvm_unreachable("Unhandled encodeInstruction length!"); 222 case 2: { 223 uint16_t Bits = getBinaryCodeForInstr(MI, Fixups, STI); 224 support::endian::write<uint16_t>(OS, Bits, support::little); 225 break; 226 } 227 case 4: { 228 uint32_t Bits = getBinaryCodeForInstr(MI, Fixups, STI); 229 support::endian::write(OS, Bits, support::little); 230 break; 231 } 232 } 233 234 ++MCNumEmitted; // Keep track of the # of mi's emitted. 235 } 236 237 unsigned 238 RISCVMCCodeEmitter::getMachineOpValue(const MCInst &MI, const MCOperand &MO, 239 SmallVectorImpl<MCFixup> &Fixups, 240 const MCSubtargetInfo &STI) const { 241 242 if (MO.isReg()) 243 return Ctx.getRegisterInfo()->getEncodingValue(MO.getReg()); 244 245 if (MO.isImm()) 246 return static_cast<unsigned>(MO.getImm()); 247 248 llvm_unreachable("Unhandled expression!"); 249 return 0; 250 } 251 252 unsigned 253 RISCVMCCodeEmitter::getImmOpValueAsr1(const MCInst &MI, unsigned OpNo, 254 SmallVectorImpl<MCFixup> &Fixups, 255 const MCSubtargetInfo &STI) const { 256 const MCOperand &MO = MI.getOperand(OpNo); 257 258 if (MO.isImm()) { 259 unsigned Res = MO.getImm(); 260 assert((Res & 1) == 0 && "LSB is non-zero"); 261 return Res >> 1; 262 } 263 264 return getImmOpValue(MI, OpNo, Fixups, STI); 265 } 266 267 unsigned RISCVMCCodeEmitter::getImmOpValue(const MCInst &MI, unsigned OpNo, 268 SmallVectorImpl<MCFixup> &Fixups, 269 const MCSubtargetInfo &STI) const { 270 bool EnableRelax = STI.getFeatureBits()[RISCV::FeatureRelax]; 271 const MCOperand &MO = MI.getOperand(OpNo); 272 273 MCInstrDesc const &Desc = MCII.get(MI.getOpcode()); 274 unsigned MIFrm = RISCVII::getFormat(Desc.TSFlags); 275 276 // If the destination is an immediate, there is nothing to do. 277 if (MO.isImm()) 278 return MO.getImm(); 279 280 assert(MO.isExpr() && 281 "getImmOpValue expects only expressions or immediates"); 282 const MCExpr *Expr = MO.getExpr(); 283 MCExpr::ExprKind Kind = Expr->getKind(); 284 RISCV::Fixups FixupKind = RISCV::fixup_riscv_invalid; 285 bool RelaxCandidate = false; 286 if (Kind == MCExpr::Target) { 287 const RISCVMCExpr *RVExpr = cast<RISCVMCExpr>(Expr); 288 289 switch (RVExpr->getKind()) { 290 case RISCVMCExpr::VK_RISCV_None: 291 case RISCVMCExpr::VK_RISCV_Invalid: 292 case RISCVMCExpr::VK_RISCV_32_PCREL: 293 llvm_unreachable("Unhandled fixup kind!"); 294 case RISCVMCExpr::VK_RISCV_TPREL_ADD: 295 // tprel_add is only used to indicate that a relocation should be emitted 296 // for an add instruction used in TP-relative addressing. It should not be 297 // expanded as if representing an actual instruction operand and so to 298 // encounter it here is an error. 299 llvm_unreachable( 300 "VK_RISCV_TPREL_ADD should not represent an instruction operand"); 301 case RISCVMCExpr::VK_RISCV_LO: 302 if (MIFrm == RISCVII::InstFormatI) 303 FixupKind = RISCV::fixup_riscv_lo12_i; 304 else if (MIFrm == RISCVII::InstFormatS) 305 FixupKind = RISCV::fixup_riscv_lo12_s; 306 else 307 llvm_unreachable("VK_RISCV_LO used with unexpected instruction format"); 308 RelaxCandidate = true; 309 break; 310 case RISCVMCExpr::VK_RISCV_HI: 311 FixupKind = RISCV::fixup_riscv_hi20; 312 RelaxCandidate = true; 313 break; 314 case RISCVMCExpr::VK_RISCV_PCREL_LO: 315 if (MIFrm == RISCVII::InstFormatI) 316 FixupKind = RISCV::fixup_riscv_pcrel_lo12_i; 317 else if (MIFrm == RISCVII::InstFormatS) 318 FixupKind = RISCV::fixup_riscv_pcrel_lo12_s; 319 else 320 llvm_unreachable( 321 "VK_RISCV_PCREL_LO used with unexpected instruction format"); 322 RelaxCandidate = true; 323 break; 324 case RISCVMCExpr::VK_RISCV_PCREL_HI: 325 FixupKind = RISCV::fixup_riscv_pcrel_hi20; 326 RelaxCandidate = true; 327 break; 328 case RISCVMCExpr::VK_RISCV_GOT_HI: 329 FixupKind = RISCV::fixup_riscv_got_hi20; 330 break; 331 case RISCVMCExpr::VK_RISCV_TPREL_LO: 332 if (MIFrm == RISCVII::InstFormatI) 333 FixupKind = RISCV::fixup_riscv_tprel_lo12_i; 334 else if (MIFrm == RISCVII::InstFormatS) 335 FixupKind = RISCV::fixup_riscv_tprel_lo12_s; 336 else 337 llvm_unreachable( 338 "VK_RISCV_TPREL_LO used with unexpected instruction format"); 339 RelaxCandidate = true; 340 break; 341 case RISCVMCExpr::VK_RISCV_TPREL_HI: 342 FixupKind = RISCV::fixup_riscv_tprel_hi20; 343 RelaxCandidate = true; 344 break; 345 case RISCVMCExpr::VK_RISCV_TLS_GOT_HI: 346 FixupKind = RISCV::fixup_riscv_tls_got_hi20; 347 break; 348 case RISCVMCExpr::VK_RISCV_TLS_GD_HI: 349 FixupKind = RISCV::fixup_riscv_tls_gd_hi20; 350 break; 351 case RISCVMCExpr::VK_RISCV_CALL: 352 FixupKind = RISCV::fixup_riscv_call; 353 RelaxCandidate = true; 354 break; 355 case RISCVMCExpr::VK_RISCV_CALL_PLT: 356 FixupKind = RISCV::fixup_riscv_call_plt; 357 RelaxCandidate = true; 358 break; 359 } 360 } else if (Kind == MCExpr::SymbolRef && 361 cast<MCSymbolRefExpr>(Expr)->getKind() == MCSymbolRefExpr::VK_None) { 362 if (MIFrm == RISCVII::InstFormatJ) { 363 FixupKind = RISCV::fixup_riscv_jal; 364 } else if (MIFrm == RISCVII::InstFormatB) { 365 FixupKind = RISCV::fixup_riscv_branch; 366 } else if (MIFrm == RISCVII::InstFormatCJ) { 367 FixupKind = RISCV::fixup_riscv_rvc_jump; 368 } else if (MIFrm == RISCVII::InstFormatCB) { 369 FixupKind = RISCV::fixup_riscv_rvc_branch; 370 } 371 } 372 373 assert(FixupKind != RISCV::fixup_riscv_invalid && "Unhandled expression!"); 374 375 Fixups.push_back( 376 MCFixup::create(0, Expr, MCFixupKind(FixupKind), MI.getLoc())); 377 ++MCNumFixups; 378 379 // Ensure an R_RISCV_RELAX relocation will be emitted if linker relaxation is 380 // enabled and the current fixup will result in a relocation that may be 381 // relaxed. 382 if (EnableRelax && RelaxCandidate) { 383 const MCConstantExpr *Dummy = MCConstantExpr::create(0, Ctx); 384 Fixups.push_back( 385 MCFixup::create(0, Dummy, MCFixupKind(RISCV::fixup_riscv_relax), 386 MI.getLoc())); 387 ++MCNumFixups; 388 } 389 390 return 0; 391 } 392 393 unsigned RISCVMCCodeEmitter::getVMaskReg(const MCInst &MI, unsigned OpNo, 394 SmallVectorImpl<MCFixup> &Fixups, 395 const MCSubtargetInfo &STI) const { 396 MCOperand MO = MI.getOperand(OpNo); 397 assert(MO.isReg() && "Expected a register."); 398 399 switch (MO.getReg()) { 400 default: 401 llvm_unreachable("Invalid mask register."); 402 case RISCV::V0: 403 return 0; 404 case RISCV::NoRegister: 405 return 1; 406 } 407 } 408 409 #define ENABLE_INSTR_PREDICATE_VERIFIER 410 #include "RISCVGenMCCodeEmitter.inc" 411