1 //===-- RISCVMCCodeEmitter.cpp - Convert RISCV code to machine code -------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements the RISCVMCCodeEmitter class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "MCTargetDesc/RISCVFixupKinds.h"
14 #include "MCTargetDesc/RISCVMCExpr.h"
15 #include "MCTargetDesc/RISCVMCTargetDesc.h"
16 #include "Utils/RISCVBaseInfo.h"
17 #include "llvm/ADT/Statistic.h"
18 #include "llvm/CodeGen/Register.h"
19 #include "llvm/MC/MCAsmInfo.h"
20 #include "llvm/MC/MCCodeEmitter.h"
21 #include "llvm/MC/MCContext.h"
22 #include "llvm/MC/MCExpr.h"
23 #include "llvm/MC/MCInst.h"
24 #include "llvm/MC/MCInstBuilder.h"
25 #include "llvm/MC/MCInstrInfo.h"
26 #include "llvm/MC/MCRegisterInfo.h"
27 #include "llvm/MC/MCSymbol.h"
28 #include "llvm/Support/Casting.h"
29 #include "llvm/Support/EndianStream.h"
30 #include "llvm/Support/raw_ostream.h"
31 
32 using namespace llvm;
33 
34 #define DEBUG_TYPE "mccodeemitter"
35 
36 STATISTIC(MCNumEmitted, "Number of MC instructions emitted");
37 STATISTIC(MCNumFixups, "Number of MC fixups created");
38 
39 namespace {
40 class RISCVMCCodeEmitter : public MCCodeEmitter {
41   RISCVMCCodeEmitter(const RISCVMCCodeEmitter &) = delete;
42   void operator=(const RISCVMCCodeEmitter &) = delete;
43   MCContext &Ctx;
44   MCInstrInfo const &MCII;
45 
46 public:
47   RISCVMCCodeEmitter(MCContext &ctx, MCInstrInfo const &MCII)
48       : Ctx(ctx), MCII(MCII) {}
49 
50   ~RISCVMCCodeEmitter() override {}
51 
52   void encodeInstruction(const MCInst &MI, raw_ostream &OS,
53                          SmallVectorImpl<MCFixup> &Fixups,
54                          const MCSubtargetInfo &STI) const override;
55 
56   void expandFunctionCall(const MCInst &MI, raw_ostream &OS,
57                           SmallVectorImpl<MCFixup> &Fixups,
58                           const MCSubtargetInfo &STI) const;
59 
60   void expandAddTPRel(const MCInst &MI, raw_ostream &OS,
61                       SmallVectorImpl<MCFixup> &Fixups,
62                       const MCSubtargetInfo &STI) const;
63 
64   /// TableGen'erated function for getting the binary encoding for an
65   /// instruction.
66   uint64_t getBinaryCodeForInstr(const MCInst &MI,
67                                  SmallVectorImpl<MCFixup> &Fixups,
68                                  const MCSubtargetInfo &STI) const;
69 
70   /// Return binary encoding of operand. If the machine operand requires
71   /// relocation, record the relocation and return zero.
72   unsigned getMachineOpValue(const MCInst &MI, const MCOperand &MO,
73                              SmallVectorImpl<MCFixup> &Fixups,
74                              const MCSubtargetInfo &STI) const;
75 
76   unsigned getImmOpValueAsr1(const MCInst &MI, unsigned OpNo,
77                              SmallVectorImpl<MCFixup> &Fixups,
78                              const MCSubtargetInfo &STI) const;
79 
80   unsigned getImmOpValue(const MCInst &MI, unsigned OpNo,
81                          SmallVectorImpl<MCFixup> &Fixups,
82                          const MCSubtargetInfo &STI) const;
83 };
84 } // end anonymous namespace
85 
86 MCCodeEmitter *llvm::createRISCVMCCodeEmitter(const MCInstrInfo &MCII,
87                                               const MCRegisterInfo &MRI,
88                                               MCContext &Ctx) {
89   return new RISCVMCCodeEmitter(Ctx, MCII);
90 }
91 
92 // Expand PseudoCALL(Reg), PseudoTAIL and PseudoJump to AUIPC and JALR with
93 // relocation types. We those pseudo-instructions while encoding them, meaning
94 // AUIPC and JALR won't go through RISCV MC to MC compressed instruction
95 // transformation. This is acceptable because AUIPC has no 16-bit form and
96 // C_JALR have no immediate operand field.  We let linker relaxation deal with
97 // it. When linker relaxation enabled, AUIPC and JALR have chance relax to JAL.
98 // If C extension is enabled, JAL has chance relax to C_JAL.
99 void RISCVMCCodeEmitter::expandFunctionCall(const MCInst &MI, raw_ostream &OS,
100                                             SmallVectorImpl<MCFixup> &Fixups,
101                                             const MCSubtargetInfo &STI) const {
102   MCInst TmpInst;
103   MCOperand Func;
104   Register Ra;
105   if (MI.getOpcode() == RISCV::PseudoTAIL) {
106     Func = MI.getOperand(0);
107     Ra = RISCV::X6;
108   } else if (MI.getOpcode() == RISCV::PseudoCALLReg) {
109     Func = MI.getOperand(1);
110     Ra = MI.getOperand(0).getReg();
111   } else if (MI.getOpcode() == RISCV::PseudoCALL) {
112     Func = MI.getOperand(0);
113     Ra = RISCV::X1;
114   } else if (MI.getOpcode() == RISCV::PseudoJump) {
115     Func = MI.getOperand(1);
116     Ra = MI.getOperand(0).getReg();
117   }
118   uint32_t Binary;
119 
120   assert(Func.isExpr() && "Expected expression");
121 
122   const MCExpr *CallExpr = Func.getExpr();
123 
124   // Emit AUIPC Ra, Func with R_RISCV_CALL relocation type.
125   TmpInst = MCInstBuilder(RISCV::AUIPC)
126                 .addReg(Ra)
127                 .addOperand(MCOperand::createExpr(CallExpr));
128   Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI);
129   support::endian::write(OS, Binary, support::little);
130 
131   if (MI.getOpcode() == RISCV::PseudoTAIL ||
132       MI.getOpcode() == RISCV::PseudoJump)
133     // Emit JALR X0, Ra, 0
134     TmpInst = MCInstBuilder(RISCV::JALR).addReg(RISCV::X0).addReg(Ra).addImm(0);
135   else
136     // Emit JALR Ra, Ra, 0
137     TmpInst = MCInstBuilder(RISCV::JALR).addReg(Ra).addReg(Ra).addImm(0);
138   Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI);
139   support::endian::write(OS, Binary, support::little);
140 }
141 
142 // Expand PseudoAddTPRel to a simple ADD with the correct relocation.
143 void RISCVMCCodeEmitter::expandAddTPRel(const MCInst &MI, raw_ostream &OS,
144                                         SmallVectorImpl<MCFixup> &Fixups,
145                                         const MCSubtargetInfo &STI) const {
146   MCOperand DestReg = MI.getOperand(0);
147   MCOperand SrcReg = MI.getOperand(1);
148   MCOperand TPReg = MI.getOperand(2);
149   assert(TPReg.isReg() && TPReg.getReg() == RISCV::X4 &&
150          "Expected thread pointer as second input to TP-relative add");
151 
152   MCOperand SrcSymbol = MI.getOperand(3);
153   assert(SrcSymbol.isExpr() &&
154          "Expected expression as third input to TP-relative add");
155 
156   const RISCVMCExpr *Expr = dyn_cast<RISCVMCExpr>(SrcSymbol.getExpr());
157   assert(Expr && Expr->getKind() == RISCVMCExpr::VK_RISCV_TPREL_ADD &&
158          "Expected tprel_add relocation on TP-relative symbol");
159 
160   // Emit the correct tprel_add relocation for the symbol.
161   Fixups.push_back(MCFixup::create(
162       0, Expr, MCFixupKind(RISCV::fixup_riscv_tprel_add), MI.getLoc()));
163 
164   // Emit fixup_riscv_relax for tprel_add where the relax feature is enabled.
165   if (STI.getFeatureBits()[RISCV::FeatureRelax]) {
166     const MCConstantExpr *Dummy = MCConstantExpr::create(0, Ctx);
167     Fixups.push_back(MCFixup::create(
168         0, Dummy, MCFixupKind(RISCV::fixup_riscv_relax), MI.getLoc()));
169   }
170 
171   // Emit a normal ADD instruction with the given operands.
172   MCInst TmpInst = MCInstBuilder(RISCV::ADD)
173                        .addOperand(DestReg)
174                        .addOperand(SrcReg)
175                        .addOperand(TPReg);
176   uint32_t Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI);
177   support::endian::write(OS, Binary, support::little);
178 }
179 
180 void RISCVMCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,
181                                            SmallVectorImpl<MCFixup> &Fixups,
182                                            const MCSubtargetInfo &STI) const {
183   const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
184   // Get byte count of instruction.
185   unsigned Size = Desc.getSize();
186 
187   if (MI.getOpcode() == RISCV::PseudoCALLReg ||
188       MI.getOpcode() == RISCV::PseudoCALL ||
189       MI.getOpcode() == RISCV::PseudoTAIL ||
190       MI.getOpcode() == RISCV::PseudoJump) {
191     expandFunctionCall(MI, OS, Fixups, STI);
192     MCNumEmitted += 2;
193     return;
194   }
195 
196   if (MI.getOpcode() == RISCV::PseudoAddTPRel) {
197     expandAddTPRel(MI, OS, Fixups, STI);
198     MCNumEmitted += 1;
199     return;
200   }
201 
202   switch (Size) {
203   default:
204     llvm_unreachable("Unhandled encodeInstruction length!");
205   case 2: {
206     uint16_t Bits = getBinaryCodeForInstr(MI, Fixups, STI);
207     support::endian::write<uint16_t>(OS, Bits, support::little);
208     break;
209   }
210   case 4: {
211     uint32_t Bits = getBinaryCodeForInstr(MI, Fixups, STI);
212     support::endian::write(OS, Bits, support::little);
213     break;
214   }
215   }
216 
217   ++MCNumEmitted; // Keep track of the # of mi's emitted.
218 }
219 
220 unsigned
221 RISCVMCCodeEmitter::getMachineOpValue(const MCInst &MI, const MCOperand &MO,
222                                       SmallVectorImpl<MCFixup> &Fixups,
223                                       const MCSubtargetInfo &STI) const {
224 
225   if (MO.isReg())
226     return Ctx.getRegisterInfo()->getEncodingValue(MO.getReg());
227 
228   if (MO.isImm())
229     return static_cast<unsigned>(MO.getImm());
230 
231   llvm_unreachable("Unhandled expression!");
232   return 0;
233 }
234 
235 unsigned
236 RISCVMCCodeEmitter::getImmOpValueAsr1(const MCInst &MI, unsigned OpNo,
237                                       SmallVectorImpl<MCFixup> &Fixups,
238                                       const MCSubtargetInfo &STI) const {
239   const MCOperand &MO = MI.getOperand(OpNo);
240 
241   if (MO.isImm()) {
242     unsigned Res = MO.getImm();
243     assert((Res & 1) == 0 && "LSB is non-zero");
244     return Res >> 1;
245   }
246 
247   return getImmOpValue(MI, OpNo, Fixups, STI);
248 }
249 
250 unsigned RISCVMCCodeEmitter::getImmOpValue(const MCInst &MI, unsigned OpNo,
251                                            SmallVectorImpl<MCFixup> &Fixups,
252                                            const MCSubtargetInfo &STI) const {
253   bool EnableRelax = STI.getFeatureBits()[RISCV::FeatureRelax];
254   const MCOperand &MO = MI.getOperand(OpNo);
255 
256   MCInstrDesc const &Desc = MCII.get(MI.getOpcode());
257   unsigned MIFrm = Desc.TSFlags & RISCVII::InstFormatMask;
258 
259   // If the destination is an immediate, there is nothing to do.
260   if (MO.isImm())
261     return MO.getImm();
262 
263   assert(MO.isExpr() &&
264          "getImmOpValue expects only expressions or immediates");
265   const MCExpr *Expr = MO.getExpr();
266   MCExpr::ExprKind Kind = Expr->getKind();
267   RISCV::Fixups FixupKind = RISCV::fixup_riscv_invalid;
268   bool RelaxCandidate = false;
269   if (Kind == MCExpr::Target) {
270     const RISCVMCExpr *RVExpr = cast<RISCVMCExpr>(Expr);
271 
272     switch (RVExpr->getKind()) {
273     case RISCVMCExpr::VK_RISCV_None:
274     case RISCVMCExpr::VK_RISCV_Invalid:
275     case RISCVMCExpr::VK_RISCV_32_PCREL:
276       llvm_unreachable("Unhandled fixup kind!");
277     case RISCVMCExpr::VK_RISCV_TPREL_ADD:
278       // tprel_add is only used to indicate that a relocation should be emitted
279       // for an add instruction used in TP-relative addressing. It should not be
280       // expanded as if representing an actual instruction operand and so to
281       // encounter it here is an error.
282       llvm_unreachable(
283           "VK_RISCV_TPREL_ADD should not represent an instruction operand");
284     case RISCVMCExpr::VK_RISCV_LO:
285       if (MIFrm == RISCVII::InstFormatI)
286         FixupKind = RISCV::fixup_riscv_lo12_i;
287       else if (MIFrm == RISCVII::InstFormatS)
288         FixupKind = RISCV::fixup_riscv_lo12_s;
289       else
290         llvm_unreachable("VK_RISCV_LO used with unexpected instruction format");
291       RelaxCandidate = true;
292       break;
293     case RISCVMCExpr::VK_RISCV_HI:
294       FixupKind = RISCV::fixup_riscv_hi20;
295       RelaxCandidate = true;
296       break;
297     case RISCVMCExpr::VK_RISCV_PCREL_LO:
298       if (MIFrm == RISCVII::InstFormatI)
299         FixupKind = RISCV::fixup_riscv_pcrel_lo12_i;
300       else if (MIFrm == RISCVII::InstFormatS)
301         FixupKind = RISCV::fixup_riscv_pcrel_lo12_s;
302       else
303         llvm_unreachable(
304             "VK_RISCV_PCREL_LO used with unexpected instruction format");
305       RelaxCandidate = true;
306       break;
307     case RISCVMCExpr::VK_RISCV_PCREL_HI:
308       FixupKind = RISCV::fixup_riscv_pcrel_hi20;
309       RelaxCandidate = true;
310       break;
311     case RISCVMCExpr::VK_RISCV_GOT_HI:
312       FixupKind = RISCV::fixup_riscv_got_hi20;
313       break;
314     case RISCVMCExpr::VK_RISCV_TPREL_LO:
315       if (MIFrm == RISCVII::InstFormatI)
316         FixupKind = RISCV::fixup_riscv_tprel_lo12_i;
317       else if (MIFrm == RISCVII::InstFormatS)
318         FixupKind = RISCV::fixup_riscv_tprel_lo12_s;
319       else
320         llvm_unreachable(
321             "VK_RISCV_TPREL_LO used with unexpected instruction format");
322       RelaxCandidate = true;
323       break;
324     case RISCVMCExpr::VK_RISCV_TPREL_HI:
325       FixupKind = RISCV::fixup_riscv_tprel_hi20;
326       RelaxCandidate = true;
327       break;
328     case RISCVMCExpr::VK_RISCV_TLS_GOT_HI:
329       FixupKind = RISCV::fixup_riscv_tls_got_hi20;
330       break;
331     case RISCVMCExpr::VK_RISCV_TLS_GD_HI:
332       FixupKind = RISCV::fixup_riscv_tls_gd_hi20;
333       break;
334     case RISCVMCExpr::VK_RISCV_CALL:
335       FixupKind = RISCV::fixup_riscv_call;
336       RelaxCandidate = true;
337       break;
338     case RISCVMCExpr::VK_RISCV_CALL_PLT:
339       FixupKind = RISCV::fixup_riscv_call_plt;
340       RelaxCandidate = true;
341       break;
342     }
343   } else if (Kind == MCExpr::SymbolRef &&
344              cast<MCSymbolRefExpr>(Expr)->getKind() == MCSymbolRefExpr::VK_None) {
345     if (Desc.getOpcode() == RISCV::JAL) {
346       FixupKind = RISCV::fixup_riscv_jal;
347     } else if (MIFrm == RISCVII::InstFormatB) {
348       FixupKind = RISCV::fixup_riscv_branch;
349     } else if (MIFrm == RISCVII::InstFormatCJ) {
350       FixupKind = RISCV::fixup_riscv_rvc_jump;
351     } else if (MIFrm == RISCVII::InstFormatCB) {
352       FixupKind = RISCV::fixup_riscv_rvc_branch;
353     }
354   }
355 
356   assert(FixupKind != RISCV::fixup_riscv_invalid && "Unhandled expression!");
357 
358   Fixups.push_back(
359       MCFixup::create(0, Expr, MCFixupKind(FixupKind), MI.getLoc()));
360   ++MCNumFixups;
361 
362   // Ensure an R_RISCV_RELAX relocation will be emitted if linker relaxation is
363   // enabled and the current fixup will result in a relocation that may be
364   // relaxed.
365   if (EnableRelax && RelaxCandidate) {
366     const MCConstantExpr *Dummy = MCConstantExpr::create(0, Ctx);
367     Fixups.push_back(
368     MCFixup::create(0, Dummy, MCFixupKind(RISCV::fixup_riscv_relax),
369                     MI.getLoc()));
370     ++MCNumFixups;
371   }
372 
373   return 0;
374 }
375 
376 #include "RISCVGenMCCodeEmitter.inc"
377