1 //===-- RISCVAsmBackend.cpp - RISCV Assembler Backend ---------------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 
10 #include "MCTargetDesc/RISCVMCTargetDesc.h"
11 #include "llvm/MC/MCAsmBackend.h"
12 #include "llvm/MC/MCAssembler.h"
13 #include "llvm/MC/MCDirectives.h"
14 #include "llvm/MC/MCELFObjectWriter.h"
15 #include "llvm/MC/MCExpr.h"
16 #include "llvm/MC/MCFixupKindInfo.h"
17 #include "llvm/MC/MCObjectWriter.h"
18 #include "llvm/MC/MCSubtargetInfo.h"
19 #include "llvm/MC/MCSymbol.h"
20 #include "llvm/Support/ErrorHandling.h"
21 #include "llvm/Support/raw_ostream.h"
22 
23 using namespace llvm;
24 
25 namespace {
26 class RISCVAsmBackend : public MCAsmBackend {
27   uint8_t OSABI;
28   bool Is64Bit;
29 
30 public:
31   RISCVAsmBackend(uint8_t OSABI, bool Is64Bit)
32       : MCAsmBackend(), OSABI(OSABI), Is64Bit(Is64Bit) {}
33   ~RISCVAsmBackend() override {}
34 
35   void applyFixup(const MCAssembler &Asm, const MCFixup &Fixup,
36                   const MCValue &Target, MutableArrayRef<char> Data,
37                   uint64_t Value, bool IsPCRel) const override;
38 
39   MCObjectWriter *createObjectWriter(raw_pwrite_stream &OS) const override;
40 
41   bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value,
42                             const MCRelaxableFragment *DF,
43                             const MCAsmLayout &Layout) const override {
44     return false;
45   }
46 
47   unsigned getNumFixupKinds() const override { return 1; }
48 
49   bool mayNeedRelaxation(const MCInst &Inst) const override { return false; }
50 
51   void relaxInstruction(const MCInst &Inst, const MCSubtargetInfo &STI,
52                         MCInst &Res) const override {
53 
54     llvm_unreachable("RISCVAsmBackend::relaxInstruction() unimplemented");
55   }
56 
57   bool writeNopData(uint64_t Count, MCObjectWriter *OW) const override;
58 };
59 
60 bool RISCVAsmBackend::writeNopData(uint64_t Count, MCObjectWriter *OW) const {
61   // Once support for the compressed instruction set is added, we will be able
62   // to conditionally support 16-bit NOPs
63   if ((Count % 4) != 0)
64     return false;
65 
66   // The canonical nop on RISC-V is addi x0, x0, 0
67   for (uint64_t i = 0; i < Count; i += 4)
68     OW->write32(0x13);
69 
70   return true;
71 }
72 
73 void RISCVAsmBackend::applyFixup(const MCAssembler &Asm, const MCFixup &Fixup,
74                                  const MCValue &Target,
75                                  MutableArrayRef<char> Data, uint64_t Value,
76                                  bool IsPCRel) const {
77   return;
78 }
79 
80 MCObjectWriter *
81 RISCVAsmBackend::createObjectWriter(raw_pwrite_stream &OS) const {
82   return createRISCVELFObjectWriter(OS, OSABI, Is64Bit);
83 }
84 
85 } // end anonymous namespace
86 
87 MCAsmBackend *llvm::createRISCVAsmBackend(const Target &T,
88                                           const MCRegisterInfo &MRI,
89                                           const Triple &TT, StringRef CPU,
90                                           const MCTargetOptions &Options) {
91   uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TT.getOS());
92   return new RISCVAsmBackend(OSABI, TT.isArch64Bit());
93 }
94