1 //===-- RISCVAsmBackend.cpp - RISCV Assembler Backend ---------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #include "RISCVAsmBackend.h"
10 #include "RISCVMCExpr.h"
11 #include "llvm/ADT/APInt.h"
12 #include "llvm/MC/MCAssembler.h"
13 #include "llvm/MC/MCContext.h"
14 #include "llvm/MC/MCDirectives.h"
15 #include "llvm/MC/MCELFObjectWriter.h"
16 #include "llvm/MC/MCExpr.h"
17 #include "llvm/MC/MCObjectWriter.h"
18 #include "llvm/MC/MCSymbol.h"
19 #include "llvm/MC/MCValue.h"
20 #include "llvm/Support/ErrorHandling.h"
21 #include "llvm/Support/raw_ostream.h"
22 
23 using namespace llvm;
24 
25 // If linker relaxation is enabled, or the relax option had previously been
26 // enabled, always emit relocations even if the fixup can be resolved. This is
27 // necessary for correctness as offsets may change during relaxation.
28 bool RISCVAsmBackend::shouldForceRelocation(const MCAssembler &Asm,
29                                             const MCFixup &Fixup,
30                                             const MCValue &Target) {
31   bool ShouldForce = false;
32 
33   switch (Fixup.getTargetKind()) {
34   default:
35     break;
36   case FK_Data_1:
37   case FK_Data_2:
38   case FK_Data_4:
39   case FK_Data_8:
40     if (Target.isAbsolute())
41       return false;
42     break;
43   case RISCV::fixup_riscv_got_hi20:
44   case RISCV::fixup_riscv_tls_got_hi20:
45   case RISCV::fixup_riscv_tls_gd_hi20:
46     return true;
47   case RISCV::fixup_riscv_pcrel_lo12_i:
48   case RISCV::fixup_riscv_pcrel_lo12_s:
49     // For pcrel_lo12, force a relocation if the target of the corresponding
50     // pcrel_hi20 is not in the same fragment.
51     const MCFixup *T = cast<RISCVMCExpr>(Fixup.getValue())->getPCRelHiFixup();
52     if (!T) {
53       Asm.getContext().reportError(Fixup.getLoc(),
54                                    "could not find corresponding %pcrel_hi");
55       return false;
56     }
57 
58     switch (T->getTargetKind()) {
59     default:
60       llvm_unreachable("Unexpected fixup kind for pcrel_lo12");
61       break;
62     case RISCV::fixup_riscv_got_hi20:
63     case RISCV::fixup_riscv_tls_got_hi20:
64     case RISCV::fixup_riscv_tls_gd_hi20:
65       ShouldForce = true;
66       break;
67     case RISCV::fixup_riscv_pcrel_hi20:
68       ShouldForce = T->getValue()->findAssociatedFragment() !=
69                     Fixup.getValue()->findAssociatedFragment();
70       break;
71     }
72     break;
73   }
74 
75   return ShouldForce || STI.getFeatureBits()[RISCV::FeatureRelax] ||
76          ForceRelocs;
77 }
78 
79 bool RISCVAsmBackend::fixupNeedsRelaxationAdvanced(const MCFixup &Fixup,
80                                                    bool Resolved,
81                                                    uint64_t Value,
82                                                    const MCRelaxableFragment *DF,
83                                                    const MCAsmLayout &Layout,
84                                                    const bool WasForced) const {
85   // Return true if the symbol is actually unresolved.
86   // Resolved could be always false when shouldForceRelocation return true.
87   // We use !WasForced to indicate that the symbol is unresolved and not forced
88   // by shouldForceRelocation.
89   if (!Resolved && !WasForced)
90     return true;
91 
92   int64_t Offset = int64_t(Value);
93   switch (Fixup.getTargetKind()) {
94   default:
95     return false;
96   case RISCV::fixup_riscv_rvc_branch:
97     // For compressed branch instructions the immediate must be
98     // in the range [-256, 254].
99     return Offset > 254 || Offset < -256;
100   case RISCV::fixup_riscv_rvc_jump:
101     // For compressed jump instructions the immediate must be
102     // in the range [-2048, 2046].
103     return Offset > 2046 || Offset < -2048;
104   }
105 }
106 
107 void RISCVAsmBackend::relaxInstruction(const MCInst &Inst,
108                                        const MCSubtargetInfo &STI,
109                                        MCInst &Res) const {
110   // TODO: replace this with call to auto generated uncompressinstr() function.
111   switch (Inst.getOpcode()) {
112   default:
113     llvm_unreachable("Opcode not expected!");
114   case RISCV::C_BEQZ:
115     // c.beqz $rs1, $imm -> beq $rs1, X0, $imm.
116     Res.setOpcode(RISCV::BEQ);
117     Res.addOperand(Inst.getOperand(0));
118     Res.addOperand(MCOperand::createReg(RISCV::X0));
119     Res.addOperand(Inst.getOperand(1));
120     break;
121   case RISCV::C_BNEZ:
122     // c.bnez $rs1, $imm -> bne $rs1, X0, $imm.
123     Res.setOpcode(RISCV::BNE);
124     Res.addOperand(Inst.getOperand(0));
125     Res.addOperand(MCOperand::createReg(RISCV::X0));
126     Res.addOperand(Inst.getOperand(1));
127     break;
128   case RISCV::C_J:
129     // c.j $imm -> jal X0, $imm.
130     Res.setOpcode(RISCV::JAL);
131     Res.addOperand(MCOperand::createReg(RISCV::X0));
132     Res.addOperand(Inst.getOperand(0));
133     break;
134   case RISCV::C_JAL:
135     // c.jal $imm -> jal X1, $imm.
136     Res.setOpcode(RISCV::JAL);
137     Res.addOperand(MCOperand::createReg(RISCV::X1));
138     Res.addOperand(Inst.getOperand(0));
139     break;
140   }
141 }
142 
143 // Given a compressed control flow instruction this function returns
144 // the expanded instruction.
145 unsigned RISCVAsmBackend::getRelaxedOpcode(unsigned Op) const {
146   switch (Op) {
147   default:
148     return Op;
149   case RISCV::C_BEQZ:
150     return RISCV::BEQ;
151   case RISCV::C_BNEZ:
152     return RISCV::BNE;
153   case RISCV::C_J:
154   case RISCV::C_JAL: // fall through.
155     return RISCV::JAL;
156   }
157 }
158 
159 bool RISCVAsmBackend::mayNeedRelaxation(const MCInst &Inst,
160                                         const MCSubtargetInfo &STI) const {
161   return getRelaxedOpcode(Inst.getOpcode()) != Inst.getOpcode();
162 }
163 
164 bool RISCVAsmBackend::writeNopData(raw_ostream &OS, uint64_t Count) const {
165   bool HasStdExtC = STI.getFeatureBits()[RISCV::FeatureStdExtC];
166   unsigned MinNopLen = HasStdExtC ? 2 : 4;
167 
168   if ((Count % MinNopLen) != 0)
169     return false;
170 
171   // The canonical nop on RISC-V is addi x0, x0, 0.
172   for (; Count >= 4; Count -= 4)
173     OS.write("\x13\0\0\0", 4);
174 
175   // The canonical nop on RVC is c.nop.
176   if (Count && HasStdExtC)
177     OS.write("\x01\0", 2);
178 
179   return true;
180 }
181 
182 static uint64_t adjustFixupValue(const MCFixup &Fixup, uint64_t Value,
183                                  MCContext &Ctx) {
184   switch (Fixup.getTargetKind()) {
185   default:
186     llvm_unreachable("Unknown fixup kind!");
187   case RISCV::fixup_riscv_got_hi20:
188   case RISCV::fixup_riscv_tls_got_hi20:
189   case RISCV::fixup_riscv_tls_gd_hi20:
190     llvm_unreachable("Relocation should be unconditionally forced\n");
191   case FK_Data_1:
192   case FK_Data_2:
193   case FK_Data_4:
194   case FK_Data_8:
195   case FK_Data_6b:
196     return Value;
197   case RISCV::fixup_riscv_lo12_i:
198   case RISCV::fixup_riscv_pcrel_lo12_i:
199   case RISCV::fixup_riscv_tprel_lo12_i:
200     return Value & 0xfff;
201   case RISCV::fixup_riscv_lo12_s:
202   case RISCV::fixup_riscv_pcrel_lo12_s:
203   case RISCV::fixup_riscv_tprel_lo12_s:
204     return (((Value >> 5) & 0x7f) << 25) | ((Value & 0x1f) << 7);
205   case RISCV::fixup_riscv_hi20:
206   case RISCV::fixup_riscv_pcrel_hi20:
207   case RISCV::fixup_riscv_tprel_hi20:
208     // Add 1 if bit 11 is 1, to compensate for low 12 bits being negative.
209     return ((Value + 0x800) >> 12) & 0xfffff;
210   case RISCV::fixup_riscv_jal: {
211     if (!isInt<21>(Value))
212       Ctx.reportError(Fixup.getLoc(), "fixup value out of range");
213     if (Value & 0x1)
214       Ctx.reportError(Fixup.getLoc(), "fixup value must be 2-byte aligned");
215     // Need to produce imm[19|10:1|11|19:12] from the 21-bit Value.
216     unsigned Sbit = (Value >> 20) & 0x1;
217     unsigned Hi8 = (Value >> 12) & 0xff;
218     unsigned Mid1 = (Value >> 11) & 0x1;
219     unsigned Lo10 = (Value >> 1) & 0x3ff;
220     // Inst{31} = Sbit;
221     // Inst{30-21} = Lo10;
222     // Inst{20} = Mid1;
223     // Inst{19-12} = Hi8;
224     Value = (Sbit << 19) | (Lo10 << 9) | (Mid1 << 8) | Hi8;
225     return Value;
226   }
227   case RISCV::fixup_riscv_branch: {
228     if (!isInt<13>(Value))
229       Ctx.reportError(Fixup.getLoc(), "fixup value out of range");
230     if (Value & 0x1)
231       Ctx.reportError(Fixup.getLoc(), "fixup value must be 2-byte aligned");
232     // Need to extract imm[12], imm[10:5], imm[4:1], imm[11] from the 13-bit
233     // Value.
234     unsigned Sbit = (Value >> 12) & 0x1;
235     unsigned Hi1 = (Value >> 11) & 0x1;
236     unsigned Mid6 = (Value >> 5) & 0x3f;
237     unsigned Lo4 = (Value >> 1) & 0xf;
238     // Inst{31} = Sbit;
239     // Inst{30-25} = Mid6;
240     // Inst{11-8} = Lo4;
241     // Inst{7} = Hi1;
242     Value = (Sbit << 31) | (Mid6 << 25) | (Lo4 << 8) | (Hi1 << 7);
243     return Value;
244   }
245   case RISCV::fixup_riscv_call:
246   case RISCV::fixup_riscv_call_plt: {
247     // Jalr will add UpperImm with the sign-extended 12-bit LowerImm,
248     // we need to add 0x800ULL before extract upper bits to reflect the
249     // effect of the sign extension.
250     uint64_t UpperImm = (Value + 0x800ULL) & 0xfffff000ULL;
251     uint64_t LowerImm = Value & 0xfffULL;
252     return UpperImm | ((LowerImm << 20) << 32);
253   }
254   case RISCV::fixup_riscv_rvc_jump: {
255     // Need to produce offset[11|4|9:8|10|6|7|3:1|5] from the 11-bit Value.
256     unsigned Bit11  = (Value >> 11) & 0x1;
257     unsigned Bit4   = (Value >> 4) & 0x1;
258     unsigned Bit9_8 = (Value >> 8) & 0x3;
259     unsigned Bit10  = (Value >> 10) & 0x1;
260     unsigned Bit6   = (Value >> 6) & 0x1;
261     unsigned Bit7   = (Value >> 7) & 0x1;
262     unsigned Bit3_1 = (Value >> 1) & 0x7;
263     unsigned Bit5   = (Value >> 5) & 0x1;
264     Value = (Bit11 << 10) | (Bit4 << 9) | (Bit9_8 << 7) | (Bit10 << 6) |
265             (Bit6 << 5) | (Bit7 << 4) | (Bit3_1 << 1) | Bit5;
266     return Value;
267   }
268   case RISCV::fixup_riscv_rvc_branch: {
269     // Need to produce offset[8|4:3], [reg 3 bit], offset[7:6|2:1|5]
270     unsigned Bit8   = (Value >> 8) & 0x1;
271     unsigned Bit7_6 = (Value >> 6) & 0x3;
272     unsigned Bit5   = (Value >> 5) & 0x1;
273     unsigned Bit4_3 = (Value >> 3) & 0x3;
274     unsigned Bit2_1 = (Value >> 1) & 0x3;
275     Value = (Bit8 << 12) | (Bit4_3 << 10) | (Bit7_6 << 5) | (Bit2_1 << 3) |
276             (Bit5 << 2);
277     return Value;
278   }
279 
280   }
281 }
282 
283 void RISCVAsmBackend::applyFixup(const MCAssembler &Asm, const MCFixup &Fixup,
284                                  const MCValue &Target,
285                                  MutableArrayRef<char> Data, uint64_t Value,
286                                  bool IsResolved,
287                                  const MCSubtargetInfo *STI) const {
288   MCContext &Ctx = Asm.getContext();
289   MCFixupKindInfo Info = getFixupKindInfo(Fixup.getKind());
290   if (!Value)
291     return; // Doesn't change encoding.
292   // Apply any target-specific value adjustments.
293   Value = adjustFixupValue(Fixup, Value, Ctx);
294 
295   // Shift the value into position.
296   Value <<= Info.TargetOffset;
297 
298   unsigned Offset = Fixup.getOffset();
299   unsigned NumBytes = alignTo(Info.TargetSize + Info.TargetOffset, 8) / 8;
300 
301   assert(Offset + NumBytes <= Data.size() && "Invalid fixup offset!");
302 
303   // For each byte of the fragment that the fixup touches, mask in the
304   // bits from the fixup value.
305   for (unsigned i = 0; i != NumBytes; ++i) {
306     Data[Offset + i] |= uint8_t((Value >> (i * 8)) & 0xff);
307   }
308 }
309 
310 // Linker relaxation may change code size. We have to insert Nops
311 // for .align directive when linker relaxation enabled. So then Linker
312 // could satisfy alignment by removing Nops.
313 // The function return the total Nops Size we need to insert.
314 bool RISCVAsmBackend::shouldInsertExtraNopBytesForCodeAlign(
315     const MCAlignFragment &AF, unsigned &Size) {
316   // Calculate Nops Size only when linker relaxation enabled.
317   if (!STI.getFeatureBits()[RISCV::FeatureRelax])
318     return false;
319 
320   bool HasStdExtC = STI.getFeatureBits()[RISCV::FeatureStdExtC];
321   unsigned MinNopLen = HasStdExtC ? 2 : 4;
322 
323   if (AF.getAlignment() <= MinNopLen) {
324     return false;
325   } else {
326     Size = AF.getAlignment() - MinNopLen;
327     return true;
328   }
329 }
330 
331 // We need to insert R_RISCV_ALIGN relocation type to indicate the
332 // position of Nops and the total bytes of the Nops have been inserted
333 // when linker relaxation enabled.
334 // The function insert fixup_riscv_align fixup which eventually will
335 // transfer to R_RISCV_ALIGN relocation type.
336 bool RISCVAsmBackend::shouldInsertFixupForCodeAlign(MCAssembler &Asm,
337                                                     const MCAsmLayout &Layout,
338                                                     MCAlignFragment &AF) {
339   // Insert the fixup only when linker relaxation enabled.
340   if (!STI.getFeatureBits()[RISCV::FeatureRelax])
341     return false;
342 
343   // Calculate total Nops we need to insert. If there are none to insert
344   // then simply return.
345   unsigned Count;
346   if (!shouldInsertExtraNopBytesForCodeAlign(AF, Count) || (Count == 0))
347     return false;
348 
349   MCContext &Ctx = Asm.getContext();
350   const MCExpr *Dummy = MCConstantExpr::create(0, Ctx);
351   // Create fixup_riscv_align fixup.
352   MCFixup Fixup =
353       MCFixup::create(0, Dummy, MCFixupKind(RISCV::fixup_riscv_align), SMLoc());
354 
355   uint64_t FixedValue = 0;
356   MCValue NopBytes = MCValue::get(Count);
357 
358   Asm.getWriter().recordRelocation(Asm, Layout, &AF, Fixup, NopBytes,
359                                    FixedValue);
360 
361   return true;
362 }
363 
364 std::unique_ptr<MCObjectTargetWriter>
365 RISCVAsmBackend::createObjectTargetWriter() const {
366   return createRISCVELFObjectWriter(OSABI, Is64Bit);
367 }
368 
369 MCAsmBackend *llvm::createRISCVAsmBackend(const Target &T,
370                                           const MCSubtargetInfo &STI,
371                                           const MCRegisterInfo &MRI,
372                                           const MCTargetOptions &Options) {
373   const Triple &TT = STI.getTargetTriple();
374   uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TT.getOS());
375   return new RISCVAsmBackend(STI, OSABI, TT.isArch64Bit(), Options);
376 }
377