1 //===-- PPCTargetTransformInfo.h - PPC specific TTI -------------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 /// \file 9 /// This file a TargetTransformInfo::Concept conforming object specific to the 10 /// PPC target machine. It uses the target's detailed information to 11 /// provide more precise answers to certain TTI queries, while letting the 12 /// target independent and default TTI implementations handle the rest. 13 /// 14 //===----------------------------------------------------------------------===// 15 16 #ifndef LLVM_LIB_TARGET_POWERPC_PPCTARGETTRANSFORMINFO_H 17 #define LLVM_LIB_TARGET_POWERPC_PPCTARGETTRANSFORMINFO_H 18 19 #include "PPCTargetMachine.h" 20 #include "llvm/Analysis/TargetTransformInfo.h" 21 #include "llvm/CodeGen/BasicTTIImpl.h" 22 #include "llvm/CodeGen/TargetLowering.h" 23 24 namespace llvm { 25 26 class PPCTTIImpl : public BasicTTIImplBase<PPCTTIImpl> { 27 typedef BasicTTIImplBase<PPCTTIImpl> BaseT; 28 typedef TargetTransformInfo TTI; 29 friend BaseT; 30 31 const PPCSubtarget *ST; 32 const PPCTargetLowering *TLI; 33 34 const PPCSubtarget *getST() const { return ST; } 35 const PPCTargetLowering *getTLI() const { return TLI; } 36 bool mightUseCTR(BasicBlock *BB, TargetLibraryInfo *LibInfo, 37 SmallPtrSetImpl<const Value *> &Visited); 38 39 public: 40 explicit PPCTTIImpl(const PPCTargetMachine *TM, const Function &F) 41 : BaseT(TM, F.getParent()->getDataLayout()), ST(TM->getSubtargetImpl(F)), 42 TLI(ST->getTargetLowering()) {} 43 44 Optional<Instruction *> instCombineIntrinsic(InstCombiner &IC, 45 IntrinsicInst &II) const; 46 47 /// \name Scalar TTI Implementations 48 /// @{ 49 50 using BaseT::getIntImmCost; 51 int getIntImmCost(const APInt &Imm, Type *Ty, 52 TTI::TargetCostKind CostKind); 53 54 int getIntImmCostInst(unsigned Opcode, unsigned Idx, const APInt &Imm, 55 Type *Ty, TTI::TargetCostKind CostKind); 56 int getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx, const APInt &Imm, 57 Type *Ty, TTI::TargetCostKind CostKind); 58 59 unsigned getUserCost(const User *U, ArrayRef<const Value *> Operands, 60 TTI::TargetCostKind CostKind); 61 62 TTI::PopcntSupportKind getPopcntSupport(unsigned TyWidth); 63 bool isHardwareLoopProfitable(Loop *L, ScalarEvolution &SE, 64 AssumptionCache &AC, 65 TargetLibraryInfo *LibInfo, 66 HardwareLoopInfo &HWLoopInfo); 67 bool canSaveCmp(Loop *L, BranchInst **BI, ScalarEvolution *SE, LoopInfo *LI, 68 DominatorTree *DT, AssumptionCache *AC, 69 TargetLibraryInfo *LibInfo); 70 void getUnrollingPreferences(Loop *L, ScalarEvolution &SE, 71 TTI::UnrollingPreferences &UP); 72 void getPeelingPreferences(Loop *L, ScalarEvolution &SE, 73 TTI::PeelingPreferences &PP); 74 bool isLSRCostLess(TargetTransformInfo::LSRCost &C1, 75 TargetTransformInfo::LSRCost &C2); 76 77 /// @} 78 79 /// \name Vector TTI Implementations 80 /// @{ 81 bool useColdCCForColdCall(Function &F); 82 bool enableAggressiveInterleaving(bool LoopHasReductions); 83 TTI::MemCmpExpansionOptions enableMemCmpExpansion(bool OptSize, 84 bool IsZeroCmp) const; 85 bool enableInterleavedAccessVectorization(); 86 87 enum PPCRegisterClass { 88 GPRRC, FPRRC, VRRC, VSXRC 89 }; 90 unsigned getNumberOfRegisters(unsigned ClassID) const; 91 unsigned getRegisterClassForType(bool Vector, Type *Ty = nullptr) const; 92 const char* getRegisterClassName(unsigned ClassID) const; 93 unsigned getRegisterBitWidth(bool Vector) const; 94 unsigned getCacheLineSize() const override; 95 unsigned getPrefetchDistance() const override; 96 unsigned getMaxInterleaveFactor(unsigned VF); 97 int vectorCostAdjustment(int Cost, unsigned Opcode, Type *Ty1, Type *Ty2); 98 int getArithmeticInstrCost( 99 unsigned Opcode, Type *Ty, 100 TTI::TargetCostKind CostKind = TTI::TCK_RecipThroughput, 101 TTI::OperandValueKind Opd1Info = TTI::OK_AnyValue, 102 TTI::OperandValueKind Opd2Info = TTI::OK_AnyValue, 103 TTI::OperandValueProperties Opd1PropInfo = TTI::OP_None, 104 TTI::OperandValueProperties Opd2PropInfo = TTI::OP_None, 105 ArrayRef<const Value *> Args = ArrayRef<const Value *>(), 106 const Instruction *CxtI = nullptr); 107 int getShuffleCost(TTI::ShuffleKind Kind, Type *Tp, int Index, Type *SubTp); 108 int getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src, 109 TTI::CastContextHint CCH, TTI::TargetCostKind CostKind, 110 const Instruction *I = nullptr); 111 int getCFInstrCost(unsigned Opcode, TTI::TargetCostKind CostKind); 112 int getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy, 113 TTI::TargetCostKind CostKind, 114 const Instruction *I = nullptr); 115 int getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index); 116 int getMemoryOpCost(unsigned Opcode, Type *Src, MaybeAlign Alignment, 117 unsigned AddressSpace, 118 TTI::TargetCostKind CostKind, 119 const Instruction *I = nullptr); 120 int getInterleavedMemoryOpCost( 121 unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef<unsigned> Indices, 122 Align Alignment, unsigned AddressSpace, 123 TTI::TargetCostKind CostKind = TTI::TCK_SizeAndLatency, 124 bool UseMaskForCond = false, bool UseMaskForGaps = false); 125 unsigned getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, 126 TTI::TargetCostKind CostKind); 127 128 /// @} 129 }; 130 131 } // end namespace llvm 132 133 #endif 134