1 //===-- PPCTargetTransformInfo.h - PPC specific TTI -------------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 /// \file 9 /// This file a TargetTransformInfo::Concept conforming object specific to the 10 /// PPC target machine. It uses the target's detailed information to 11 /// provide more precise answers to certain TTI queries, while letting the 12 /// target independent and default TTI implementations handle the rest. 13 /// 14 //===----------------------------------------------------------------------===// 15 16 #ifndef LLVM_LIB_TARGET_POWERPC_PPCTARGETTRANSFORMINFO_H 17 #define LLVM_LIB_TARGET_POWERPC_PPCTARGETTRANSFORMINFO_H 18 19 #include "PPCTargetMachine.h" 20 #include "llvm/Analysis/TargetTransformInfo.h" 21 #include "llvm/CodeGen/BasicTTIImpl.h" 22 #include "llvm/CodeGen/TargetLowering.h" 23 24 namespace llvm { 25 26 class PPCTTIImpl : public BasicTTIImplBase<PPCTTIImpl> { 27 typedef BasicTTIImplBase<PPCTTIImpl> BaseT; 28 typedef TargetTransformInfo TTI; 29 friend BaseT; 30 31 const PPCSubtarget *ST; 32 const PPCTargetLowering *TLI; 33 34 const PPCSubtarget *getST() const { return ST; } 35 const PPCTargetLowering *getTLI() const { return TLI; } 36 bool mightUseCTR(BasicBlock *BB, TargetLibraryInfo *LibInfo, 37 SmallPtrSetImpl<const Value *> &Visited); 38 39 public: 40 explicit PPCTTIImpl(const PPCTargetMachine *TM, const Function &F) 41 : BaseT(TM, F.getParent()->getDataLayout()), ST(TM->getSubtargetImpl(F)), 42 TLI(ST->getTargetLowering()) {} 43 44 Optional<Instruction *> instCombineIntrinsic(InstCombiner &IC, 45 IntrinsicInst &II) const; 46 47 /// \name Scalar TTI Implementations 48 /// @{ 49 50 using BaseT::getIntImmCost; 51 int getIntImmCost(const APInt &Imm, Type *Ty, 52 TTI::TargetCostKind CostKind); 53 54 int getIntImmCostInst(unsigned Opcode, unsigned Idx, const APInt &Imm, 55 Type *Ty, TTI::TargetCostKind CostKind, 56 Instruction *Inst = nullptr); 57 int getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx, const APInt &Imm, 58 Type *Ty, TTI::TargetCostKind CostKind); 59 60 InstructionCost getUserCost(const User *U, ArrayRef<const Value *> Operands, 61 TTI::TargetCostKind CostKind); 62 63 TTI::PopcntSupportKind getPopcntSupport(unsigned TyWidth); 64 bool isHardwareLoopProfitable(Loop *L, ScalarEvolution &SE, 65 AssumptionCache &AC, 66 TargetLibraryInfo *LibInfo, 67 HardwareLoopInfo &HWLoopInfo); 68 bool canSaveCmp(Loop *L, BranchInst **BI, ScalarEvolution *SE, LoopInfo *LI, 69 DominatorTree *DT, AssumptionCache *AC, 70 TargetLibraryInfo *LibInfo); 71 bool getTgtMemIntrinsic(IntrinsicInst *Inst, MemIntrinsicInfo &Info); 72 void getUnrollingPreferences(Loop *L, ScalarEvolution &SE, 73 TTI::UnrollingPreferences &UP); 74 void getPeelingPreferences(Loop *L, ScalarEvolution &SE, 75 TTI::PeelingPreferences &PP); 76 bool isLSRCostLess(TargetTransformInfo::LSRCost &C1, 77 TargetTransformInfo::LSRCost &C2); 78 bool isNumRegsMajorCostOfLSR(); 79 80 /// @} 81 82 /// \name Vector TTI Implementations 83 /// @{ 84 bool useColdCCForColdCall(Function &F); 85 bool enableAggressiveInterleaving(bool LoopHasReductions); 86 TTI::MemCmpExpansionOptions enableMemCmpExpansion(bool OptSize, 87 bool IsZeroCmp) const; 88 bool enableInterleavedAccessVectorization(); 89 90 enum PPCRegisterClass { 91 GPRRC, FPRRC, VRRC, VSXRC 92 }; 93 unsigned getNumberOfRegisters(unsigned ClassID) const; 94 unsigned getRegisterClassForType(bool Vector, Type *Ty = nullptr) const; 95 const char* getRegisterClassName(unsigned ClassID) const; 96 TypeSize getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const; 97 unsigned getCacheLineSize() const override; 98 unsigned getPrefetchDistance() const override; 99 unsigned getMaxInterleaveFactor(unsigned VF); 100 InstructionCost vectorCostAdjustment(InstructionCost Cost, unsigned Opcode, 101 Type *Ty1, Type *Ty2); 102 InstructionCost getArithmeticInstrCost( 103 unsigned Opcode, Type *Ty, 104 TTI::TargetCostKind CostKind = TTI::TCK_RecipThroughput, 105 TTI::OperandValueKind Opd1Info = TTI::OK_AnyValue, 106 TTI::OperandValueKind Opd2Info = TTI::OK_AnyValue, 107 TTI::OperandValueProperties Opd1PropInfo = TTI::OP_None, 108 TTI::OperandValueProperties Opd2PropInfo = TTI::OP_None, 109 ArrayRef<const Value *> Args = ArrayRef<const Value *>(), 110 const Instruction *CxtI = nullptr); 111 InstructionCost getShuffleCost(TTI::ShuffleKind Kind, Type *Tp, 112 ArrayRef<int> Mask, int Index, Type *SubTp); 113 InstructionCost getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src, 114 TTI::CastContextHint CCH, 115 TTI::TargetCostKind CostKind, 116 const Instruction *I = nullptr); 117 InstructionCost getCFInstrCost(unsigned Opcode, TTI::TargetCostKind CostKind, 118 const Instruction *I = nullptr); 119 InstructionCost getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy, 120 CmpInst::Predicate VecPred, 121 TTI::TargetCostKind CostKind, 122 const Instruction *I = nullptr); 123 InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, 124 unsigned Index); 125 InstructionCost getMemoryOpCost(unsigned Opcode, Type *Src, 126 MaybeAlign Alignment, unsigned AddressSpace, 127 TTI::TargetCostKind CostKind, 128 const Instruction *I = nullptr); 129 InstructionCost getInterleavedMemoryOpCost( 130 unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef<unsigned> Indices, 131 Align Alignment, unsigned AddressSpace, 132 TTI::TargetCostKind CostKind = TTI::TCK_SizeAndLatency, 133 bool UseMaskForCond = false, bool UseMaskForGaps = false); 134 InstructionCost getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, 135 TTI::TargetCostKind CostKind); 136 137 /// @} 138 }; 139 140 } // end namespace llvm 141 142 #endif 143