1 //===---------- PPCTLSDynamicCall.cpp - TLS Dynamic Call Fixup ------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This pass expands ADDItls{ld,gd}LADDR[32] machine instructions into 10 // separate ADDItls[gd]L[32] and GETtlsADDR[32] instructions, both of 11 // which define GPR3. A copy is added from GPR3 to the target virtual 12 // register of the original instruction. The GETtlsADDR[32] is really 13 // a call instruction, so its target register is constrained to be GPR3. 14 // This is not true of ADDItls[gd]L[32], but there is a legacy linker 15 // optimization bug that requires the target register of the addi of 16 // a local- or general-dynamic TLS access sequence to be GPR3. 17 // 18 // This is done in a late pass so that TLS variable accesses can be 19 // fully commoned by MachineCSE. 20 // 21 //===----------------------------------------------------------------------===// 22 23 #include "PPC.h" 24 #include "PPCInstrBuilder.h" 25 #include "PPCInstrInfo.h" 26 #include "PPCTargetMachine.h" 27 #include "llvm/CodeGen/LiveIntervals.h" 28 #include "llvm/CodeGen/MachineFunctionPass.h" 29 #include "llvm/CodeGen/MachineInstrBuilder.h" 30 #include "llvm/InitializePasses.h" 31 #include "llvm/Support/Debug.h" 32 #include "llvm/Support/raw_ostream.h" 33 34 using namespace llvm; 35 36 #define DEBUG_TYPE "ppc-tls-dynamic-call" 37 38 namespace { 39 struct PPCTLSDynamicCall : public MachineFunctionPass { 40 static char ID; 41 PPCTLSDynamicCall() : MachineFunctionPass(ID) { 42 initializePPCTLSDynamicCallPass(*PassRegistry::getPassRegistry()); 43 } 44 45 const PPCInstrInfo *TII; 46 LiveIntervals *LIS; 47 48 protected: 49 bool processBlock(MachineBasicBlock &MBB) { 50 bool Changed = false; 51 bool NeedFence = true; 52 bool Is64Bit = MBB.getParent()->getSubtarget<PPCSubtarget>().isPPC64(); 53 bool IsAIX = MBB.getParent()->getSubtarget<PPCSubtarget>().isAIXABI(); 54 bool IsPCREL = false; 55 56 for (MachineBasicBlock::iterator I = MBB.begin(), IE = MBB.end(); 57 I != IE;) { 58 MachineInstr &MI = *I; 59 IsPCREL = isPCREL(MI); 60 61 if (MI.getOpcode() != PPC::ADDItlsgdLADDR && 62 MI.getOpcode() != PPC::ADDItlsldLADDR && 63 MI.getOpcode() != PPC::ADDItlsgdLADDR32 && 64 MI.getOpcode() != PPC::ADDItlsldLADDR32 && 65 MI.getOpcode() != PPC::TLSGDAIX && !IsPCREL) { 66 // Although we create ADJCALLSTACKDOWN and ADJCALLSTACKUP 67 // as scheduling fences, we skip creating fences if we already 68 // have existing ADJCALLSTACKDOWN/UP to avoid nesting, 69 // which causes verification error with -verify-machineinstrs. 70 if (MI.getOpcode() == PPC::ADJCALLSTACKDOWN) 71 NeedFence = false; 72 else if (MI.getOpcode() == PPC::ADJCALLSTACKUP) 73 NeedFence = true; 74 75 ++I; 76 continue; 77 } 78 79 LLVM_DEBUG(dbgs() << "TLS Dynamic Call Fixup:\n " << MI); 80 81 Register OutReg = MI.getOperand(0).getReg(); 82 Register InReg = PPC::NoRegister; 83 Register GPR3 = Is64Bit ? PPC::X3 : PPC::R3; 84 Register GPR4 = Is64Bit ? PPC::X4 : PPC::R4; 85 SmallVector<Register, 3> OrigRegs = {OutReg, GPR3}; 86 if (!IsPCREL) { 87 InReg = MI.getOperand(1).getReg(); 88 OrigRegs.push_back(InReg); 89 } 90 DebugLoc DL = MI.getDebugLoc(); 91 92 unsigned Opc1, Opc2; 93 switch (MI.getOpcode()) { 94 default: 95 llvm_unreachable("Opcode inconsistency error"); 96 case PPC::ADDItlsgdLADDR: 97 Opc1 = PPC::ADDItlsgdL; 98 Opc2 = PPC::GETtlsADDR; 99 break; 100 case PPC::ADDItlsldLADDR: 101 Opc1 = PPC::ADDItlsldL; 102 Opc2 = PPC::GETtlsldADDR; 103 break; 104 case PPC::ADDItlsgdLADDR32: 105 Opc1 = PPC::ADDItlsgdL32; 106 Opc2 = PPC::GETtlsADDR32; 107 break; 108 case PPC::ADDItlsldLADDR32: 109 Opc1 = PPC::ADDItlsldL32; 110 Opc2 = PPC::GETtlsldADDR32; 111 break; 112 case PPC::TLSGDAIX: 113 // TLSGDAIX is expanded to two copies and GET_TLS_ADDR, so we only 114 // set Opc2 here. 115 Opc2 = PPC::GETtlsADDR32AIX; 116 break; 117 case PPC::PADDI8pc: 118 assert(IsPCREL && "Expecting General/Local Dynamic PCRel"); 119 Opc1 = PPC::PADDI8pc; 120 Opc2 = MI.getOperand(2).getTargetFlags() == 121 PPCII::MO_GOT_TLSGD_PCREL_FLAG 122 ? PPC::GETtlsADDRPCREL 123 : PPC::GETtlsldADDRPCREL; 124 } 125 126 // We create ADJCALLSTACKUP and ADJCALLSTACKDOWN around _tls_get_addr 127 // as scheduling fence to avoid it is scheduled before 128 // mflr in the prologue and the address in LR is clobbered (PR25839). 129 // We don't really need to save data to the stack - the clobbered 130 // registers are already saved when the SDNode (e.g. PPCaddiTlsgdLAddr) 131 // gets translated to the pseudo instruction (e.g. ADDItlsgdLADDR). 132 if (NeedFence) 133 BuildMI(MBB, I, DL, TII->get(PPC::ADJCALLSTACKDOWN)).addImm(0) 134 .addImm(0); 135 136 // The ADDItls* instruction is the first instruction in the 137 // repair range. 138 MachineBasicBlock::iterator First = I; 139 --First; 140 141 if (IsAIX) { 142 // The variable offset and region handle are copied in r4 and r3. The 143 // copies are followed by the GETtlsADDR32AIX instruction. 144 BuildMI(MBB, I, DL, TII->get(TargetOpcode::COPY), GPR4) 145 .addReg(MI.getOperand(1).getReg()); 146 BuildMI(MBB, I, DL, TII->get(TargetOpcode::COPY), GPR3) 147 .addReg(MI.getOperand(2).getReg()); 148 BuildMI(MBB, I, DL, TII->get(Opc2), GPR3).addReg(GPR3).addReg(GPR4); 149 } else { 150 MachineInstr *Addi; 151 if (IsPCREL) { 152 Addi = BuildMI(MBB, I, DL, TII->get(Opc1), GPR3).addImm(0); 153 } else { 154 // Expand into two ops built prior to the existing instruction. 155 assert(InReg != PPC::NoRegister && "Operand must be a register"); 156 Addi = BuildMI(MBB, I, DL, TII->get(Opc1), GPR3).addReg(InReg); 157 } 158 159 Addi->addOperand(MI.getOperand(2)); 160 161 MachineInstr *Call = 162 (BuildMI(MBB, I, DL, TII->get(Opc2), GPR3).addReg(GPR3)); 163 if (IsPCREL) 164 Call->addOperand(MI.getOperand(2)); 165 else 166 Call->addOperand(MI.getOperand(3)); 167 } 168 if (NeedFence) 169 BuildMI(MBB, I, DL, TII->get(PPC::ADJCALLSTACKUP)).addImm(0).addImm(0); 170 171 BuildMI(MBB, I, DL, TII->get(TargetOpcode::COPY), OutReg) 172 .addReg(GPR3); 173 174 // The COPY is the last instruction in the repair range. 175 MachineBasicBlock::iterator Last = I; 176 --Last; 177 178 // Move past the original instruction and remove it. 179 ++I; 180 MI.removeFromParent(); 181 182 // Repair the live intervals. 183 LIS->repairIntervalsInRange(&MBB, First, Last, OrigRegs); 184 Changed = true; 185 } 186 187 return Changed; 188 } 189 190 public: 191 bool isPCREL(const MachineInstr &MI) { 192 return (MI.getOpcode() == PPC::PADDI8pc) && 193 (MI.getOperand(2).getTargetFlags() == 194 PPCII::MO_GOT_TLSGD_PCREL_FLAG || 195 MI.getOperand(2).getTargetFlags() == 196 PPCII::MO_GOT_TLSLD_PCREL_FLAG); 197 } 198 199 bool runOnMachineFunction(MachineFunction &MF) override { 200 TII = MF.getSubtarget<PPCSubtarget>().getInstrInfo(); 201 LIS = &getAnalysis<LiveIntervals>(); 202 203 bool Changed = false; 204 205 for (MachineFunction::iterator I = MF.begin(); I != MF.end();) { 206 MachineBasicBlock &B = *I++; 207 if (processBlock(B)) 208 Changed = true; 209 } 210 211 return Changed; 212 } 213 214 void getAnalysisUsage(AnalysisUsage &AU) const override { 215 AU.addRequired<LiveIntervals>(); 216 AU.addPreserved<LiveIntervals>(); 217 AU.addRequired<SlotIndexes>(); 218 AU.addPreserved<SlotIndexes>(); 219 MachineFunctionPass::getAnalysisUsage(AU); 220 } 221 }; 222 } 223 224 INITIALIZE_PASS_BEGIN(PPCTLSDynamicCall, DEBUG_TYPE, 225 "PowerPC TLS Dynamic Call Fixup", false, false) 226 INITIALIZE_PASS_DEPENDENCY(LiveIntervals) 227 INITIALIZE_PASS_DEPENDENCY(SlotIndexes) 228 INITIALIZE_PASS_END(PPCTLSDynamicCall, DEBUG_TYPE, 229 "PowerPC TLS Dynamic Call Fixup", false, false) 230 231 char PPCTLSDynamicCall::ID = 0; 232 FunctionPass* 233 llvm::createPPCTLSDynamicCallPass() { return new PPCTLSDynamicCall(); } 234