1 //===-- PPCSubtarget.h - Define Subtarget for the PPC ----------*- C++ -*--===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file declares the PowerPC specific subclass of TargetSubtargetInfo.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef POWERPCSUBTARGET_H
15 #define POWERPCSUBTARGET_H
16 
17 #include "PPCFrameLowering.h"
18 #include "PPCInstrInfo.h"
19 #include "PPCISelLowering.h"
20 #include "PPCJITInfo.h"
21 #include "PPCSelectionDAGInfo.h"
22 #include "llvm/ADT/Triple.h"
23 #include "llvm/IR/DataLayout.h"
24 #include "llvm/MC/MCInstrItineraries.h"
25 #include "llvm/Target/TargetSubtargetInfo.h"
26 #include <string>
27 
28 #define GET_SUBTARGETINFO_HEADER
29 #include "PPCGenSubtargetInfo.inc"
30 
31 // GCC #defines PPC on Linux but we use it as our namespace name
32 #undef PPC
33 
34 namespace llvm {
35 class StringRef;
36 
37 namespace PPC {
38   // -m directive values.
39   enum {
40     DIR_NONE,
41     DIR_32,
42     DIR_440,
43     DIR_601,
44     DIR_602,
45     DIR_603,
46     DIR_7400,
47     DIR_750,
48     DIR_970,
49     DIR_A2,
50     DIR_E500mc,
51     DIR_E5500,
52     DIR_PWR3,
53     DIR_PWR4,
54     DIR_PWR5,
55     DIR_PWR5X,
56     DIR_PWR6,
57     DIR_PWR6X,
58     DIR_PWR7,
59     DIR_PWR8,
60     DIR_64
61   };
62 }
63 
64 class GlobalValue;
65 class TargetMachine;
66 
67 class PPCSubtarget : public PPCGenSubtargetInfo {
68 protected:
69   /// TargetTriple - What processor and OS we're targeting.
70   Triple TargetTriple;
71 
72   // Calculates type size & alignment
73   const DataLayout DL;
74 
75   /// stackAlignment - The minimum alignment known to hold of the stack frame on
76   /// entry to the function and which must be maintained by every function.
77   unsigned StackAlignment;
78 
79   /// Selected instruction itineraries (one entry per itinerary class.)
80   InstrItineraryData InstrItins;
81 
82   /// Which cpu directive was used.
83   unsigned DarwinDirective;
84 
85   /// Used by the ISel to turn in optimizations for POWER4-derived architectures
86   bool HasMFOCRF;
87   bool Has64BitSupport;
88   bool Use64BitRegs;
89   bool UseCRBits;
90   bool IsPPC64;
91   bool HasAltivec;
92   bool HasSPE;
93   bool HasQPX;
94   bool HasVSX;
95   bool HasFCPSGN;
96   bool HasFSQRT;
97   bool HasFRE, HasFRES, HasFRSQRTE, HasFRSQRTES;
98   bool HasRecipPrec;
99   bool HasSTFIWX;
100   bool HasLFIWAX;
101   bool HasFPRND;
102   bool HasFPCVT;
103   bool HasISEL;
104   bool HasPOPCNTD;
105   bool HasLDBRX;
106   bool IsBookE;
107   bool IsE500;
108   bool IsPPC4xx;
109   bool IsPPC6xx;
110   bool DeprecatedMFTB;
111   bool DeprecatedDST;
112   bool HasLazyResolverStubs;
113   bool IsJITCodeModel;
114   bool IsLittleEndian;
115 
116   /// OptLevel - What default optimization level we're emitting code for.
117   CodeGenOpt::Level OptLevel;
118 
119   enum {
120     PPC_ABI_UNKNOWN,
121     PPC_ABI_ELFv1,
122     PPC_ABI_ELFv2
123   } TargetABI;
124 
125   PPCFrameLowering FrameLowering;
126   PPCInstrInfo InstrInfo;
127   PPCJITInfo JITInfo;
128   PPCTargetLowering TLInfo;
129   PPCSelectionDAGInfo TSInfo;
130 
131 public:
132   /// This constructor initializes the data members to match that
133   /// of the specified triple.
134   ///
135   PPCSubtarget(const std::string &TT, const std::string &CPU,
136                const std::string &FS, PPCTargetMachine &TM,
137                CodeGenOpt::Level OptLevel);
138 
139   /// ParseSubtargetFeatures - Parses features string setting specified
140   /// subtarget options.  Definition of function is auto generated by tblgen.
141   void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
142 
143   /// SetJITMode - This is called to inform the subtarget info that we are
144   /// producing code for the JIT.
145   void SetJITMode();
146 
147   /// getStackAlignment - Returns the minimum alignment known to hold of the
148   /// stack frame on entry to the function and which must be maintained by every
149   /// function for this subtarget.
150   unsigned getStackAlignment() const { return StackAlignment; }
151 
152   /// getDarwinDirective - Returns the -m directive specified for the cpu.
153   ///
154   unsigned getDarwinDirective() const { return DarwinDirective; }
155 
156   /// getInstrItins - Return the instruction itineraries based on subtarget
157   /// selection.
158   const InstrItineraryData *getInstrItineraryData() const override {
159     return &InstrItins;
160   }
161 
162   const PPCFrameLowering *getFrameLowering() const override {
163     return &FrameLowering;
164   }
165   const DataLayout *getDataLayout() const override { return &DL; }
166   const PPCInstrInfo *getInstrInfo() const override { return &InstrInfo; }
167   PPCJITInfo *getJITInfo() override { return &JITInfo; }
168   const PPCTargetLowering *getTargetLowering() const override {
169     return &TLInfo;
170   }
171   const PPCSelectionDAGInfo *getSelectionDAGInfo() const override {
172     return &TSInfo;
173   }
174   const PPCRegisterInfo *getRegisterInfo() const override {
175     return &getInstrInfo()->getRegisterInfo();
176   }
177 
178   /// initializeSubtargetDependencies - Initializes using a CPU and feature string
179   /// so that we can use initializer lists for subtarget initialization.
180   PPCSubtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS);
181 
182   /// \brief Reset the features for the PowerPC target.
183   void resetSubtargetFeatures(const MachineFunction *MF) override;
184 private:
185   void initializeEnvironment();
186   void resetSubtargetFeatures(StringRef CPU, StringRef FS);
187 
188 public:
189   /// isPPC64 - Return true if we are generating code for 64-bit pointer mode.
190   ///
191   bool isPPC64() const { return IsPPC64; }
192 
193   /// has64BitSupport - Return true if the selected CPU supports 64-bit
194   /// instructions, regardless of whether we are in 32-bit or 64-bit mode.
195   bool has64BitSupport() const { return Has64BitSupport; }
196 
197   /// use64BitRegs - Return true if in 64-bit mode or if we should use 64-bit
198   /// registers in 32-bit mode when possible.  This can only true if
199   /// has64BitSupport() returns true.
200   bool use64BitRegs() const { return Use64BitRegs; }
201 
202   /// useCRBits - Return true if we should store and manipulate i1 values in
203   /// the individual condition register bits.
204   bool useCRBits() const { return UseCRBits; }
205 
206   /// hasLazyResolverStub - Return true if accesses to the specified global have
207   /// to go through a dyld lazy resolution stub.  This means that an extra load
208   /// is required to get the address of the global.
209   bool hasLazyResolverStub(const GlobalValue *GV,
210                            const TargetMachine &TM) const;
211 
212   // isJITCodeModel - True if we're generating code for the JIT
213   bool isJITCodeModel() const { return IsJITCodeModel; }
214 
215   // isLittleEndian - True if generating little-endian code
216   bool isLittleEndian() const { return IsLittleEndian; }
217 
218   // Specific obvious features.
219   bool hasFCPSGN() const { return HasFCPSGN; }
220   bool hasFSQRT() const { return HasFSQRT; }
221   bool hasFRE() const { return HasFRE; }
222   bool hasFRES() const { return HasFRES; }
223   bool hasFRSQRTE() const { return HasFRSQRTE; }
224   bool hasFRSQRTES() const { return HasFRSQRTES; }
225   bool hasRecipPrec() const { return HasRecipPrec; }
226   bool hasSTFIWX() const { return HasSTFIWX; }
227   bool hasLFIWAX() const { return HasLFIWAX; }
228   bool hasFPRND() const { return HasFPRND; }
229   bool hasFPCVT() const { return HasFPCVT; }
230   bool hasAltivec() const { return HasAltivec; }
231   bool hasSPE() const { return HasSPE; }
232   bool hasQPX() const { return HasQPX; }
233   bool hasVSX() const { return HasVSX; }
234   bool hasMFOCRF() const { return HasMFOCRF; }
235   bool hasISEL() const { return HasISEL; }
236   bool hasPOPCNTD() const { return HasPOPCNTD; }
237   bool hasLDBRX() const { return HasLDBRX; }
238   bool isBookE() const { return IsBookE; }
239   bool isPPC4xx() const { return IsPPC4xx; }
240   bool isPPC6xx() const { return IsPPC6xx; }
241   bool isE500() const { return IsE500; }
242   bool isDeprecatedMFTB() const { return DeprecatedMFTB; }
243   bool isDeprecatedDST() const { return DeprecatedDST; }
244 
245   const Triple &getTargetTriple() const { return TargetTriple; }
246 
247   /// isDarwin - True if this is any darwin platform.
248   bool isDarwin() const { return TargetTriple.isMacOSX(); }
249   /// isBGQ - True if this is a BG/Q platform.
250   bool isBGQ() const { return TargetTriple.getVendor() == Triple::BGQ; }
251 
252   bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
253   bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); }
254 
255   bool isDarwinABI() const { return isDarwin(); }
256   bool isSVR4ABI() const { return !isDarwin(); }
257   bool isELFv2ABI() const { return TargetABI == PPC_ABI_ELFv2; }
258 
259   bool enableEarlyIfConversion() const override { return hasISEL(); }
260 
261   // Scheduling customization.
262   bool enableMachineScheduler() const override;
263   // This overrides the PostRAScheduler bit in the SchedModel for each CPU.
264   bool enablePostMachineScheduler() const override;
265   AntiDepBreakMode getAntiDepBreakMode() const override;
266   void getCriticalPathRCs(RegClassVector &CriticalPathRCs) const override;
267 
268   void overrideSchedPolicy(MachineSchedPolicy &Policy,
269                            MachineInstr *begin,
270                            MachineInstr *end,
271                            unsigned NumRegionInstrs) const override;
272   bool useAA() const override;
273 };
274 } // End llvm namespace
275 
276 #endif
277