1 //===-- PPCSubtarget.h - Define Subtarget for the PPC ----------*- C++ -*--===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file declares the PowerPC specific subclass of TargetSubtargetInfo.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_TARGET_POWERPC_PPCSUBTARGET_H
14 #define LLVM_LIB_TARGET_POWERPC_PPCSUBTARGET_H
15 
16 #include "PPCFrameLowering.h"
17 #include "PPCISelLowering.h"
18 #include "PPCInstrInfo.h"
19 #include "llvm/ADT/Triple.h"
20 #include "llvm/CodeGen/GlobalISel/CallLowering.h"
21 #include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
22 #include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
23 #include "llvm/CodeGen/SelectionDAGTargetInfo.h"
24 #include "llvm/CodeGen/TargetSubtargetInfo.h"
25 #include "llvm/IR/DataLayout.h"
26 #include "llvm/MC/MCInstrItineraries.h"
27 #include <string>
28 
29 #define GET_SUBTARGETINFO_HEADER
30 #include "PPCGenSubtargetInfo.inc"
31 
32 // GCC #defines PPC on Linux but we use it as our namespace name
33 #undef PPC
34 
35 namespace llvm {
36 class StringRef;
37 
38 namespace PPC {
39   // -m directive values.
40 enum {
41   DIR_NONE,
42   DIR_32,
43   DIR_440,
44   DIR_601,
45   DIR_602,
46   DIR_603,
47   DIR_7400,
48   DIR_750,
49   DIR_970,
50   DIR_A2,
51   DIR_E500,
52   DIR_E500mc,
53   DIR_E5500,
54   DIR_PWR3,
55   DIR_PWR4,
56   DIR_PWR5,
57   DIR_PWR5X,
58   DIR_PWR6,
59   DIR_PWR6X,
60   DIR_PWR7,
61   DIR_PWR8,
62   DIR_PWR9,
63   DIR_PWR10,
64   DIR_PWR_FUTURE,
65   DIR_64
66 };
67 }
68 
69 class GlobalValue;
70 
71 class PPCSubtarget : public PPCGenSubtargetInfo {
72 public:
73   enum POPCNTDKind {
74     POPCNTD_Unavailable,
75     POPCNTD_Slow,
76     POPCNTD_Fast
77   };
78 
79 protected:
80   /// TargetTriple - What processor and OS we're targeting.
81   Triple TargetTriple;
82 
83   /// stackAlignment - The minimum alignment known to hold of the stack frame on
84   /// entry to the function and which must be maintained by every function.
85   Align StackAlignment;
86 
87   /// Selected instruction itineraries (one entry per itinerary class.)
88   InstrItineraryData InstrItins;
89 
90   /// Which cpu directive was used.
91   unsigned CPUDirective;
92 
93   /// Used by the ISel to turn in optimizations for POWER4-derived architectures
94   bool HasMFOCRF;
95   bool Has64BitSupport;
96   bool Use64BitRegs;
97   bool UseCRBits;
98   bool HasHardFloat;
99   bool IsPPC64;
100   bool HasAltivec;
101   bool HasFPU;
102   bool HasSPE;
103   bool HasEFPU2;
104   bool HasVSX;
105   bool NeedsTwoConstNR;
106   bool HasP8Vector;
107   bool HasP8Altivec;
108   bool HasP8Crypto;
109   bool HasP9Vector;
110   bool HasP9Altivec;
111   bool HasP10Vector;
112   bool HasPrefixInstrs;
113   bool HasPCRelativeMemops;
114   bool HasMMA;
115   bool HasROPProtection;
116   bool HasFCPSGN;
117   bool HasFSQRT;
118   bool HasFRE, HasFRES, HasFRSQRTE, HasFRSQRTES;
119   bool HasRecipPrec;
120   bool HasSTFIWX;
121   bool HasLFIWAX;
122   bool HasFPRND;
123   bool HasFPCVT;
124   bool HasISEL;
125   bool HasBPERMD;
126   bool HasExtDiv;
127   bool HasCMPB;
128   bool HasLDBRX;
129   bool IsBookE;
130   bool HasOnlyMSYNC;
131   bool IsE500;
132   bool IsPPC4xx;
133   bool IsPPC6xx;
134   bool FeatureMFTB;
135   bool AllowsUnalignedFPAccess;
136   bool DeprecatedDST;
137   bool IsLittleEndian;
138   bool HasICBT;
139   bool HasInvariantFunctionDescriptors;
140   bool HasPartwordAtomics;
141   bool HasDirectMove;
142   bool HasHTM;
143   bool HasFloat128;
144   bool HasFusion;
145   bool HasStoreFusion;
146   bool HasAddiLoadFusion;
147   bool HasAddisLoadFusion;
148   bool IsISA3_0;
149   bool IsISA3_1;
150   bool UseLongCalls;
151   bool SecurePlt;
152   bool VectorsUseTwoUnits;
153   bool UsePPCPreRASchedStrategy;
154   bool UsePPCPostRASchedStrategy;
155   bool PairedVectorMemops;
156   bool PredictableSelectIsExpensive;
157   bool HasModernAIXAs;
158   bool IsAIX;
159 
160   POPCNTDKind HasPOPCNTD;
161 
162   const PPCTargetMachine &TM;
163   PPCFrameLowering FrameLowering;
164   PPCInstrInfo InstrInfo;
165   PPCTargetLowering TLInfo;
166   SelectionDAGTargetInfo TSInfo;
167 
168   /// GlobalISel related APIs.
169   std::unique_ptr<CallLowering> CallLoweringInfo;
170   std::unique_ptr<LegalizerInfo> Legalizer;
171   std::unique_ptr<RegisterBankInfo> RegBankInfo;
172   std::unique_ptr<InstructionSelector> InstSelector;
173 
174 public:
175   /// This constructor initializes the data members to match that
176   /// of the specified triple.
177   ///
178   PPCSubtarget(const Triple &TT, const std::string &CPU, const std::string &FS,
179                const PPCTargetMachine &TM);
180 
181   /// ParseSubtargetFeatures - Parses features string setting specified
182   /// subtarget options.  Definition of function is auto generated by tblgen.
183   void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS);
184 
185   /// getStackAlignment - Returns the minimum alignment known to hold of the
186   /// stack frame on entry to the function and which must be maintained by every
187   /// function for this subtarget.
188   Align getStackAlignment() const { return StackAlignment; }
189 
190   /// getCPUDirective - Returns the -m directive specified for the cpu.
191   ///
192   unsigned getCPUDirective() const { return CPUDirective; }
193 
194   /// getInstrItins - Return the instruction itineraries based on subtarget
195   /// selection.
196   const InstrItineraryData *getInstrItineraryData() const override {
197     return &InstrItins;
198   }
199 
200   const PPCFrameLowering *getFrameLowering() const override {
201     return &FrameLowering;
202   }
203   const PPCInstrInfo *getInstrInfo() const override { return &InstrInfo; }
204   const PPCTargetLowering *getTargetLowering() const override {
205     return &TLInfo;
206   }
207   const SelectionDAGTargetInfo *getSelectionDAGInfo() const override {
208     return &TSInfo;
209   }
210   const PPCRegisterInfo *getRegisterInfo() const override {
211     return &getInstrInfo()->getRegisterInfo();
212   }
213   const PPCTargetMachine &getTargetMachine() const { return TM; }
214 
215   /// initializeSubtargetDependencies - Initializes using a CPU and feature string
216   /// so that we can use initializer lists for subtarget initialization.
217   PPCSubtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS);
218 
219 private:
220   void initializeEnvironment();
221   void initSubtargetFeatures(StringRef CPU, StringRef FS);
222 
223 public:
224   /// isPPC64 - Return true if we are generating code for 64-bit pointer mode.
225   ///
226   bool isPPC64() const;
227 
228   /// has64BitSupport - Return true if the selected CPU supports 64-bit
229   /// instructions, regardless of whether we are in 32-bit or 64-bit mode.
230   bool has64BitSupport() const { return Has64BitSupport; }
231   // useSoftFloat - Return true if soft-float option is turned on.
232   bool useSoftFloat() const {
233     if (isAIXABI() && !HasHardFloat)
234       report_fatal_error("soft-float is not yet supported on AIX.");
235     return !HasHardFloat;
236   }
237 
238   /// use64BitRegs - Return true if in 64-bit mode or if we should use 64-bit
239   /// registers in 32-bit mode when possible.  This can only true if
240   /// has64BitSupport() returns true.
241   bool use64BitRegs() const { return Use64BitRegs; }
242 
243   /// useCRBits - Return true if we should store and manipulate i1 values in
244   /// the individual condition register bits.
245   bool useCRBits() const { return UseCRBits; }
246 
247   // isLittleEndian - True if generating little-endian code
248   bool isLittleEndian() const { return IsLittleEndian; }
249 
250   // Specific obvious features.
251   bool hasFCPSGN() const { return HasFCPSGN; }
252   bool hasFSQRT() const { return HasFSQRT; }
253   bool hasFRE() const { return HasFRE; }
254   bool hasFRES() const { return HasFRES; }
255   bool hasFRSQRTE() const { return HasFRSQRTE; }
256   bool hasFRSQRTES() const { return HasFRSQRTES; }
257   bool hasRecipPrec() const { return HasRecipPrec; }
258   bool hasSTFIWX() const { return HasSTFIWX; }
259   bool hasLFIWAX() const { return HasLFIWAX; }
260   bool hasFPRND() const { return HasFPRND; }
261   bool hasFPCVT() const { return HasFPCVT; }
262   bool hasAltivec() const { return HasAltivec; }
263   bool hasSPE() const { return HasSPE; }
264   bool hasEFPU2() const { return HasEFPU2; }
265   bool hasFPU() const { return HasFPU; }
266   bool hasVSX() const { return HasVSX; }
267   bool needsTwoConstNR() const { return NeedsTwoConstNR; }
268   bool hasP8Vector() const { return HasP8Vector; }
269   bool hasP8Altivec() const { return HasP8Altivec; }
270   bool hasP8Crypto() const { return HasP8Crypto; }
271   bool hasP9Vector() const { return HasP9Vector; }
272   bool hasP9Altivec() const { return HasP9Altivec; }
273   bool hasP10Vector() const { return HasP10Vector; }
274   bool hasPrefixInstrs() const { return HasPrefixInstrs; }
275   bool hasPCRelativeMemops() const { return HasPCRelativeMemops; }
276   bool hasMMA() const { return HasMMA; }
277   bool hasROPProtection() const { return HasROPProtection; }
278   bool pairedVectorMemops() const { return PairedVectorMemops; }
279   bool hasMFOCRF() const { return HasMFOCRF; }
280   bool hasISEL() const { return HasISEL; }
281   bool hasBPERMD() const { return HasBPERMD; }
282   bool hasExtDiv() const { return HasExtDiv; }
283   bool hasCMPB() const { return HasCMPB; }
284   bool hasLDBRX() const { return HasLDBRX; }
285   bool isBookE() const { return IsBookE; }
286   bool hasOnlyMSYNC() const { return HasOnlyMSYNC; }
287   bool isPPC4xx() const { return IsPPC4xx; }
288   bool isPPC6xx() const { return IsPPC6xx; }
289   bool isSecurePlt() const {return SecurePlt; }
290   bool vectorsUseTwoUnits() const {return VectorsUseTwoUnits; }
291   bool isE500() const { return IsE500; }
292   bool isFeatureMFTB() const { return FeatureMFTB; }
293   bool allowsUnalignedFPAccess() const { return AllowsUnalignedFPAccess; }
294   bool isDeprecatedDST() const { return DeprecatedDST; }
295   bool hasICBT() const { return HasICBT; }
296   bool hasInvariantFunctionDescriptors() const {
297     return HasInvariantFunctionDescriptors;
298   }
299   bool usePPCPreRASchedStrategy() const { return UsePPCPreRASchedStrategy; }
300   bool usePPCPostRASchedStrategy() const { return UsePPCPostRASchedStrategy; }
301   bool hasPartwordAtomics() const { return HasPartwordAtomics; }
302   bool hasDirectMove() const { return HasDirectMove; }
303 
304   Align getPlatformStackAlignment() const {
305     return Align(16);
306   }
307 
308   unsigned  getRedZoneSize() const {
309     if (isPPC64())
310       // 288 bytes = 18*8 (FPRs) + 18*8 (GPRs, GPR13 reserved)
311       return 288;
312 
313     // AIX PPC32: 220 bytes = 18*8 (FPRs) + 19*4 (GPRs);
314     // PPC32 SVR4ABI has no redzone.
315     return isAIXABI() ? 220 : 0;
316   }
317 
318   bool hasHTM() const { return HasHTM; }
319   bool hasFloat128() const { return HasFloat128; }
320   bool isISA3_0() const { return IsISA3_0; }
321   bool isISA3_1() const { return IsISA3_1; }
322   bool useLongCalls() const { return UseLongCalls; }
323   bool hasFusion() const { return HasFusion; }
324   bool hasStoreFusion() const { return HasStoreFusion; }
325   bool hasAddiLoadFusion() const { return HasAddiLoadFusion; }
326   bool hasAddisLoadFusion() const { return HasAddisLoadFusion; }
327   bool needsSwapsForVSXMemOps() const {
328     return hasVSX() && isLittleEndian() && !hasP9Vector();
329   }
330 
331   POPCNTDKind hasPOPCNTD() const { return HasPOPCNTD; }
332 
333   const Triple &getTargetTriple() const { return TargetTriple; }
334 
335   bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
336   bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); }
337   bool isTargetLinux() const { return TargetTriple.isOSLinux(); }
338 
339   bool isAIXABI() const { return TargetTriple.isOSAIX(); }
340   bool isSVR4ABI() const { return !isAIXABI(); }
341   bool isELFv2ABI() const;
342 
343   bool is64BitELFABI() const { return  isSVR4ABI() && isPPC64(); }
344   bool is32BitELFABI() const { return  isSVR4ABI() && !isPPC64(); }
345   bool isUsingPCRelativeCalls() const;
346 
347   /// Originally, this function return hasISEL(). Now we always enable it,
348   /// but may expand the ISEL instruction later.
349   bool enableEarlyIfConversion() const override { return true; }
350 
351   /// Scheduling customization.
352   bool enableMachineScheduler() const override;
353   /// Pipeliner customization.
354   bool enableMachinePipeliner() const override;
355   /// Machine Pipeliner customization
356   bool useDFAforSMS() const override;
357   /// This overrides the PostRAScheduler bit in the SchedModel for each CPU.
358   bool enablePostRAScheduler() const override;
359   AntiDepBreakMode getAntiDepBreakMode() const override;
360   void getCriticalPathRCs(RegClassVector &CriticalPathRCs) const override;
361 
362   void overrideSchedPolicy(MachineSchedPolicy &Policy,
363                            unsigned NumRegionInstrs) const override;
364   bool useAA() const override;
365 
366   bool enableSubRegLiveness() const override;
367 
368   /// True if the GV will be accessed via an indirect symbol.
369   bool isGVIndirectSymbol(const GlobalValue *GV) const;
370 
371   /// True if the ABI is descriptor based.
372   bool usesFunctionDescriptors() const {
373     // Both 32-bit and 64-bit AIX are descriptor based. For ELF only the 64-bit
374     // v1 ABI uses descriptors.
375     return isAIXABI() || (is64BitELFABI() && !isELFv2ABI());
376   }
377 
378   unsigned descriptorTOCAnchorOffset() const {
379     assert(usesFunctionDescriptors() &&
380            "Should only be called when the target uses descriptors.");
381     return IsPPC64 ? 8 : 4;
382   }
383 
384   unsigned descriptorEnvironmentPointerOffset() const {
385     assert(usesFunctionDescriptors() &&
386            "Should only be called when the target uses descriptors.");
387     return IsPPC64 ? 16 : 8;
388   }
389 
390   MCRegister getEnvironmentPointerRegister() const {
391     assert(usesFunctionDescriptors() &&
392            "Should only be called when the target uses descriptors.");
393      return IsPPC64 ? PPC::X11 : PPC::R11;
394   }
395 
396   MCRegister getTOCPointerRegister() const {
397     assert((is64BitELFABI() || isAIXABI()) &&
398            "Should only be called when the target is a TOC based ABI.");
399     return IsPPC64 ? PPC::X2 : PPC::R2;
400   }
401 
402   MCRegister getStackPointerRegister() const {
403     return IsPPC64 ? PPC::X1 : PPC::R1;
404   }
405 
406   bool isXRaySupported() const override { return IsPPC64 && IsLittleEndian; }
407 
408   bool isPredictableSelectIsExpensive() const {
409     return PredictableSelectIsExpensive;
410   }
411 
412   // GlobalISEL
413   const CallLowering *getCallLowering() const override;
414   const RegisterBankInfo *getRegBankInfo() const override;
415   const LegalizerInfo *getLegalizerInfo() const override;
416   InstructionSelector *getInstructionSelector() const override;
417 };
418 } // End llvm namespace
419 
420 #endif
421