1 //===-- PPCSubtarget.h - Define Subtarget for the PPC ----------*- C++ -*--===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file declares the PowerPC specific subclass of TargetSubtargetInfo.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_TARGET_POWERPC_PPCSUBTARGET_H
14 #define LLVM_LIB_TARGET_POWERPC_PPCSUBTARGET_H
15 
16 #include "PPCFrameLowering.h"
17 #include "PPCISelLowering.h"
18 #include "PPCInstrInfo.h"
19 #include "llvm/ADT/Triple.h"
20 #include "llvm/CodeGen/SelectionDAGTargetInfo.h"
21 #include "llvm/CodeGen/TargetSubtargetInfo.h"
22 #include "llvm/IR/DataLayout.h"
23 #include "llvm/MC/MCInstrItineraries.h"
24 #include <string>
25 
26 #define GET_SUBTARGETINFO_HEADER
27 #include "PPCGenSubtargetInfo.inc"
28 
29 // GCC #defines PPC on Linux but we use it as our namespace name
30 #undef PPC
31 
32 namespace llvm {
33 class StringRef;
34 
35 namespace PPC {
36   // -m directive values.
37   enum {
38     DIR_NONE,
39     DIR_32,
40     DIR_440,
41     DIR_601,
42     DIR_602,
43     DIR_603,
44     DIR_7400,
45     DIR_750,
46     DIR_970,
47     DIR_A2,
48     DIR_E500,
49     DIR_E500mc,
50     DIR_E5500,
51     DIR_PWR3,
52     DIR_PWR4,
53     DIR_PWR5,
54     DIR_PWR5X,
55     DIR_PWR6,
56     DIR_PWR6X,
57     DIR_PWR7,
58     DIR_PWR8,
59     DIR_PWR9,
60     DIR_PWR_FUTURE,
61     DIR_64
62   };
63 }
64 
65 class GlobalValue;
66 class TargetMachine;
67 
68 class PPCSubtarget : public PPCGenSubtargetInfo {
69 public:
70   enum POPCNTDKind {
71     POPCNTD_Unavailable,
72     POPCNTD_Slow,
73     POPCNTD_Fast
74   };
75 
76 protected:
77   /// TargetTriple - What processor and OS we're targeting.
78   Triple TargetTriple;
79 
80   /// stackAlignment - The minimum alignment known to hold of the stack frame on
81   /// entry to the function and which must be maintained by every function.
82   Align StackAlignment;
83 
84   /// Selected instruction itineraries (one entry per itinerary class.)
85   InstrItineraryData InstrItins;
86 
87   /// Which cpu directive was used.
88   unsigned CPUDirective;
89 
90   /// Used by the ISel to turn in optimizations for POWER4-derived architectures
91   bool HasMFOCRF;
92   bool Has64BitSupport;
93   bool Use64BitRegs;
94   bool UseCRBits;
95   bool HasHardFloat;
96   bool IsPPC64;
97   bool HasAltivec;
98   bool HasFPU;
99   bool HasSPE;
100   bool HasQPX;
101   bool HasVSX;
102   bool NeedsTwoConstNR;
103   bool HasP8Vector;
104   bool HasP8Altivec;
105   bool HasP8Crypto;
106   bool HasP9Vector;
107   bool HasP9Altivec;
108   bool HasPrefixInstrs;
109   bool HasPCRelativeMemops;
110   bool HasFCPSGN;
111   bool HasFSQRT;
112   bool HasFRE, HasFRES, HasFRSQRTE, HasFRSQRTES;
113   bool HasRecipPrec;
114   bool HasSTFIWX;
115   bool HasLFIWAX;
116   bool HasFPRND;
117   bool HasFPCVT;
118   bool HasISEL;
119   bool HasBPERMD;
120   bool HasExtDiv;
121   bool HasCMPB;
122   bool HasLDBRX;
123   bool IsBookE;
124   bool HasOnlyMSYNC;
125   bool IsE500;
126   bool IsPPC4xx;
127   bool IsPPC6xx;
128   bool FeatureMFTB;
129   bool AllowsUnalignedFPAccess;
130   bool DeprecatedDST;
131   bool IsLittleEndian;
132   bool HasICBT;
133   bool HasInvariantFunctionDescriptors;
134   bool HasPartwordAtomics;
135   bool HasDirectMove;
136   bool HasHTM;
137   bool HasFloat128;
138   bool HasFusion;
139   bool HasAddiLoadFusion;
140   bool HasAddisLoadFusion;
141   bool IsISA3_0;
142   bool UseLongCalls;
143   bool SecurePlt;
144   bool VectorsUseTwoUnits;
145   bool UsePPCPreRASchedStrategy;
146   bool UsePPCPostRASchedStrategy;
147 
148   POPCNTDKind HasPOPCNTD;
149 
150   /// When targeting QPX running a stock PPC64 Linux kernel where the stack
151   /// alignment has not been changed, we need to keep the 16-byte alignment
152   /// of the stack.
153   bool IsQPXStackUnaligned;
154 
155   const PPCTargetMachine &TM;
156   PPCFrameLowering FrameLowering;
157   PPCInstrInfo InstrInfo;
158   PPCTargetLowering TLInfo;
159   SelectionDAGTargetInfo TSInfo;
160 
161 public:
162   /// This constructor initializes the data members to match that
163   /// of the specified triple.
164   ///
165   PPCSubtarget(const Triple &TT, const std::string &CPU, const std::string &FS,
166                const PPCTargetMachine &TM);
167 
168   /// ParseSubtargetFeatures - Parses features string setting specified
169   /// subtarget options.  Definition of function is auto generated by tblgen.
170   void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
171 
172   /// getStackAlignment - Returns the minimum alignment known to hold of the
173   /// stack frame on entry to the function and which must be maintained by every
174   /// function for this subtarget.
175   Align getStackAlignment() const { return StackAlignment; }
176 
177   /// getDarwinDirective - Returns the -m directive specified for the cpu.
178   unsigned getDarwinDirective() const { return CPUDirective; }
179 
180   /// getCPUDirective - Returns the -m directive specified for the cpu.
181   ///
182   unsigned getCPUDirective() const { return CPUDirective; }
183 
184   /// getInstrItins - Return the instruction itineraries based on subtarget
185   /// selection.
186   const InstrItineraryData *getInstrItineraryData() const override {
187     return &InstrItins;
188   }
189 
190   const PPCFrameLowering *getFrameLowering() const override {
191     return &FrameLowering;
192   }
193   const PPCInstrInfo *getInstrInfo() const override { return &InstrInfo; }
194   const PPCTargetLowering *getTargetLowering() const override {
195     return &TLInfo;
196   }
197   const SelectionDAGTargetInfo *getSelectionDAGInfo() const override {
198     return &TSInfo;
199   }
200   const PPCRegisterInfo *getRegisterInfo() const override {
201     return &getInstrInfo()->getRegisterInfo();
202   }
203   const PPCTargetMachine &getTargetMachine() const { return TM; }
204 
205   /// initializeSubtargetDependencies - Initializes using a CPU and feature string
206   /// so that we can use initializer lists for subtarget initialization.
207   PPCSubtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS);
208 
209 private:
210   void initializeEnvironment();
211   void initSubtargetFeatures(StringRef CPU, StringRef FS);
212 
213 public:
214   /// isPPC64 - Return true if we are generating code for 64-bit pointer mode.
215   ///
216   bool isPPC64() const;
217 
218   /// has64BitSupport - Return true if the selected CPU supports 64-bit
219   /// instructions, regardless of whether we are in 32-bit or 64-bit mode.
220   bool has64BitSupport() const { return Has64BitSupport; }
221   // useSoftFloat - Return true if soft-float option is turned on.
222   bool useSoftFloat() const {
223     if (isAIXABI() && !HasHardFloat)
224       report_fatal_error("soft-float is not yet supported on AIX.");
225     return !HasHardFloat;
226   }
227 
228   /// use64BitRegs - Return true if in 64-bit mode or if we should use 64-bit
229   /// registers in 32-bit mode when possible.  This can only true if
230   /// has64BitSupport() returns true.
231   bool use64BitRegs() const { return Use64BitRegs; }
232 
233   /// useCRBits - Return true if we should store and manipulate i1 values in
234   /// the individual condition register bits.
235   bool useCRBits() const { return UseCRBits; }
236 
237   // isLittleEndian - True if generating little-endian code
238   bool isLittleEndian() const { return IsLittleEndian; }
239 
240   // Specific obvious features.
241   bool hasFCPSGN() const { return HasFCPSGN; }
242   bool hasFSQRT() const { return HasFSQRT; }
243   bool hasFRE() const { return HasFRE; }
244   bool hasFRES() const { return HasFRES; }
245   bool hasFRSQRTE() const { return HasFRSQRTE; }
246   bool hasFRSQRTES() const { return HasFRSQRTES; }
247   bool hasRecipPrec() const { return HasRecipPrec; }
248   bool hasSTFIWX() const { return HasSTFIWX; }
249   bool hasLFIWAX() const { return HasLFIWAX; }
250   bool hasFPRND() const { return HasFPRND; }
251   bool hasFPCVT() const { return HasFPCVT; }
252   bool hasAltivec() const { return HasAltivec; }
253   bool hasSPE() const { return HasSPE; }
254   bool hasFPU() const { return HasFPU; }
255   bool hasQPX() const { return HasQPX; }
256   bool hasVSX() const { return HasVSX; }
257   bool needsTwoConstNR() const { return NeedsTwoConstNR; }
258   bool hasP8Vector() const { return HasP8Vector; }
259   bool hasP8Altivec() const { return HasP8Altivec; }
260   bool hasP8Crypto() const { return HasP8Crypto; }
261   bool hasP9Vector() const { return HasP9Vector; }
262   bool hasP9Altivec() const { return HasP9Altivec; }
263   bool hasPrefixInstrs() const { return HasPrefixInstrs; }
264   bool hasPCRelativeMemops() const { return HasPCRelativeMemops; }
265   bool hasMFOCRF() const { return HasMFOCRF; }
266   bool hasISEL() const { return HasISEL; }
267   bool hasBPERMD() const { return HasBPERMD; }
268   bool hasExtDiv() const { return HasExtDiv; }
269   bool hasCMPB() const { return HasCMPB; }
270   bool hasLDBRX() const { return HasLDBRX; }
271   bool isBookE() const { return IsBookE; }
272   bool hasOnlyMSYNC() const { return HasOnlyMSYNC; }
273   bool isPPC4xx() const { return IsPPC4xx; }
274   bool isPPC6xx() const { return IsPPC6xx; }
275   bool isSecurePlt() const {return SecurePlt; }
276   bool vectorsUseTwoUnits() const {return VectorsUseTwoUnits; }
277   bool isE500() const { return IsE500; }
278   bool isFeatureMFTB() const { return FeatureMFTB; }
279   bool allowsUnalignedFPAccess() const { return AllowsUnalignedFPAccess; }
280   bool isDeprecatedDST() const { return DeprecatedDST; }
281   bool hasICBT() const { return HasICBT; }
282   bool hasInvariantFunctionDescriptors() const {
283     return HasInvariantFunctionDescriptors;
284   }
285   bool usePPCPreRASchedStrategy() const { return UsePPCPreRASchedStrategy; }
286   bool usePPCPostRASchedStrategy() const { return UsePPCPostRASchedStrategy; }
287   bool hasPartwordAtomics() const { return HasPartwordAtomics; }
288   bool hasDirectMove() const { return HasDirectMove; }
289 
290   bool isQPXStackUnaligned() const { return IsQPXStackUnaligned; }
291   Align getPlatformStackAlignment() const {
292     if ((hasQPX() || isBGQ()) && !isQPXStackUnaligned())
293       return Align(32);
294 
295     return Align(16);
296   }
297 
298   unsigned  getRedZoneSize() const {
299     if (isPPC64())
300       // 288 bytes = 18*8 (FPRs) + 18*8 (GPRs, GPR13 reserved)
301       return 288;
302 
303     // AIX PPC32: 220 bytes = 18*8 (FPRs) + 19*4 (GPRs);
304     // PPC32 SVR4ABI has no redzone.
305     return isAIXABI() ? 220 : 0;
306   }
307 
308   bool hasHTM() const { return HasHTM; }
309   bool hasFloat128() const { return HasFloat128; }
310   bool isISA3_0() const { return IsISA3_0; }
311   bool useLongCalls() const { return UseLongCalls; }
312   bool hasFusion() const { return HasFusion; }
313   bool hasAddiLoadFusion() const { return HasAddiLoadFusion; }
314   bool hasAddisLoadFusion() const { return HasAddisLoadFusion; }
315   bool needsSwapsForVSXMemOps() const {
316     return hasVSX() && isLittleEndian() && !hasP9Vector();
317   }
318 
319   POPCNTDKind hasPOPCNTD() const { return HasPOPCNTD; }
320 
321   const Triple &getTargetTriple() const { return TargetTriple; }
322 
323   /// isBGQ - True if this is a BG/Q platform.
324   bool isBGQ() const { return TargetTriple.getVendor() == Triple::BGQ; }
325 
326   bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
327   bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); }
328   bool isTargetLinux() const { return TargetTriple.isOSLinux(); }
329 
330   bool isAIXABI() const { return TargetTriple.isOSAIX(); }
331   bool isSVR4ABI() const { return !isAIXABI(); }
332   bool isELFv2ABI() const;
333 
334   bool is64BitELFABI() const { return  isSVR4ABI() && isPPC64(); }
335   bool is32BitELFABI() const { return  isSVR4ABI() && !isPPC64(); }
336   bool isUsingPCRelativeCalls() const;
337 
338   /// Originally, this function return hasISEL(). Now we always enable it,
339   /// but may expand the ISEL instruction later.
340   bool enableEarlyIfConversion() const override { return true; }
341 
342   /// Scheduling customization.
343   bool enableMachineScheduler() const override;
344   /// Pipeliner customization.
345   bool enableMachinePipeliner() const override;
346   /// Machine Pipeliner customization
347   bool useDFAforSMS() const override;
348   /// This overrides the PostRAScheduler bit in the SchedModel for each CPU.
349   bool enablePostRAScheduler() const override;
350   AntiDepBreakMode getAntiDepBreakMode() const override;
351   void getCriticalPathRCs(RegClassVector &CriticalPathRCs) const override;
352 
353   void overrideSchedPolicy(MachineSchedPolicy &Policy,
354                            unsigned NumRegionInstrs) const override;
355   bool useAA() const override;
356 
357   bool enableSubRegLiveness() const override;
358 
359   /// True if the GV will be accessed via an indirect symbol.
360   bool isGVIndirectSymbol(const GlobalValue *GV) const;
361 
362   /// True if the ABI is descriptor based.
363   bool usesFunctionDescriptors() const {
364     // Both 32-bit and 64-bit AIX are descriptor based. For ELF only the 64-bit
365     // v1 ABI uses descriptors.
366     return isAIXABI() || (is64BitELFABI() && !isELFv2ABI());
367   }
368 
369   unsigned descriptorTOCAnchorOffset() const {
370     assert(usesFunctionDescriptors() &&
371            "Should only be called when the target uses descriptors.");
372     return IsPPC64 ? 8 : 4;
373   }
374 
375   unsigned descriptorEnvironmentPointerOffset() const {
376     assert(usesFunctionDescriptors() &&
377            "Should only be called when the target uses descriptors.");
378     return IsPPC64 ? 16 : 8;
379   }
380 
381   MCRegister getEnvironmentPointerRegister() const {
382     assert(usesFunctionDescriptors() &&
383            "Should only be called when the target uses descriptors.");
384      return IsPPC64 ? PPC::X11 : PPC::R11;
385   }
386 
387   MCRegister getTOCPointerRegister() const {
388     assert((is64BitELFABI() || isAIXABI()) &&
389            "Should only be called when the target is a TOC based ABI.");
390     return IsPPC64 ? PPC::X2 : PPC::R2;
391   }
392 
393   MCRegister getStackPointerRegister() const {
394     return IsPPC64 ? PPC::X1 : PPC::R1;
395   }
396 
397   bool isXRaySupported() const override { return IsPPC64 && IsLittleEndian; }
398 };
399 } // End llvm namespace
400 
401 #endif
402