1 //===-- PPCSubtarget.h - Define Subtarget for the PPC ----------*- C++ -*--===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file declares the PowerPC specific subclass of TargetSubtargetInfo.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_POWERPC_PPCSUBTARGET_H
15 #define LLVM_LIB_TARGET_POWERPC_PPCSUBTARGET_H
16 
17 #include "PPCFrameLowering.h"
18 #include "PPCISelLowering.h"
19 #include "PPCInstrInfo.h"
20 #include "llvm/ADT/Triple.h"
21 #include "llvm/CodeGen/SelectionDAGTargetInfo.h"
22 #include "llvm/IR/DataLayout.h"
23 #include "llvm/MC/MCInstrItineraries.h"
24 #include "llvm/Target/TargetSubtargetInfo.h"
25 #include <string>
26 
27 #define GET_SUBTARGETINFO_HEADER
28 #include "PPCGenSubtargetInfo.inc"
29 
30 // GCC #defines PPC on Linux but we use it as our namespace name
31 #undef PPC
32 
33 namespace llvm {
34 class StringRef;
35 
36 namespace PPC {
37   // -m directive values.
38   enum {
39     DIR_NONE,
40     DIR_32,
41     DIR_440,
42     DIR_601,
43     DIR_602,
44     DIR_603,
45     DIR_7400,
46     DIR_750,
47     DIR_970,
48     DIR_A2,
49     DIR_E500mc,
50     DIR_E5500,
51     DIR_PWR3,
52     DIR_PWR4,
53     DIR_PWR5,
54     DIR_PWR5X,
55     DIR_PWR6,
56     DIR_PWR6X,
57     DIR_PWR7,
58     DIR_PWR8,
59     DIR_64
60   };
61 }
62 
63 class GlobalValue;
64 class TargetMachine;
65 
66 class PPCSubtarget : public PPCGenSubtargetInfo {
67 protected:
68   /// TargetTriple - What processor and OS we're targeting.
69   Triple TargetTriple;
70 
71   /// stackAlignment - The minimum alignment known to hold of the stack frame on
72   /// entry to the function and which must be maintained by every function.
73   unsigned StackAlignment;
74 
75   /// Selected instruction itineraries (one entry per itinerary class.)
76   InstrItineraryData InstrItins;
77 
78   /// Which cpu directive was used.
79   unsigned DarwinDirective;
80 
81   /// Used by the ISel to turn in optimizations for POWER4-derived architectures
82   bool HasMFOCRF;
83   bool Has64BitSupport;
84   bool Use64BitRegs;
85   bool UseCRBits;
86   bool UseSoftFloat;
87   bool IsPPC64;
88   bool HasAltivec;
89   bool HasSPE;
90   bool HasQPX;
91   bool HasVSX;
92   bool HasP8Vector;
93   bool HasP8Altivec;
94   bool HasP8Crypto;
95   bool HasP9Vector;
96   bool HasP9Altivec;
97   bool HasFCPSGN;
98   bool HasFSQRT;
99   bool HasFRE, HasFRES, HasFRSQRTE, HasFRSQRTES;
100   bool HasRecipPrec;
101   bool HasSTFIWX;
102   bool HasLFIWAX;
103   bool HasFPRND;
104   bool HasFPCVT;
105   bool HasISEL;
106   bool HasPOPCNTD;
107   bool HasBPERMD;
108   bool HasExtDiv;
109   bool HasCMPB;
110   bool HasLDBRX;
111   bool IsBookE;
112   bool HasOnlyMSYNC;
113   bool IsE500;
114   bool IsPPC4xx;
115   bool IsPPC6xx;
116   bool FeatureMFTB;
117   bool DeprecatedDST;
118   bool HasLazyResolverStubs;
119   bool IsLittleEndian;
120   bool HasICBT;
121   bool HasInvariantFunctionDescriptors;
122   bool HasPartwordAtomics;
123   bool HasDirectMove;
124   bool HasHTM;
125   bool HasFusion;
126   bool HasFloat128;
127 
128   /// When targeting QPX running a stock PPC64 Linux kernel where the stack
129   /// alignment has not been changed, we need to keep the 16-byte alignment
130   /// of the stack.
131   bool IsQPXStackUnaligned;
132 
133   const PPCTargetMachine &TM;
134   PPCFrameLowering FrameLowering;
135   PPCInstrInfo InstrInfo;
136   PPCTargetLowering TLInfo;
137   SelectionDAGTargetInfo TSInfo;
138 
139 public:
140   /// This constructor initializes the data members to match that
141   /// of the specified triple.
142   ///
143   PPCSubtarget(const Triple &TT, const std::string &CPU, const std::string &FS,
144                const PPCTargetMachine &TM);
145 
146   /// ParseSubtargetFeatures - Parses features string setting specified
147   /// subtarget options.  Definition of function is auto generated by tblgen.
148   void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
149 
150   /// getStackAlignment - Returns the minimum alignment known to hold of the
151   /// stack frame on entry to the function and which must be maintained by every
152   /// function for this subtarget.
153   unsigned getStackAlignment() const { return StackAlignment; }
154 
155   /// getDarwinDirective - Returns the -m directive specified for the cpu.
156   ///
157   unsigned getDarwinDirective() const { return DarwinDirective; }
158 
159   /// getInstrItins - Return the instruction itineraries based on subtarget
160   /// selection.
161   const InstrItineraryData *getInstrItineraryData() const override {
162     return &InstrItins;
163   }
164 
165   const PPCFrameLowering *getFrameLowering() const override {
166     return &FrameLowering;
167   }
168   const PPCInstrInfo *getInstrInfo() const override { return &InstrInfo; }
169   const PPCTargetLowering *getTargetLowering() const override {
170     return &TLInfo;
171   }
172   const SelectionDAGTargetInfo *getSelectionDAGInfo() const override {
173     return &TSInfo;
174   }
175   const PPCRegisterInfo *getRegisterInfo() const override {
176     return &getInstrInfo()->getRegisterInfo();
177   }
178   const PPCTargetMachine &getTargetMachine() const { return TM; }
179 
180   /// initializeSubtargetDependencies - Initializes using a CPU and feature string
181   /// so that we can use initializer lists for subtarget initialization.
182   PPCSubtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS);
183 
184 private:
185   void initializeEnvironment();
186   void initSubtargetFeatures(StringRef CPU, StringRef FS);
187 
188 public:
189   /// isPPC64 - Return true if we are generating code for 64-bit pointer mode.
190   ///
191   bool isPPC64() const;
192 
193   /// has64BitSupport - Return true if the selected CPU supports 64-bit
194   /// instructions, regardless of whether we are in 32-bit or 64-bit mode.
195   bool has64BitSupport() const { return Has64BitSupport; }
196   // useSoftFloat - Return true if soft-float option is turned on.
197   bool useSoftFloat() const { return UseSoftFloat; }
198 
199   /// use64BitRegs - Return true if in 64-bit mode or if we should use 64-bit
200   /// registers in 32-bit mode when possible.  This can only true if
201   /// has64BitSupport() returns true.
202   bool use64BitRegs() const { return Use64BitRegs; }
203 
204   /// useCRBits - Return true if we should store and manipulate i1 values in
205   /// the individual condition register bits.
206   bool useCRBits() const { return UseCRBits; }
207 
208   /// hasLazyResolverStub - Return true if accesses to the specified global have
209   /// to go through a dyld lazy resolution stub.  This means that an extra load
210   /// is required to get the address of the global.
211   bool hasLazyResolverStub(const GlobalValue *GV) const;
212 
213   // isLittleEndian - True if generating little-endian code
214   bool isLittleEndian() const { return IsLittleEndian; }
215 
216   // Specific obvious features.
217   bool hasFCPSGN() const { return HasFCPSGN; }
218   bool hasFSQRT() const { return HasFSQRT; }
219   bool hasFRE() const { return HasFRE; }
220   bool hasFRES() const { return HasFRES; }
221   bool hasFRSQRTE() const { return HasFRSQRTE; }
222   bool hasFRSQRTES() const { return HasFRSQRTES; }
223   bool hasRecipPrec() const { return HasRecipPrec; }
224   bool hasSTFIWX() const { return HasSTFIWX; }
225   bool hasLFIWAX() const { return HasLFIWAX; }
226   bool hasFPRND() const { return HasFPRND; }
227   bool hasFPCVT() const { return HasFPCVT; }
228   bool hasAltivec() const { return HasAltivec; }
229   bool hasSPE() const { return HasSPE; }
230   bool hasQPX() const { return HasQPX; }
231   bool hasVSX() const { return HasVSX; }
232   bool hasP8Vector() const { return HasP8Vector; }
233   bool hasP8Altivec() const { return HasP8Altivec; }
234   bool hasP8Crypto() const { return HasP8Crypto; }
235   bool hasP9Vector() const { return HasP9Vector; }
236   bool hasP9Altivec() const { return HasP9Altivec; }
237   bool hasMFOCRF() const { return HasMFOCRF; }
238   bool hasISEL() const { return HasISEL; }
239   bool hasPOPCNTD() const { return HasPOPCNTD; }
240   bool hasBPERMD() const { return HasBPERMD; }
241   bool hasExtDiv() const { return HasExtDiv; }
242   bool hasCMPB() const { return HasCMPB; }
243   bool hasLDBRX() const { return HasLDBRX; }
244   bool isBookE() const { return IsBookE; }
245   bool hasOnlyMSYNC() const { return HasOnlyMSYNC; }
246   bool isPPC4xx() const { return IsPPC4xx; }
247   bool isPPC6xx() const { return IsPPC6xx; }
248   bool isE500() const { return IsE500; }
249   bool isFeatureMFTB() const { return FeatureMFTB; }
250   bool isDeprecatedDST() const { return DeprecatedDST; }
251   bool hasICBT() const { return HasICBT; }
252   bool hasInvariantFunctionDescriptors() const {
253     return HasInvariantFunctionDescriptors;
254   }
255   bool hasPartwordAtomics() const { return HasPartwordAtomics; }
256   bool hasDirectMove() const { return HasDirectMove; }
257 
258   bool isQPXStackUnaligned() const { return IsQPXStackUnaligned; }
259   unsigned getPlatformStackAlignment() const {
260     if ((hasQPX() || isBGQ()) && !isQPXStackUnaligned())
261       return 32;
262 
263     return 16;
264   }
265   bool hasHTM() const { return HasHTM; }
266   bool hasFusion() const { return HasFusion; }
267   bool hasFloat128() const { return HasFloat128; }
268 
269   const Triple &getTargetTriple() const { return TargetTriple; }
270 
271   /// isDarwin - True if this is any darwin platform.
272   bool isDarwin() const { return TargetTriple.isMacOSX(); }
273   /// isBGQ - True if this is a BG/Q platform.
274   bool isBGQ() const { return TargetTriple.getVendor() == Triple::BGQ; }
275 
276   bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
277   bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); }
278 
279   bool isDarwinABI() const { return isTargetMachO() || isDarwin(); }
280   bool isSVR4ABI() const { return !isDarwinABI(); }
281   bool isELFv2ABI() const;
282 
283   bool enableEarlyIfConversion() const override { return hasISEL(); }
284 
285   // Scheduling customization.
286   bool enableMachineScheduler() const override;
287   // This overrides the PostRAScheduler bit in the SchedModel for each CPU.
288   bool enablePostRAScheduler() const override;
289   AntiDepBreakMode getAntiDepBreakMode() const override;
290   void getCriticalPathRCs(RegClassVector &CriticalPathRCs) const override;
291 
292   void overrideSchedPolicy(MachineSchedPolicy &Policy,
293                            MachineInstr *begin,
294                            MachineInstr *end,
295                            unsigned NumRegionInstrs) const override;
296   bool useAA() const override;
297 
298   bool enableSubRegLiveness() const override;
299 
300   /// classifyGlobalReference - Classify a global variable reference for the
301   /// current subtarget accourding to how we should reference it.
302   unsigned char classifyGlobalReference(const GlobalValue *GV) const;
303 };
304 } // End llvm namespace
305 
306 #endif
307