1 //===-- PPCSubtarget.h - Define Subtarget for the PPC ----------*- C++ -*--===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file declares the PowerPC specific subclass of TargetSubtargetInfo.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_TARGET_POWERPC_PPCSUBTARGET_H
14 #define LLVM_LIB_TARGET_POWERPC_PPCSUBTARGET_H
15 
16 #include "PPCFrameLowering.h"
17 #include "PPCISelLowering.h"
18 #include "PPCInstrInfo.h"
19 #include "llvm/ADT/Triple.h"
20 #include "llvm/CodeGen/SelectionDAGTargetInfo.h"
21 #include "llvm/CodeGen/TargetSubtargetInfo.h"
22 #include "llvm/IR/DataLayout.h"
23 #include "llvm/MC/MCInstrItineraries.h"
24 #include <string>
25 
26 #define GET_SUBTARGETINFO_HEADER
27 #include "PPCGenSubtargetInfo.inc"
28 
29 // GCC #defines PPC on Linux but we use it as our namespace name
30 #undef PPC
31 
32 namespace llvm {
33 class StringRef;
34 
35 namespace PPC {
36   // -m directive values.
37 enum {
38   DIR_NONE,
39   DIR_32,
40   DIR_440,
41   DIR_601,
42   DIR_602,
43   DIR_603,
44   DIR_7400,
45   DIR_750,
46   DIR_970,
47   DIR_A2,
48   DIR_E500,
49   DIR_E500mc,
50   DIR_E5500,
51   DIR_PWR3,
52   DIR_PWR4,
53   DIR_PWR5,
54   DIR_PWR5X,
55   DIR_PWR6,
56   DIR_PWR6X,
57   DIR_PWR7,
58   DIR_PWR8,
59   DIR_PWR9,
60   DIR_PWR10,
61   DIR_PWR_FUTURE,
62   DIR_64
63 };
64 }
65 
66 class GlobalValue;
67 
68 class PPCSubtarget : public PPCGenSubtargetInfo {
69 public:
70   enum POPCNTDKind {
71     POPCNTD_Unavailable,
72     POPCNTD_Slow,
73     POPCNTD_Fast
74   };
75 
76 protected:
77   /// TargetTriple - What processor and OS we're targeting.
78   Triple TargetTriple;
79 
80   /// stackAlignment - The minimum alignment known to hold of the stack frame on
81   /// entry to the function and which must be maintained by every function.
82   Align StackAlignment;
83 
84   /// Selected instruction itineraries (one entry per itinerary class.)
85   InstrItineraryData InstrItins;
86 
87   /// Which cpu directive was used.
88   unsigned CPUDirective;
89 
90   /// Used by the ISel to turn in optimizations for POWER4-derived architectures
91   bool HasMFOCRF;
92   bool Has64BitSupport;
93   bool Use64BitRegs;
94   bool UseCRBits;
95   bool HasHardFloat;
96   bool IsPPC64;
97   bool HasAltivec;
98   bool HasFPU;
99   bool HasSPE;
100   bool HasVSX;
101   bool NeedsTwoConstNR;
102   bool HasP8Vector;
103   bool HasP8Altivec;
104   bool HasP8Crypto;
105   bool HasP9Vector;
106   bool HasP9Altivec;
107   bool HasP10Vector;
108   bool HasPrefixInstrs;
109   bool HasPCRelativeMemops;
110   bool HasFCPSGN;
111   bool HasFSQRT;
112   bool HasFRE, HasFRES, HasFRSQRTE, HasFRSQRTES;
113   bool HasRecipPrec;
114   bool HasSTFIWX;
115   bool HasLFIWAX;
116   bool HasFPRND;
117   bool HasFPCVT;
118   bool HasISEL;
119   bool HasBPERMD;
120   bool HasExtDiv;
121   bool HasCMPB;
122   bool HasLDBRX;
123   bool IsBookE;
124   bool HasOnlyMSYNC;
125   bool IsE500;
126   bool IsPPC4xx;
127   bool IsPPC6xx;
128   bool FeatureMFTB;
129   bool AllowsUnalignedFPAccess;
130   bool DeprecatedDST;
131   bool IsLittleEndian;
132   bool HasICBT;
133   bool HasInvariantFunctionDescriptors;
134   bool HasPartwordAtomics;
135   bool HasDirectMove;
136   bool HasHTM;
137   bool HasFloat128;
138   bool HasFusion;
139   bool HasAddiLoadFusion;
140   bool HasAddisLoadFusion;
141   bool IsISA3_0;
142   bool IsISA3_1;
143   bool UseLongCalls;
144   bool SecurePlt;
145   bool VectorsUseTwoUnits;
146   bool UsePPCPreRASchedStrategy;
147   bool UsePPCPostRASchedStrategy;
148   bool PairedVectorMemops;
149   bool PredictableSelectIsExpensive;
150 
151   POPCNTDKind HasPOPCNTD;
152 
153   const PPCTargetMachine &TM;
154   PPCFrameLowering FrameLowering;
155   PPCInstrInfo InstrInfo;
156   PPCTargetLowering TLInfo;
157   SelectionDAGTargetInfo TSInfo;
158 
159 public:
160   /// This constructor initializes the data members to match that
161   /// of the specified triple.
162   ///
163   PPCSubtarget(const Triple &TT, const std::string &CPU, const std::string &FS,
164                const PPCTargetMachine &TM);
165 
166   /// ParseSubtargetFeatures - Parses features string setting specified
167   /// subtarget options.  Definition of function is auto generated by tblgen.
168   void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
169 
170   /// getStackAlignment - Returns the minimum alignment known to hold of the
171   /// stack frame on entry to the function and which must be maintained by every
172   /// function for this subtarget.
173   Align getStackAlignment() const { return StackAlignment; }
174 
175   /// getDarwinDirective - Returns the -m directive specified for the cpu.
176   unsigned getDarwinDirective() const { return CPUDirective; }
177 
178   /// getCPUDirective - Returns the -m directive specified for the cpu.
179   ///
180   unsigned getCPUDirective() const { return CPUDirective; }
181 
182   /// getInstrItins - Return the instruction itineraries based on subtarget
183   /// selection.
184   const InstrItineraryData *getInstrItineraryData() const override {
185     return &InstrItins;
186   }
187 
188   const PPCFrameLowering *getFrameLowering() const override {
189     return &FrameLowering;
190   }
191   const PPCInstrInfo *getInstrInfo() const override { return &InstrInfo; }
192   const PPCTargetLowering *getTargetLowering() const override {
193     return &TLInfo;
194   }
195   const SelectionDAGTargetInfo *getSelectionDAGInfo() const override {
196     return &TSInfo;
197   }
198   const PPCRegisterInfo *getRegisterInfo() const override {
199     return &getInstrInfo()->getRegisterInfo();
200   }
201   const PPCTargetMachine &getTargetMachine() const { return TM; }
202 
203   /// initializeSubtargetDependencies - Initializes using a CPU and feature string
204   /// so that we can use initializer lists for subtarget initialization.
205   PPCSubtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS);
206 
207 private:
208   void initializeEnvironment();
209   void initSubtargetFeatures(StringRef CPU, StringRef FS);
210 
211 public:
212   /// isPPC64 - Return true if we are generating code for 64-bit pointer mode.
213   ///
214   bool isPPC64() const;
215 
216   /// has64BitSupport - Return true if the selected CPU supports 64-bit
217   /// instructions, regardless of whether we are in 32-bit or 64-bit mode.
218   bool has64BitSupport() const { return Has64BitSupport; }
219   // useSoftFloat - Return true if soft-float option is turned on.
220   bool useSoftFloat() const {
221     if (isAIXABI() && !HasHardFloat)
222       report_fatal_error("soft-float is not yet supported on AIX.");
223     return !HasHardFloat;
224   }
225 
226   /// use64BitRegs - Return true if in 64-bit mode or if we should use 64-bit
227   /// registers in 32-bit mode when possible.  This can only true if
228   /// has64BitSupport() returns true.
229   bool use64BitRegs() const { return Use64BitRegs; }
230 
231   /// useCRBits - Return true if we should store and manipulate i1 values in
232   /// the individual condition register bits.
233   bool useCRBits() const { return UseCRBits; }
234 
235   // isLittleEndian - True if generating little-endian code
236   bool isLittleEndian() const { return IsLittleEndian; }
237 
238   // Specific obvious features.
239   bool hasFCPSGN() const { return HasFCPSGN; }
240   bool hasFSQRT() const { return HasFSQRT; }
241   bool hasFRE() const { return HasFRE; }
242   bool hasFRES() const { return HasFRES; }
243   bool hasFRSQRTE() const { return HasFRSQRTE; }
244   bool hasFRSQRTES() const { return HasFRSQRTES; }
245   bool hasRecipPrec() const { return HasRecipPrec; }
246   bool hasSTFIWX() const { return HasSTFIWX; }
247   bool hasLFIWAX() const { return HasLFIWAX; }
248   bool hasFPRND() const { return HasFPRND; }
249   bool hasFPCVT() const { return HasFPCVT; }
250   bool hasAltivec() const { return HasAltivec; }
251   bool hasSPE() const { return HasSPE; }
252   bool hasFPU() const { return HasFPU; }
253   bool hasVSX() const { return HasVSX; }
254   bool needsTwoConstNR() const { return NeedsTwoConstNR; }
255   bool hasP8Vector() const { return HasP8Vector; }
256   bool hasP8Altivec() const { return HasP8Altivec; }
257   bool hasP8Crypto() const { return HasP8Crypto; }
258   bool hasP9Vector() const { return HasP9Vector; }
259   bool hasP9Altivec() const { return HasP9Altivec; }
260   bool hasP10Vector() const { return HasP10Vector; }
261   bool hasPrefixInstrs() const { return HasPrefixInstrs; }
262   bool hasPCRelativeMemops() const { return HasPCRelativeMemops; }
263   bool pairedVectorMemops() const { return PairedVectorMemops; }
264   bool hasMFOCRF() const { return HasMFOCRF; }
265   bool hasISEL() const { return HasISEL; }
266   bool hasBPERMD() const { return HasBPERMD; }
267   bool hasExtDiv() const { return HasExtDiv; }
268   bool hasCMPB() const { return HasCMPB; }
269   bool hasLDBRX() const { return HasLDBRX; }
270   bool isBookE() const { return IsBookE; }
271   bool hasOnlyMSYNC() const { return HasOnlyMSYNC; }
272   bool isPPC4xx() const { return IsPPC4xx; }
273   bool isPPC6xx() const { return IsPPC6xx; }
274   bool isSecurePlt() const {return SecurePlt; }
275   bool vectorsUseTwoUnits() const {return VectorsUseTwoUnits; }
276   bool isE500() const { return IsE500; }
277   bool isFeatureMFTB() const { return FeatureMFTB; }
278   bool allowsUnalignedFPAccess() const { return AllowsUnalignedFPAccess; }
279   bool isDeprecatedDST() const { return DeprecatedDST; }
280   bool hasICBT() const { return HasICBT; }
281   bool hasInvariantFunctionDescriptors() const {
282     return HasInvariantFunctionDescriptors;
283   }
284   bool usePPCPreRASchedStrategy() const { return UsePPCPreRASchedStrategy; }
285   bool usePPCPostRASchedStrategy() const { return UsePPCPostRASchedStrategy; }
286   bool hasPartwordAtomics() const { return HasPartwordAtomics; }
287   bool hasDirectMove() const { return HasDirectMove; }
288 
289   Align getPlatformStackAlignment() const {
290     return Align(16);
291   }
292 
293   unsigned  getRedZoneSize() const {
294     if (isPPC64())
295       // 288 bytes = 18*8 (FPRs) + 18*8 (GPRs, GPR13 reserved)
296       return 288;
297 
298     // AIX PPC32: 220 bytes = 18*8 (FPRs) + 19*4 (GPRs);
299     // PPC32 SVR4ABI has no redzone.
300     return isAIXABI() ? 220 : 0;
301   }
302 
303   bool hasHTM() const { return HasHTM; }
304   bool hasFloat128() const { return HasFloat128; }
305   bool isISA3_0() const { return IsISA3_0; }
306   bool isISA3_1() const { return IsISA3_1; }
307   bool useLongCalls() const { return UseLongCalls; }
308   bool hasFusion() const { return HasFusion; }
309   bool hasAddiLoadFusion() const { return HasAddiLoadFusion; }
310   bool hasAddisLoadFusion() const { return HasAddisLoadFusion; }
311   bool needsSwapsForVSXMemOps() const {
312     return hasVSX() && isLittleEndian() && !hasP9Vector();
313   }
314 
315   POPCNTDKind hasPOPCNTD() const { return HasPOPCNTD; }
316 
317   const Triple &getTargetTriple() const { return TargetTriple; }
318 
319   bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
320   bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); }
321   bool isTargetLinux() const { return TargetTriple.isOSLinux(); }
322 
323   bool isAIXABI() const { return TargetTriple.isOSAIX(); }
324   bool isSVR4ABI() const { return !isAIXABI(); }
325   bool isELFv2ABI() const;
326 
327   bool is64BitELFABI() const { return  isSVR4ABI() && isPPC64(); }
328   bool is32BitELFABI() const { return  isSVR4ABI() && !isPPC64(); }
329   bool isUsingPCRelativeCalls() const;
330 
331   /// Originally, this function return hasISEL(). Now we always enable it,
332   /// but may expand the ISEL instruction later.
333   bool enableEarlyIfConversion() const override { return true; }
334 
335   /// Scheduling customization.
336   bool enableMachineScheduler() const override;
337   /// Pipeliner customization.
338   bool enableMachinePipeliner() const override;
339   /// Machine Pipeliner customization
340   bool useDFAforSMS() const override;
341   /// This overrides the PostRAScheduler bit in the SchedModel for each CPU.
342   bool enablePostRAScheduler() const override;
343   AntiDepBreakMode getAntiDepBreakMode() const override;
344   void getCriticalPathRCs(RegClassVector &CriticalPathRCs) const override;
345 
346   void overrideSchedPolicy(MachineSchedPolicy &Policy,
347                            unsigned NumRegionInstrs) const override;
348   bool useAA() const override;
349 
350   bool enableSubRegLiveness() const override;
351 
352   /// True if the GV will be accessed via an indirect symbol.
353   bool isGVIndirectSymbol(const GlobalValue *GV) const;
354 
355   /// True if the ABI is descriptor based.
356   bool usesFunctionDescriptors() const {
357     // Both 32-bit and 64-bit AIX are descriptor based. For ELF only the 64-bit
358     // v1 ABI uses descriptors.
359     return isAIXABI() || (is64BitELFABI() && !isELFv2ABI());
360   }
361 
362   unsigned descriptorTOCAnchorOffset() const {
363     assert(usesFunctionDescriptors() &&
364            "Should only be called when the target uses descriptors.");
365     return IsPPC64 ? 8 : 4;
366   }
367 
368   unsigned descriptorEnvironmentPointerOffset() const {
369     assert(usesFunctionDescriptors() &&
370            "Should only be called when the target uses descriptors.");
371     return IsPPC64 ? 16 : 8;
372   }
373 
374   MCRegister getEnvironmentPointerRegister() const {
375     assert(usesFunctionDescriptors() &&
376            "Should only be called when the target uses descriptors.");
377      return IsPPC64 ? PPC::X11 : PPC::R11;
378   }
379 
380   MCRegister getTOCPointerRegister() const {
381     assert((is64BitELFABI() || isAIXABI()) &&
382            "Should only be called when the target is a TOC based ABI.");
383     return IsPPC64 ? PPC::X2 : PPC::R2;
384   }
385 
386   MCRegister getStackPointerRegister() const {
387     return IsPPC64 ? PPC::X1 : PPC::R1;
388   }
389 
390   bool isXRaySupported() const override { return IsPPC64 && IsLittleEndian; }
391 
392   bool isPredictableSelectIsExpensive() const {
393     return PredictableSelectIsExpensive;
394   }
395 };
396 } // End llvm namespace
397 
398 #endif
399