1 //===-- PPCSubtarget.h - Define Subtarget for the PPC ----------*- C++ -*--===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file declares the PowerPC specific subclass of TargetSubtargetInfo.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_TARGET_POWERPC_PPCSUBTARGET_H
14 #define LLVM_LIB_TARGET_POWERPC_PPCSUBTARGET_H
15 
16 #include "PPCFrameLowering.h"
17 #include "PPCISelLowering.h"
18 #include "PPCInstrInfo.h"
19 #include "llvm/ADT/Triple.h"
20 #include "llvm/CodeGen/GlobalISel/CallLowering.h"
21 #include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
22 #include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
23 #include "llvm/CodeGen/SelectionDAGTargetInfo.h"
24 #include "llvm/CodeGen/TargetSubtargetInfo.h"
25 #include "llvm/IR/DataLayout.h"
26 #include "llvm/MC/MCInstrItineraries.h"
27 #include <string>
28 
29 #define GET_SUBTARGETINFO_HEADER
30 #include "PPCGenSubtargetInfo.inc"
31 
32 // GCC #defines PPC on Linux but we use it as our namespace name
33 #undef PPC
34 
35 namespace llvm {
36 class StringRef;
37 
38 namespace PPC {
39   // -m directive values.
40 enum {
41   DIR_NONE,
42   DIR_32,
43   DIR_440,
44   DIR_601,
45   DIR_602,
46   DIR_603,
47   DIR_7400,
48   DIR_750,
49   DIR_970,
50   DIR_A2,
51   DIR_E500,
52   DIR_E500mc,
53   DIR_E5500,
54   DIR_PWR3,
55   DIR_PWR4,
56   DIR_PWR5,
57   DIR_PWR5X,
58   DIR_PWR6,
59   DIR_PWR6X,
60   DIR_PWR7,
61   DIR_PWR8,
62   DIR_PWR9,
63   DIR_PWR10,
64   DIR_PWR_FUTURE,
65   DIR_64
66 };
67 }
68 
69 class GlobalValue;
70 
71 class PPCSubtarget : public PPCGenSubtargetInfo {
72 public:
73   enum POPCNTDKind {
74     POPCNTD_Unavailable,
75     POPCNTD_Slow,
76     POPCNTD_Fast
77   };
78 
79 protected:
80   /// TargetTriple - What processor and OS we're targeting.
81   Triple TargetTriple;
82 
83   /// stackAlignment - The minimum alignment known to hold of the stack frame on
84   /// entry to the function and which must be maintained by every function.
85   Align StackAlignment;
86 
87   /// Selected instruction itineraries (one entry per itinerary class.)
88   InstrItineraryData InstrItins;
89 
90   /// Which cpu directive was used.
91   unsigned CPUDirective;
92 
93   /// Used by the ISel to turn in optimizations for POWER4-derived architectures
94   bool HasMFOCRF;
95   bool Has64BitSupport;
96   bool Use64BitRegs;
97   bool UseCRBits;
98   bool HasHardFloat;
99   bool IsPPC64;
100   bool HasAltivec;
101   bool HasFPU;
102   bool HasSPE;
103   bool HasVSX;
104   bool NeedsTwoConstNR;
105   bool HasP8Vector;
106   bool HasP8Altivec;
107   bool HasP8Crypto;
108   bool HasP9Vector;
109   bool HasP9Altivec;
110   bool HasP10Vector;
111   bool HasPrefixInstrs;
112   bool HasPCRelativeMemops;
113   bool HasMMA;
114   bool HasFCPSGN;
115   bool HasFSQRT;
116   bool HasFRE, HasFRES, HasFRSQRTE, HasFRSQRTES;
117   bool HasRecipPrec;
118   bool HasSTFIWX;
119   bool HasLFIWAX;
120   bool HasFPRND;
121   bool HasFPCVT;
122   bool HasISEL;
123   bool HasBPERMD;
124   bool HasExtDiv;
125   bool HasCMPB;
126   bool HasLDBRX;
127   bool IsBookE;
128   bool HasOnlyMSYNC;
129   bool IsE500;
130   bool IsPPC4xx;
131   bool IsPPC6xx;
132   bool FeatureMFTB;
133   bool AllowsUnalignedFPAccess;
134   bool DeprecatedDST;
135   bool IsLittleEndian;
136   bool HasICBT;
137   bool HasInvariantFunctionDescriptors;
138   bool HasPartwordAtomics;
139   bool HasDirectMove;
140   bool HasHTM;
141   bool HasFloat128;
142   bool HasFusion;
143   bool HasAddiLoadFusion;
144   bool HasAddisLoadFusion;
145   bool IsISA3_0;
146   bool IsISA3_1;
147   bool UseLongCalls;
148   bool SecurePlt;
149   bool VectorsUseTwoUnits;
150   bool UsePPCPreRASchedStrategy;
151   bool UsePPCPostRASchedStrategy;
152   bool PairedVectorMemops;
153   bool PredictableSelectIsExpensive;
154 
155   POPCNTDKind HasPOPCNTD;
156 
157   const PPCTargetMachine &TM;
158   PPCFrameLowering FrameLowering;
159   PPCInstrInfo InstrInfo;
160   PPCTargetLowering TLInfo;
161   SelectionDAGTargetInfo TSInfo;
162 
163   /// GlobalISel related APIs.
164   std::unique_ptr<CallLowering> CallLoweringInfo;
165   std::unique_ptr<LegalizerInfo> Legalizer;
166   std::unique_ptr<RegisterBankInfo> RegBankInfo;
167   std::unique_ptr<InstructionSelector> InstSelector;
168 
169 public:
170   /// This constructor initializes the data members to match that
171   /// of the specified triple.
172   ///
173   PPCSubtarget(const Triple &TT, const std::string &CPU, const std::string &FS,
174                const PPCTargetMachine &TM);
175 
176   /// ParseSubtargetFeatures - Parses features string setting specified
177   /// subtarget options.  Definition of function is auto generated by tblgen.
178   void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS);
179 
180   /// getStackAlignment - Returns the minimum alignment known to hold of the
181   /// stack frame on entry to the function and which must be maintained by every
182   /// function for this subtarget.
183   Align getStackAlignment() const { return StackAlignment; }
184 
185   /// getDarwinDirective - Returns the -m directive specified for the cpu.
186   unsigned getDarwinDirective() const { return CPUDirective; }
187 
188   /// getCPUDirective - Returns the -m directive specified for the cpu.
189   ///
190   unsigned getCPUDirective() const { return CPUDirective; }
191 
192   /// getInstrItins - Return the instruction itineraries based on subtarget
193   /// selection.
194   const InstrItineraryData *getInstrItineraryData() const override {
195     return &InstrItins;
196   }
197 
198   const PPCFrameLowering *getFrameLowering() const override {
199     return &FrameLowering;
200   }
201   const PPCInstrInfo *getInstrInfo() const override { return &InstrInfo; }
202   const PPCTargetLowering *getTargetLowering() const override {
203     return &TLInfo;
204   }
205   const SelectionDAGTargetInfo *getSelectionDAGInfo() const override {
206     return &TSInfo;
207   }
208   const PPCRegisterInfo *getRegisterInfo() const override {
209     return &getInstrInfo()->getRegisterInfo();
210   }
211   const PPCTargetMachine &getTargetMachine() const { return TM; }
212 
213   /// initializeSubtargetDependencies - Initializes using a CPU and feature string
214   /// so that we can use initializer lists for subtarget initialization.
215   PPCSubtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS);
216 
217 private:
218   void initializeEnvironment();
219   void initSubtargetFeatures(StringRef CPU, StringRef FS);
220 
221 public:
222   /// isPPC64 - Return true if we are generating code for 64-bit pointer mode.
223   ///
224   bool isPPC64() const;
225 
226   /// has64BitSupport - Return true if the selected CPU supports 64-bit
227   /// instructions, regardless of whether we are in 32-bit or 64-bit mode.
228   bool has64BitSupport() const { return Has64BitSupport; }
229   // useSoftFloat - Return true if soft-float option is turned on.
230   bool useSoftFloat() const {
231     if (isAIXABI() && !HasHardFloat)
232       report_fatal_error("soft-float is not yet supported on AIX.");
233     return !HasHardFloat;
234   }
235 
236   /// use64BitRegs - Return true if in 64-bit mode or if we should use 64-bit
237   /// registers in 32-bit mode when possible.  This can only true if
238   /// has64BitSupport() returns true.
239   bool use64BitRegs() const { return Use64BitRegs; }
240 
241   /// useCRBits - Return true if we should store and manipulate i1 values in
242   /// the individual condition register bits.
243   bool useCRBits() const { return UseCRBits; }
244 
245   // isLittleEndian - True if generating little-endian code
246   bool isLittleEndian() const { return IsLittleEndian; }
247 
248   // Specific obvious features.
249   bool hasFCPSGN() const { return HasFCPSGN; }
250   bool hasFSQRT() const { return HasFSQRT; }
251   bool hasFRE() const { return HasFRE; }
252   bool hasFRES() const { return HasFRES; }
253   bool hasFRSQRTE() const { return HasFRSQRTE; }
254   bool hasFRSQRTES() const { return HasFRSQRTES; }
255   bool hasRecipPrec() const { return HasRecipPrec; }
256   bool hasSTFIWX() const { return HasSTFIWX; }
257   bool hasLFIWAX() const { return HasLFIWAX; }
258   bool hasFPRND() const { return HasFPRND; }
259   bool hasFPCVT() const { return HasFPCVT; }
260   bool hasAltivec() const { return HasAltivec; }
261   bool hasSPE() const { return HasSPE; }
262   bool hasFPU() const { return HasFPU; }
263   bool hasVSX() const { return HasVSX; }
264   bool needsTwoConstNR() const { return NeedsTwoConstNR; }
265   bool hasP8Vector() const { return HasP8Vector; }
266   bool hasP8Altivec() const { return HasP8Altivec; }
267   bool hasP8Crypto() const { return HasP8Crypto; }
268   bool hasP9Vector() const { return HasP9Vector; }
269   bool hasP9Altivec() const { return HasP9Altivec; }
270   bool hasP10Vector() const { return HasP10Vector; }
271   bool hasPrefixInstrs() const { return HasPrefixInstrs; }
272   bool hasPCRelativeMemops() const { return HasPCRelativeMemops; }
273   bool hasMMA() const { return HasMMA; }
274   bool pairedVectorMemops() const { return PairedVectorMemops; }
275   bool hasMFOCRF() const { return HasMFOCRF; }
276   bool hasISEL() const { return HasISEL; }
277   bool hasBPERMD() const { return HasBPERMD; }
278   bool hasExtDiv() const { return HasExtDiv; }
279   bool hasCMPB() const { return HasCMPB; }
280   bool hasLDBRX() const { return HasLDBRX; }
281   bool isBookE() const { return IsBookE; }
282   bool hasOnlyMSYNC() const { return HasOnlyMSYNC; }
283   bool isPPC4xx() const { return IsPPC4xx; }
284   bool isPPC6xx() const { return IsPPC6xx; }
285   bool isSecurePlt() const {return SecurePlt; }
286   bool vectorsUseTwoUnits() const {return VectorsUseTwoUnits; }
287   bool isE500() const { return IsE500; }
288   bool isFeatureMFTB() const { return FeatureMFTB; }
289   bool allowsUnalignedFPAccess() const { return AllowsUnalignedFPAccess; }
290   bool isDeprecatedDST() const { return DeprecatedDST; }
291   bool hasICBT() const { return HasICBT; }
292   bool hasInvariantFunctionDescriptors() const {
293     return HasInvariantFunctionDescriptors;
294   }
295   bool usePPCPreRASchedStrategy() const { return UsePPCPreRASchedStrategy; }
296   bool usePPCPostRASchedStrategy() const { return UsePPCPostRASchedStrategy; }
297   bool hasPartwordAtomics() const { return HasPartwordAtomics; }
298   bool hasDirectMove() const { return HasDirectMove; }
299 
300   Align getPlatformStackAlignment() const {
301     return Align(16);
302   }
303 
304   unsigned  getRedZoneSize() const {
305     if (isPPC64())
306       // 288 bytes = 18*8 (FPRs) + 18*8 (GPRs, GPR13 reserved)
307       return 288;
308 
309     // AIX PPC32: 220 bytes = 18*8 (FPRs) + 19*4 (GPRs);
310     // PPC32 SVR4ABI has no redzone.
311     return isAIXABI() ? 220 : 0;
312   }
313 
314   bool hasHTM() const { return HasHTM; }
315   bool hasFloat128() const { return HasFloat128; }
316   bool isISA3_0() const { return IsISA3_0; }
317   bool isISA3_1() const { return IsISA3_1; }
318   bool useLongCalls() const { return UseLongCalls; }
319   bool hasFusion() const { return HasFusion; }
320   bool hasAddiLoadFusion() const { return HasAddiLoadFusion; }
321   bool hasAddisLoadFusion() const { return HasAddisLoadFusion; }
322   bool needsSwapsForVSXMemOps() const {
323     return hasVSX() && isLittleEndian() && !hasP9Vector();
324   }
325 
326   POPCNTDKind hasPOPCNTD() const { return HasPOPCNTD; }
327 
328   const Triple &getTargetTriple() const { return TargetTriple; }
329 
330   bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
331   bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); }
332   bool isTargetLinux() const { return TargetTriple.isOSLinux(); }
333 
334   bool isAIXABI() const { return TargetTriple.isOSAIX(); }
335   bool isSVR4ABI() const { return !isAIXABI(); }
336   bool isELFv2ABI() const;
337 
338   bool is64BitELFABI() const { return  isSVR4ABI() && isPPC64(); }
339   bool is32BitELFABI() const { return  isSVR4ABI() && !isPPC64(); }
340   bool isUsingPCRelativeCalls() const;
341 
342   /// Originally, this function return hasISEL(). Now we always enable it,
343   /// but may expand the ISEL instruction later.
344   bool enableEarlyIfConversion() const override { return true; }
345 
346   /// Scheduling customization.
347   bool enableMachineScheduler() const override;
348   /// Pipeliner customization.
349   bool enableMachinePipeliner() const override;
350   /// Machine Pipeliner customization
351   bool useDFAforSMS() const override;
352   /// This overrides the PostRAScheduler bit in the SchedModel for each CPU.
353   bool enablePostRAScheduler() const override;
354   AntiDepBreakMode getAntiDepBreakMode() const override;
355   void getCriticalPathRCs(RegClassVector &CriticalPathRCs) const override;
356 
357   void overrideSchedPolicy(MachineSchedPolicy &Policy,
358                            unsigned NumRegionInstrs) const override;
359   bool useAA() const override;
360 
361   bool enableSubRegLiveness() const override;
362 
363   /// True if the GV will be accessed via an indirect symbol.
364   bool isGVIndirectSymbol(const GlobalValue *GV) const;
365 
366   /// True if the ABI is descriptor based.
367   bool usesFunctionDescriptors() const {
368     // Both 32-bit and 64-bit AIX are descriptor based. For ELF only the 64-bit
369     // v1 ABI uses descriptors.
370     return isAIXABI() || (is64BitELFABI() && !isELFv2ABI());
371   }
372 
373   unsigned descriptorTOCAnchorOffset() const {
374     assert(usesFunctionDescriptors() &&
375            "Should only be called when the target uses descriptors.");
376     return IsPPC64 ? 8 : 4;
377   }
378 
379   unsigned descriptorEnvironmentPointerOffset() const {
380     assert(usesFunctionDescriptors() &&
381            "Should only be called when the target uses descriptors.");
382     return IsPPC64 ? 16 : 8;
383   }
384 
385   MCRegister getEnvironmentPointerRegister() const {
386     assert(usesFunctionDescriptors() &&
387            "Should only be called when the target uses descriptors.");
388      return IsPPC64 ? PPC::X11 : PPC::R11;
389   }
390 
391   MCRegister getTOCPointerRegister() const {
392     assert((is64BitELFABI() || isAIXABI()) &&
393            "Should only be called when the target is a TOC based ABI.");
394     return IsPPC64 ? PPC::X2 : PPC::R2;
395   }
396 
397   MCRegister getStackPointerRegister() const {
398     return IsPPC64 ? PPC::X1 : PPC::R1;
399   }
400 
401   bool isXRaySupported() const override { return IsPPC64 && IsLittleEndian; }
402 
403   bool isPredictableSelectIsExpensive() const {
404     return PredictableSelectIsExpensive;
405   }
406 
407   // GlobalISEL
408   const CallLowering *getCallLowering() const override;
409   const RegisterBankInfo *getRegBankInfo() const override;
410   const LegalizerInfo *getLegalizerInfo() const override;
411   InstructionSelector *getInstructionSelector() const override;
412 };
413 } // End llvm namespace
414 
415 #endif
416