1 //===-- PPCSubtarget.h - Define Subtarget for the PPC ----------*- C++ -*--===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file declares the PowerPC specific subclass of TargetSubtargetInfo.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_TARGET_POWERPC_PPCSUBTARGET_H
14 #define LLVM_LIB_TARGET_POWERPC_PPCSUBTARGET_H
15 
16 #include "PPCFrameLowering.h"
17 #include "PPCISelLowering.h"
18 #include "PPCInstrInfo.h"
19 #include "llvm/ADT/Triple.h"
20 #include "llvm/CodeGen/SelectionDAGTargetInfo.h"
21 #include "llvm/CodeGen/TargetSubtargetInfo.h"
22 #include "llvm/IR/DataLayout.h"
23 #include "llvm/MC/MCInstrItineraries.h"
24 #include <string>
25 
26 #define GET_SUBTARGETINFO_HEADER
27 #include "PPCGenSubtargetInfo.inc"
28 
29 // GCC #defines PPC on Linux but we use it as our namespace name
30 #undef PPC
31 
32 namespace llvm {
33 class StringRef;
34 
35 namespace PPC {
36   // -m directive values.
37 enum {
38   DIR_NONE,
39   DIR_32,
40   DIR_440,
41   DIR_601,
42   DIR_602,
43   DIR_603,
44   DIR_7400,
45   DIR_750,
46   DIR_970,
47   DIR_A2,
48   DIR_E500,
49   DIR_E500mc,
50   DIR_E5500,
51   DIR_PWR3,
52   DIR_PWR4,
53   DIR_PWR5,
54   DIR_PWR5X,
55   DIR_PWR6,
56   DIR_PWR6X,
57   DIR_PWR7,
58   DIR_PWR8,
59   DIR_PWR9,
60   DIR_PWR10,
61   DIR_PWR_FUTURE,
62   DIR_64
63 };
64 }
65 
66 class GlobalValue;
67 
68 class PPCSubtarget : public PPCGenSubtargetInfo {
69 public:
70   enum POPCNTDKind {
71     POPCNTD_Unavailable,
72     POPCNTD_Slow,
73     POPCNTD_Fast
74   };
75 
76 protected:
77   /// TargetTriple - What processor and OS we're targeting.
78   Triple TargetTriple;
79 
80   /// stackAlignment - The minimum alignment known to hold of the stack frame on
81   /// entry to the function and which must be maintained by every function.
82   Align StackAlignment;
83 
84   /// Selected instruction itineraries (one entry per itinerary class.)
85   InstrItineraryData InstrItins;
86 
87   /// Which cpu directive was used.
88   unsigned CPUDirective;
89 
90   /// Used by the ISel to turn in optimizations for POWER4-derived architectures
91   bool HasMFOCRF;
92   bool Has64BitSupport;
93   bool Use64BitRegs;
94   bool UseCRBits;
95   bool HasHardFloat;
96   bool IsPPC64;
97   bool HasAltivec;
98   bool HasFPU;
99   bool HasSPE;
100   bool HasVSX;
101   bool NeedsTwoConstNR;
102   bool HasP8Vector;
103   bool HasP8Altivec;
104   bool HasP8Crypto;
105   bool HasP9Vector;
106   bool HasP9Altivec;
107   bool HasP10Vector;
108   bool HasPrefixInstrs;
109   bool HasPCRelativeMemops;
110   bool HasMMA;
111   bool HasFCPSGN;
112   bool HasFSQRT;
113   bool HasFRE, HasFRES, HasFRSQRTE, HasFRSQRTES;
114   bool HasRecipPrec;
115   bool HasSTFIWX;
116   bool HasLFIWAX;
117   bool HasFPRND;
118   bool HasFPCVT;
119   bool HasISEL;
120   bool HasBPERMD;
121   bool HasExtDiv;
122   bool HasCMPB;
123   bool HasLDBRX;
124   bool IsBookE;
125   bool HasOnlyMSYNC;
126   bool IsE500;
127   bool IsPPC4xx;
128   bool IsPPC6xx;
129   bool FeatureMFTB;
130   bool AllowsUnalignedFPAccess;
131   bool DeprecatedDST;
132   bool IsLittleEndian;
133   bool HasICBT;
134   bool HasInvariantFunctionDescriptors;
135   bool HasPartwordAtomics;
136   bool HasDirectMove;
137   bool HasHTM;
138   bool HasFloat128;
139   bool HasFusion;
140   bool HasAddiLoadFusion;
141   bool HasAddisLoadFusion;
142   bool IsISA3_0;
143   bool IsISA3_1;
144   bool UseLongCalls;
145   bool SecurePlt;
146   bool VectorsUseTwoUnits;
147   bool UsePPCPreRASchedStrategy;
148   bool UsePPCPostRASchedStrategy;
149   bool PairedVectorMemops;
150   bool PredictableSelectIsExpensive;
151 
152   POPCNTDKind HasPOPCNTD;
153 
154   const PPCTargetMachine &TM;
155   PPCFrameLowering FrameLowering;
156   PPCInstrInfo InstrInfo;
157   PPCTargetLowering TLInfo;
158   SelectionDAGTargetInfo TSInfo;
159 
160 public:
161   /// This constructor initializes the data members to match that
162   /// of the specified triple.
163   ///
164   PPCSubtarget(const Triple &TT, const std::string &CPU, const std::string &FS,
165                const PPCTargetMachine &TM);
166 
167   /// ParseSubtargetFeatures - Parses features string setting specified
168   /// subtarget options.  Definition of function is auto generated by tblgen.
169   void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS);
170 
171   /// getStackAlignment - Returns the minimum alignment known to hold of the
172   /// stack frame on entry to the function and which must be maintained by every
173   /// function for this subtarget.
174   Align getStackAlignment() const { return StackAlignment; }
175 
176   /// getDarwinDirective - Returns the -m directive specified for the cpu.
177   unsigned getDarwinDirective() const { return CPUDirective; }
178 
179   /// getCPUDirective - Returns the -m directive specified for the cpu.
180   ///
181   unsigned getCPUDirective() const { return CPUDirective; }
182 
183   /// getInstrItins - Return the instruction itineraries based on subtarget
184   /// selection.
185   const InstrItineraryData *getInstrItineraryData() const override {
186     return &InstrItins;
187   }
188 
189   const PPCFrameLowering *getFrameLowering() const override {
190     return &FrameLowering;
191   }
192   const PPCInstrInfo *getInstrInfo() const override { return &InstrInfo; }
193   const PPCTargetLowering *getTargetLowering() const override {
194     return &TLInfo;
195   }
196   const SelectionDAGTargetInfo *getSelectionDAGInfo() const override {
197     return &TSInfo;
198   }
199   const PPCRegisterInfo *getRegisterInfo() const override {
200     return &getInstrInfo()->getRegisterInfo();
201   }
202   const PPCTargetMachine &getTargetMachine() const { return TM; }
203 
204   /// initializeSubtargetDependencies - Initializes using a CPU and feature string
205   /// so that we can use initializer lists for subtarget initialization.
206   PPCSubtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS);
207 
208 private:
209   void initializeEnvironment();
210   void initSubtargetFeatures(StringRef CPU, StringRef FS);
211 
212 public:
213   /// isPPC64 - Return true if we are generating code for 64-bit pointer mode.
214   ///
215   bool isPPC64() const;
216 
217   /// has64BitSupport - Return true if the selected CPU supports 64-bit
218   /// instructions, regardless of whether we are in 32-bit or 64-bit mode.
219   bool has64BitSupport() const { return Has64BitSupport; }
220   // useSoftFloat - Return true if soft-float option is turned on.
221   bool useSoftFloat() const {
222     if (isAIXABI() && !HasHardFloat)
223       report_fatal_error("soft-float is not yet supported on AIX.");
224     return !HasHardFloat;
225   }
226 
227   /// use64BitRegs - Return true if in 64-bit mode or if we should use 64-bit
228   /// registers in 32-bit mode when possible.  This can only true if
229   /// has64BitSupport() returns true.
230   bool use64BitRegs() const { return Use64BitRegs; }
231 
232   /// useCRBits - Return true if we should store and manipulate i1 values in
233   /// the individual condition register bits.
234   bool useCRBits() const { return UseCRBits; }
235 
236   // isLittleEndian - True if generating little-endian code
237   bool isLittleEndian() const { return IsLittleEndian; }
238 
239   // Specific obvious features.
240   bool hasFCPSGN() const { return HasFCPSGN; }
241   bool hasFSQRT() const { return HasFSQRT; }
242   bool hasFRE() const { return HasFRE; }
243   bool hasFRES() const { return HasFRES; }
244   bool hasFRSQRTE() const { return HasFRSQRTE; }
245   bool hasFRSQRTES() const { return HasFRSQRTES; }
246   bool hasRecipPrec() const { return HasRecipPrec; }
247   bool hasSTFIWX() const { return HasSTFIWX; }
248   bool hasLFIWAX() const { return HasLFIWAX; }
249   bool hasFPRND() const { return HasFPRND; }
250   bool hasFPCVT() const { return HasFPCVT; }
251   bool hasAltivec() const { return HasAltivec; }
252   bool hasSPE() const { return HasSPE; }
253   bool hasFPU() const { return HasFPU; }
254   bool hasVSX() const { return HasVSX; }
255   bool needsTwoConstNR() const { return NeedsTwoConstNR; }
256   bool hasP8Vector() const { return HasP8Vector; }
257   bool hasP8Altivec() const { return HasP8Altivec; }
258   bool hasP8Crypto() const { return HasP8Crypto; }
259   bool hasP9Vector() const { return HasP9Vector; }
260   bool hasP9Altivec() const { return HasP9Altivec; }
261   bool hasP10Vector() const { return HasP10Vector; }
262   bool hasPrefixInstrs() const { return HasPrefixInstrs; }
263   bool hasPCRelativeMemops() const { return HasPCRelativeMemops; }
264   bool hasMMA() const { return HasMMA; }
265   bool pairedVectorMemops() const { return PairedVectorMemops; }
266   bool hasMFOCRF() const { return HasMFOCRF; }
267   bool hasISEL() const { return HasISEL; }
268   bool hasBPERMD() const { return HasBPERMD; }
269   bool hasExtDiv() const { return HasExtDiv; }
270   bool hasCMPB() const { return HasCMPB; }
271   bool hasLDBRX() const { return HasLDBRX; }
272   bool isBookE() const { return IsBookE; }
273   bool hasOnlyMSYNC() const { return HasOnlyMSYNC; }
274   bool isPPC4xx() const { return IsPPC4xx; }
275   bool isPPC6xx() const { return IsPPC6xx; }
276   bool isSecurePlt() const {return SecurePlt; }
277   bool vectorsUseTwoUnits() const {return VectorsUseTwoUnits; }
278   bool isE500() const { return IsE500; }
279   bool isFeatureMFTB() const { return FeatureMFTB; }
280   bool allowsUnalignedFPAccess() const { return AllowsUnalignedFPAccess; }
281   bool isDeprecatedDST() const { return DeprecatedDST; }
282   bool hasICBT() const { return HasICBT; }
283   bool hasInvariantFunctionDescriptors() const {
284     return HasInvariantFunctionDescriptors;
285   }
286   bool usePPCPreRASchedStrategy() const { return UsePPCPreRASchedStrategy; }
287   bool usePPCPostRASchedStrategy() const { return UsePPCPostRASchedStrategy; }
288   bool hasPartwordAtomics() const { return HasPartwordAtomics; }
289   bool hasDirectMove() const { return HasDirectMove; }
290 
291   Align getPlatformStackAlignment() const {
292     return Align(16);
293   }
294 
295   unsigned  getRedZoneSize() const {
296     if (isPPC64())
297       // 288 bytes = 18*8 (FPRs) + 18*8 (GPRs, GPR13 reserved)
298       return 288;
299 
300     // AIX PPC32: 220 bytes = 18*8 (FPRs) + 19*4 (GPRs);
301     // PPC32 SVR4ABI has no redzone.
302     return isAIXABI() ? 220 : 0;
303   }
304 
305   bool hasHTM() const { return HasHTM; }
306   bool hasFloat128() const { return HasFloat128; }
307   bool isISA3_0() const { return IsISA3_0; }
308   bool isISA3_1() const { return IsISA3_1; }
309   bool useLongCalls() const { return UseLongCalls; }
310   bool hasFusion() const { return HasFusion; }
311   bool hasAddiLoadFusion() const { return HasAddiLoadFusion; }
312   bool hasAddisLoadFusion() const { return HasAddisLoadFusion; }
313   bool needsSwapsForVSXMemOps() const {
314     return hasVSX() && isLittleEndian() && !hasP9Vector();
315   }
316 
317   POPCNTDKind hasPOPCNTD() const { return HasPOPCNTD; }
318 
319   const Triple &getTargetTriple() const { return TargetTriple; }
320 
321   bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
322   bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); }
323   bool isTargetLinux() const { return TargetTriple.isOSLinux(); }
324 
325   bool isAIXABI() const { return TargetTriple.isOSAIX(); }
326   bool isSVR4ABI() const { return !isAIXABI(); }
327   bool isELFv2ABI() const;
328 
329   bool is64BitELFABI() const { return  isSVR4ABI() && isPPC64(); }
330   bool is32BitELFABI() const { return  isSVR4ABI() && !isPPC64(); }
331   bool isUsingPCRelativeCalls() const;
332 
333   /// Originally, this function return hasISEL(). Now we always enable it,
334   /// but may expand the ISEL instruction later.
335   bool enableEarlyIfConversion() const override { return true; }
336 
337   /// Scheduling customization.
338   bool enableMachineScheduler() const override;
339   /// Pipeliner customization.
340   bool enableMachinePipeliner() const override;
341   /// Machine Pipeliner customization
342   bool useDFAforSMS() const override;
343   /// This overrides the PostRAScheduler bit in the SchedModel for each CPU.
344   bool enablePostRAScheduler() const override;
345   AntiDepBreakMode getAntiDepBreakMode() const override;
346   void getCriticalPathRCs(RegClassVector &CriticalPathRCs) const override;
347 
348   void overrideSchedPolicy(MachineSchedPolicy &Policy,
349                            unsigned NumRegionInstrs) const override;
350   bool useAA() const override;
351 
352   bool enableSubRegLiveness() const override;
353 
354   /// True if the GV will be accessed via an indirect symbol.
355   bool isGVIndirectSymbol(const GlobalValue *GV) const;
356 
357   /// True if the ABI is descriptor based.
358   bool usesFunctionDescriptors() const {
359     // Both 32-bit and 64-bit AIX are descriptor based. For ELF only the 64-bit
360     // v1 ABI uses descriptors.
361     return isAIXABI() || (is64BitELFABI() && !isELFv2ABI());
362   }
363 
364   unsigned descriptorTOCAnchorOffset() const {
365     assert(usesFunctionDescriptors() &&
366            "Should only be called when the target uses descriptors.");
367     return IsPPC64 ? 8 : 4;
368   }
369 
370   unsigned descriptorEnvironmentPointerOffset() const {
371     assert(usesFunctionDescriptors() &&
372            "Should only be called when the target uses descriptors.");
373     return IsPPC64 ? 16 : 8;
374   }
375 
376   MCRegister getEnvironmentPointerRegister() const {
377     assert(usesFunctionDescriptors() &&
378            "Should only be called when the target uses descriptors.");
379      return IsPPC64 ? PPC::X11 : PPC::R11;
380   }
381 
382   MCRegister getTOCPointerRegister() const {
383     assert((is64BitELFABI() || isAIXABI()) &&
384            "Should only be called when the target is a TOC based ABI.");
385     return IsPPC64 ? PPC::X2 : PPC::R2;
386   }
387 
388   MCRegister getStackPointerRegister() const {
389     return IsPPC64 ? PPC::X1 : PPC::R1;
390   }
391 
392   bool isXRaySupported() const override { return IsPPC64 && IsLittleEndian; }
393 
394   bool isPredictableSelectIsExpensive() const {
395     return PredictableSelectIsExpensive;
396   }
397 };
398 } // End llvm namespace
399 
400 #endif
401