1 //===-- PowerPCSubtarget.cpp - PPC Subtarget Information ------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements the PPC specific subclass of TargetSubtargetInfo. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "PPCSubtarget.h" 15 #include "PPC.h" 16 #include "PPCRegisterInfo.h" 17 #include "llvm/CodeGen/MachineFunction.h" 18 #include "llvm/CodeGen/MachineScheduler.h" 19 #include "llvm/IR/Attributes.h" 20 #include "llvm/IR/Function.h" 21 #include "llvm/IR/GlobalValue.h" 22 #include "llvm/Support/Host.h" 23 #include "llvm/Support/TargetRegistry.h" 24 #include "llvm/Target/TargetMachine.h" 25 #include <cstdlib> 26 27 using namespace llvm; 28 29 #define DEBUG_TYPE "ppc-subtarget" 30 31 #define GET_SUBTARGETINFO_TARGET_DESC 32 #define GET_SUBTARGETINFO_CTOR 33 #include "PPCGenSubtargetInfo.inc" 34 35 /// Return the datalayout string of a subtarget. 36 static std::string getDataLayoutString(const Triple &T) { 37 bool is64Bit = T.getArch() == Triple::ppc64 || T.getArch() == Triple::ppc64le; 38 std::string Ret; 39 40 // Most PPC* platforms are big endian, PPC64LE is little endian. 41 if (T.getArch() == Triple::ppc64le) 42 Ret = "e"; 43 else 44 Ret = "E"; 45 46 Ret += DataLayout::getManglingComponent(T); 47 48 // PPC32 has 32 bit pointers. The PS3 (OS Lv2) is a PPC64 machine with 32 bit 49 // pointers. 50 if (!is64Bit || T.getOS() == Triple::Lv2) 51 Ret += "-p:32:32"; 52 53 // Note, the alignment values for f64 and i64 on ppc64 in Darwin 54 // documentation are wrong; these are correct (i.e. "what gcc does"). 55 if (is64Bit || !T.isOSDarwin()) 56 Ret += "-i64:64"; 57 else 58 Ret += "-f64:32:64"; 59 60 // PPC64 has 32 and 64 bit registers, PPC32 has only 32 bit ones. 61 if (is64Bit) 62 Ret += "-n32:64"; 63 else 64 Ret += "-n32"; 65 66 return Ret; 67 } 68 69 PPCSubtarget &PPCSubtarget::initializeSubtargetDependencies(StringRef CPU, 70 StringRef FS) { 71 initializeEnvironment(); 72 initSubtargetFeatures(CPU, FS); 73 return *this; 74 } 75 76 PPCSubtarget::PPCSubtarget(const std::string &TT, const std::string &CPU, 77 const std::string &FS, const PPCTargetMachine &TM) 78 : PPCGenSubtargetInfo(TT, CPU, FS), TargetTriple(TT), 79 DL(getDataLayoutString(TargetTriple)), 80 IsPPC64(TargetTriple.getArch() == Triple::ppc64 || 81 TargetTriple.getArch() == Triple::ppc64le), 82 TargetABI(PPC_ABI_UNKNOWN), 83 FrameLowering(initializeSubtargetDependencies(CPU, FS)), InstrInfo(*this), 84 TLInfo(TM), TSInfo(&DL) {} 85 86 void PPCSubtarget::initializeEnvironment() { 87 StackAlignment = 16; 88 DarwinDirective = PPC::DIR_NONE; 89 HasMFOCRF = false; 90 Has64BitSupport = false; 91 Use64BitRegs = false; 92 UseCRBits = false; 93 HasAltivec = false; 94 HasSPE = false; 95 HasQPX = false; 96 HasVSX = false; 97 HasP8Vector = false; 98 HasFCPSGN = false; 99 HasFSQRT = false; 100 HasFRE = false; 101 HasFRES = false; 102 HasFRSQRTE = false; 103 HasFRSQRTES = false; 104 HasRecipPrec = false; 105 HasSTFIWX = false; 106 HasLFIWAX = false; 107 HasFPRND = false; 108 HasFPCVT = false; 109 HasISEL = false; 110 HasPOPCNTD = false; 111 HasLDBRX = false; 112 IsBookE = false; 113 HasOnlyMSYNC = false; 114 IsPPC4xx = false; 115 IsPPC6xx = false; 116 IsE500 = false; 117 DeprecatedMFTB = false; 118 DeprecatedDST = false; 119 HasLazyResolverStubs = false; 120 } 121 122 void PPCSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) { 123 // Determine default and user specified characteristics 124 std::string CPUName = CPU; 125 if (CPUName.empty()) 126 CPUName = "generic"; 127 #if (defined(__APPLE__) || defined(__linux__)) && \ 128 (defined(__ppc__) || defined(__powerpc__)) 129 if (CPUName == "generic") 130 CPUName = sys::getHostCPUName(); 131 #endif 132 133 // Initialize scheduling itinerary for the specified CPU. 134 InstrItins = getInstrItineraryForCPU(CPUName); 135 136 // Parse features string. 137 ParseSubtargetFeatures(CPUName, FS); 138 139 // If the user requested use of 64-bit regs, but the cpu selected doesn't 140 // support it, ignore. 141 if (IsPPC64 && has64BitSupport()) 142 Use64BitRegs = true; 143 144 // Set up darwin-specific properties. 145 if (isDarwin()) 146 HasLazyResolverStubs = true; 147 148 // QPX requires a 32-byte aligned stack. Note that we need to do this if 149 // we're compiling for a BG/Q system regardless of whether or not QPX 150 // is enabled because external functions will assume this alignment. 151 if (hasQPX() || isBGQ()) 152 StackAlignment = 32; 153 154 // Determine endianness. 155 IsLittleEndian = (TargetTriple.getArch() == Triple::ppc64le); 156 157 // FIXME: For now, we disable VSX in little-endian mode until endian 158 // issues in those instructions can be addressed. 159 if (IsLittleEndian) { 160 HasVSX = false; 161 HasP8Vector = false; 162 } 163 164 // Determine default ABI. 165 if (TargetABI == PPC_ABI_UNKNOWN) { 166 if (!isDarwin() && IsPPC64) { 167 if (IsLittleEndian) 168 TargetABI = PPC_ABI_ELFv2; 169 else 170 TargetABI = PPC_ABI_ELFv1; 171 } 172 } 173 } 174 175 /// hasLazyResolverStub - Return true if accesses to the specified global have 176 /// to go through a dyld lazy resolution stub. This means that an extra load 177 /// is required to get the address of the global. 178 bool PPCSubtarget::hasLazyResolverStub(const GlobalValue *GV, 179 const TargetMachine &TM) const { 180 // We never have stubs if HasLazyResolverStubs=false or if in static mode. 181 if (!HasLazyResolverStubs || TM.getRelocationModel() == Reloc::Static) 182 return false; 183 // If symbol visibility is hidden, the extra load is not needed if 184 // the symbol is definitely defined in the current translation unit. 185 bool isDecl = GV->isDeclaration() && !GV->isMaterializable(); 186 if (GV->hasHiddenVisibility() && !isDecl && !GV->hasCommonLinkage()) 187 return false; 188 return GV->hasWeakLinkage() || GV->hasLinkOnceLinkage() || 189 GV->hasCommonLinkage() || isDecl; 190 } 191 192 // Embedded cores need aggressive scheduling (and some others also benefit). 193 static bool needsAggressiveScheduling(unsigned Directive) { 194 switch (Directive) { 195 default: return false; 196 case PPC::DIR_440: 197 case PPC::DIR_A2: 198 case PPC::DIR_E500mc: 199 case PPC::DIR_E5500: 200 case PPC::DIR_PWR7: 201 case PPC::DIR_PWR8: 202 return true; 203 } 204 } 205 206 bool PPCSubtarget::enableMachineScheduler() const { 207 // Enable MI scheduling for the embedded cores. 208 // FIXME: Enable this for all cores (some additional modeling 209 // may be necessary). 210 return needsAggressiveScheduling(DarwinDirective); 211 } 212 213 // This overrides the PostRAScheduler bit in the SchedModel for each CPU. 214 bool PPCSubtarget::enablePostMachineScheduler() const { return true; } 215 216 PPCGenSubtargetInfo::AntiDepBreakMode PPCSubtarget::getAntiDepBreakMode() const { 217 return TargetSubtargetInfo::ANTIDEP_ALL; 218 } 219 220 void PPCSubtarget::getCriticalPathRCs(RegClassVector &CriticalPathRCs) const { 221 CriticalPathRCs.clear(); 222 CriticalPathRCs.push_back(isPPC64() ? 223 &PPC::G8RCRegClass : &PPC::GPRCRegClass); 224 } 225 226 void PPCSubtarget::overrideSchedPolicy(MachineSchedPolicy &Policy, 227 MachineInstr *begin, 228 MachineInstr *end, 229 unsigned NumRegionInstrs) const { 230 if (needsAggressiveScheduling(DarwinDirective)) { 231 Policy.OnlyTopDown = false; 232 Policy.OnlyBottomUp = false; 233 } 234 235 // Spilling is generally expensive on all PPC cores, so always enable 236 // register-pressure tracking. 237 Policy.ShouldTrackPressure = true; 238 } 239 240 bool PPCSubtarget::useAA() const { 241 // Use AA during code generation for the embedded cores. 242 return needsAggressiveScheduling(DarwinDirective); 243 } 244 245