1 //===-- PowerPCSubtarget.cpp - PPC Subtarget Information ------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements the PPC specific subclass of TargetSubtargetInfo. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "PPCSubtarget.h" 15 #include "PPC.h" 16 #include "PPCRegisterInfo.h" 17 #include "llvm/IR/GlobalValue.h" 18 #include "llvm/Support/Host.h" 19 #include "llvm/Support/TargetRegistry.h" 20 #include "llvm/Target/TargetMachine.h" 21 #include <cstdlib> 22 23 #define GET_SUBTARGETINFO_TARGET_DESC 24 #define GET_SUBTARGETINFO_CTOR 25 #include "PPCGenSubtargetInfo.inc" 26 27 using namespace llvm; 28 29 PPCSubtarget::PPCSubtarget(const std::string &TT, const std::string &CPU, 30 const std::string &FS, bool is64Bit) 31 : PPCGenSubtargetInfo(TT, CPU, FS) 32 , StackAlignment(16) 33 , DarwinDirective(PPC::DIR_NONE) 34 , HasMFOCRF(false) 35 , Has64BitSupport(false) 36 , Use64BitRegs(false) 37 , IsPPC64(is64Bit) 38 , HasAltivec(false) 39 , HasQPX(false) 40 , HasFSQRT(false) 41 , HasFRE(false) 42 , HasFRES(false) 43 , HasFRSQRTE(false) 44 , HasFRSQRTES(false) 45 , HasRecipPrec(false) 46 , HasSTFIWX(false) 47 , HasLFIWAX(false) 48 , HasFPRND(false) 49 , HasFPCVT(false) 50 , HasISEL(false) 51 , HasPOPCNTD(false) 52 , HasLDBRX(false) 53 , IsBookE(false) 54 , HasLazyResolverStubs(false) 55 , IsJITCodeModel(false) 56 , TargetTriple(TT) { 57 58 // Determine default and user specified characteristics 59 std::string CPUName = CPU; 60 if (CPUName.empty()) 61 CPUName = "generic"; 62 #if (defined(__APPLE__) || defined(__linux__)) && \ 63 (defined(__ppc__) || defined(__powerpc__)) 64 if (CPUName == "generic") 65 CPUName = sys::getHostCPUName(); 66 #endif 67 68 // Initialize scheduling itinerary for the specified CPU. 69 InstrItins = getInstrItineraryForCPU(CPUName); 70 71 // Make sure 64-bit features are available when CPUname is generic 72 std::string FullFS = FS; 73 74 // If we are generating code for ppc64, verify that options make sense. 75 if (is64Bit) { 76 Has64BitSupport = true; 77 // Silently force 64-bit register use on ppc64. 78 Use64BitRegs = true; 79 if (!FullFS.empty()) 80 FullFS = "+64bit," + FullFS; 81 else 82 FullFS = "+64bit"; 83 } 84 85 // Parse features string. 86 ParseSubtargetFeatures(CPUName, FullFS); 87 88 // If the user requested use of 64-bit regs, but the cpu selected doesn't 89 // support it, ignore. 90 if (use64BitRegs() && !has64BitSupport()) 91 Use64BitRegs = false; 92 93 // Set up darwin-specific properties. 94 if (isDarwin()) 95 HasLazyResolverStubs = true; 96 97 // QPX requires a 32-byte aligned stack. Note that we need to do this if 98 // we're compiling for a BG/Q system regardless of whether or not QPX 99 // is enabled because external functions will assume this alignment. 100 if (hasQPX() || isBGQ()) 101 StackAlignment = 32; 102 } 103 104 /// SetJITMode - This is called to inform the subtarget info that we are 105 /// producing code for the JIT. 106 void PPCSubtarget::SetJITMode() { 107 // JIT mode doesn't want lazy resolver stubs, it knows exactly where 108 // everything is. This matters for PPC64, which codegens in PIC mode without 109 // stubs. 110 HasLazyResolverStubs = false; 111 112 // Calls to external functions need to use indirect calls 113 IsJITCodeModel = true; 114 } 115 116 117 /// hasLazyResolverStub - Return true if accesses to the specified global have 118 /// to go through a dyld lazy resolution stub. This means that an extra load 119 /// is required to get the address of the global. 120 bool PPCSubtarget::hasLazyResolverStub(const GlobalValue *GV, 121 const TargetMachine &TM) const { 122 // We never have stubs if HasLazyResolverStubs=false or if in static mode. 123 if (!HasLazyResolverStubs || TM.getRelocationModel() == Reloc::Static) 124 return false; 125 // If symbol visibility is hidden, the extra load is not needed if 126 // the symbol is definitely defined in the current translation unit. 127 bool isDecl = GV->isDeclaration() && !GV->isMaterializable(); 128 if (GV->hasHiddenVisibility() && !isDecl && !GV->hasCommonLinkage()) 129 return false; 130 return GV->hasWeakLinkage() || GV->hasLinkOnceLinkage() || 131 GV->hasCommonLinkage() || isDecl; 132 } 133 134 bool PPCSubtarget::enablePostRAScheduler( 135 CodeGenOpt::Level OptLevel, 136 TargetSubtargetInfo::AntiDepBreakMode& Mode, 137 RegClassVector& CriticalPathRCs) const { 138 // FIXME: It would be best to use TargetSubtargetInfo::ANTIDEP_ALL here, 139 // but we can't because we can't reassign the cr registers. There is a 140 // dependence between the cr register and the RLWINM instruction used 141 // to extract its value which the anti-dependency breaker can't currently 142 // see. Maybe we should make a late-expanded pseudo to encode this dependency. 143 // (the relevant code is in PPCDAGToDAGISel::SelectSETCC) 144 145 Mode = TargetSubtargetInfo::ANTIDEP_CRITICAL; 146 147 CriticalPathRCs.clear(); 148 149 if (isPPC64()) 150 CriticalPathRCs.push_back(&PPC::G8RCRegClass); 151 else 152 CriticalPathRCs.push_back(&PPC::GPRCRegClass); 153 154 CriticalPathRCs.push_back(&PPC::F8RCRegClass); 155 CriticalPathRCs.push_back(&PPC::VRRCRegClass); 156 157 return OptLevel >= CodeGenOpt::Default; 158 } 159 160