1 //===-- PowerPCSubtarget.cpp - PPC Subtarget Information ------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements the PPC specific subclass of TargetSubtargetInfo. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "PPCSubtarget.h" 15 #include "PPC.h" 16 #include "PPCRegisterInfo.h" 17 #include "llvm/CodeGen/MachineFunction.h" 18 #include "llvm/CodeGen/MachineScheduler.h" 19 #include "llvm/IR/Attributes.h" 20 #include "llvm/IR/Function.h" 21 #include "llvm/IR/GlobalValue.h" 22 #include "llvm/Support/CommandLine.h" 23 #include "llvm/Support/Host.h" 24 #include "llvm/Support/TargetRegistry.h" 25 #include "llvm/Target/TargetMachine.h" 26 #include <cstdlib> 27 28 using namespace llvm; 29 30 #define DEBUG_TYPE "ppc-subtarget" 31 32 #define GET_SUBTARGETINFO_TARGET_DESC 33 #define GET_SUBTARGETINFO_CTOR 34 #include "PPCGenSubtargetInfo.inc" 35 36 static cl::opt<bool> UseSubRegLiveness("ppc-track-subreg-liveness", 37 cl::desc("Enable subregister liveness tracking for PPC"), cl::Hidden); 38 39 /// Return the datalayout string of a subtarget. 40 static std::string getDataLayoutString(const Triple &T) { 41 bool is64Bit = T.getArch() == Triple::ppc64 || T.getArch() == Triple::ppc64le; 42 std::string Ret; 43 44 // Most PPC* platforms are big endian, PPC64LE is little endian. 45 if (T.getArch() == Triple::ppc64le) 46 Ret = "e"; 47 else 48 Ret = "E"; 49 50 Ret += DataLayout::getManglingComponent(T); 51 52 // PPC32 has 32 bit pointers. The PS3 (OS Lv2) is a PPC64 machine with 32 bit 53 // pointers. 54 if (!is64Bit || T.getOS() == Triple::Lv2) 55 Ret += "-p:32:32"; 56 57 // Note, the alignment values for f64 and i64 on ppc64 in Darwin 58 // documentation are wrong; these are correct (i.e. "what gcc does"). 59 if (is64Bit || !T.isOSDarwin()) 60 Ret += "-i64:64"; 61 else 62 Ret += "-f64:32:64"; 63 64 // PPC64 has 32 and 64 bit registers, PPC32 has only 32 bit ones. 65 if (is64Bit) 66 Ret += "-n32:64"; 67 else 68 Ret += "-n32"; 69 70 return Ret; 71 } 72 73 PPCSubtarget &PPCSubtarget::initializeSubtargetDependencies(StringRef CPU, 74 StringRef FS) { 75 initializeEnvironment(); 76 initSubtargetFeatures(CPU, FS); 77 return *this; 78 } 79 80 PPCSubtarget::PPCSubtarget(const std::string &TT, const std::string &CPU, 81 const std::string &FS, const PPCTargetMachine &TM) 82 : PPCGenSubtargetInfo(TT, CPU, FS), TargetTriple(TT), 83 DL(getDataLayoutString(TargetTriple)), 84 IsPPC64(TargetTriple.getArch() == Triple::ppc64 || 85 TargetTriple.getArch() == Triple::ppc64le), 86 TargetABI(PPC_ABI_UNKNOWN), 87 FrameLowering(initializeSubtargetDependencies(CPU, FS)), InstrInfo(*this), 88 TLInfo(TM), TSInfo(&DL) {} 89 90 void PPCSubtarget::initializeEnvironment() { 91 StackAlignment = 16; 92 DarwinDirective = PPC::DIR_NONE; 93 HasMFOCRF = false; 94 Has64BitSupport = false; 95 Use64BitRegs = false; 96 UseCRBits = false; 97 HasAltivec = false; 98 HasSPE = false; 99 HasQPX = false; 100 HasVSX = false; 101 HasP8Vector = false; 102 HasFCPSGN = false; 103 HasFSQRT = false; 104 HasFRE = false; 105 HasFRES = false; 106 HasFRSQRTE = false; 107 HasFRSQRTES = false; 108 HasRecipPrec = false; 109 HasSTFIWX = false; 110 HasLFIWAX = false; 111 HasFPRND = false; 112 HasFPCVT = false; 113 HasISEL = false; 114 HasPOPCNTD = false; 115 HasCMPB = false; 116 HasLDBRX = false; 117 IsBookE = false; 118 HasOnlyMSYNC = false; 119 IsPPC4xx = false; 120 IsPPC6xx = false; 121 IsE500 = false; 122 DeprecatedMFTB = false; 123 DeprecatedDST = false; 124 HasLazyResolverStubs = false; 125 HasICBT = false; 126 127 } 128 129 void PPCSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) { 130 // Determine default and user specified characteristics 131 std::string CPUName = CPU; 132 if (CPUName.empty()) 133 CPUName = "generic"; 134 #if (defined(__APPLE__) || defined(__linux__)) && \ 135 (defined(__ppc__) || defined(__powerpc__)) 136 if (CPUName == "generic") 137 CPUName = sys::getHostCPUName(); 138 #endif 139 140 // Initialize scheduling itinerary for the specified CPU. 141 InstrItins = getInstrItineraryForCPU(CPUName); 142 143 // Parse features string. 144 ParseSubtargetFeatures(CPUName, FS); 145 146 // If the user requested use of 64-bit regs, but the cpu selected doesn't 147 // support it, ignore. 148 if (IsPPC64 && has64BitSupport()) 149 Use64BitRegs = true; 150 151 // Set up darwin-specific properties. 152 if (isDarwin()) 153 HasLazyResolverStubs = true; 154 155 // QPX requires a 32-byte aligned stack. Note that we need to do this if 156 // we're compiling for a BG/Q system regardless of whether or not QPX 157 // is enabled because external functions will assume this alignment. 158 if (hasQPX() || isBGQ()) 159 StackAlignment = 32; 160 161 // Determine endianness. 162 IsLittleEndian = (TargetTriple.getArch() == Triple::ppc64le); 163 164 // Determine default ABI. 165 if (TargetABI == PPC_ABI_UNKNOWN) { 166 if (!isDarwin() && IsPPC64) { 167 if (IsLittleEndian) 168 TargetABI = PPC_ABI_ELFv2; 169 else 170 TargetABI = PPC_ABI_ELFv1; 171 } 172 } 173 } 174 175 /// hasLazyResolverStub - Return true if accesses to the specified global have 176 /// to go through a dyld lazy resolution stub. This means that an extra load 177 /// is required to get the address of the global. 178 bool PPCSubtarget::hasLazyResolverStub(const GlobalValue *GV, 179 const TargetMachine &TM) const { 180 // We never have stubs if HasLazyResolverStubs=false or if in static mode. 181 if (!HasLazyResolverStubs || TM.getRelocationModel() == Reloc::Static) 182 return false; 183 bool isDecl = GV->isDeclaration(); 184 if (GV->hasHiddenVisibility() && !isDecl && !GV->hasCommonLinkage()) 185 return false; 186 return GV->hasWeakLinkage() || GV->hasLinkOnceLinkage() || 187 GV->hasCommonLinkage() || isDecl; 188 } 189 190 // Embedded cores need aggressive scheduling (and some others also benefit). 191 static bool needsAggressiveScheduling(unsigned Directive) { 192 switch (Directive) { 193 default: return false; 194 case PPC::DIR_440: 195 case PPC::DIR_A2: 196 case PPC::DIR_E500mc: 197 case PPC::DIR_E5500: 198 case PPC::DIR_PWR7: 199 case PPC::DIR_PWR8: 200 return true; 201 } 202 } 203 204 bool PPCSubtarget::enableMachineScheduler() const { 205 // Enable MI scheduling for the embedded cores. 206 // FIXME: Enable this for all cores (some additional modeling 207 // may be necessary). 208 return needsAggressiveScheduling(DarwinDirective); 209 } 210 211 // This overrides the PostRAScheduler bit in the SchedModel for each CPU. 212 bool PPCSubtarget::enablePostMachineScheduler() const { return true; } 213 214 PPCGenSubtargetInfo::AntiDepBreakMode PPCSubtarget::getAntiDepBreakMode() const { 215 return TargetSubtargetInfo::ANTIDEP_ALL; 216 } 217 218 void PPCSubtarget::getCriticalPathRCs(RegClassVector &CriticalPathRCs) const { 219 CriticalPathRCs.clear(); 220 CriticalPathRCs.push_back(isPPC64() ? 221 &PPC::G8RCRegClass : &PPC::GPRCRegClass); 222 } 223 224 void PPCSubtarget::overrideSchedPolicy(MachineSchedPolicy &Policy, 225 MachineInstr *begin, 226 MachineInstr *end, 227 unsigned NumRegionInstrs) const { 228 if (needsAggressiveScheduling(DarwinDirective)) { 229 Policy.OnlyTopDown = false; 230 Policy.OnlyBottomUp = false; 231 } 232 233 // Spilling is generally expensive on all PPC cores, so always enable 234 // register-pressure tracking. 235 Policy.ShouldTrackPressure = true; 236 } 237 238 bool PPCSubtarget::useAA() const { 239 // Use AA during code generation for the embedded cores. 240 return needsAggressiveScheduling(DarwinDirective); 241 } 242 243 bool PPCSubtarget::enableSubRegLiveness() const { 244 return UseSubRegLiveness; 245 } 246 247