1 //===-- PowerPCSubtarget.cpp - PPC Subtarget Information ------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file implements the PPC specific subclass of TargetSubtargetInfo. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "PPCSubtarget.h" 14 #include "PPC.h" 15 #include "PPCRegisterInfo.h" 16 #include "PPCTargetMachine.h" 17 #include "llvm/CodeGen/MachineFunction.h" 18 #include "llvm/CodeGen/MachineScheduler.h" 19 #include "llvm/IR/Attributes.h" 20 #include "llvm/IR/Function.h" 21 #include "llvm/IR/GlobalValue.h" 22 #include "llvm/Support/CommandLine.h" 23 #include "llvm/Support/TargetRegistry.h" 24 #include "llvm/Target/TargetMachine.h" 25 #include <cstdlib> 26 27 using namespace llvm; 28 29 #define DEBUG_TYPE "ppc-subtarget" 30 31 #define GET_SUBTARGETINFO_TARGET_DESC 32 #define GET_SUBTARGETINFO_CTOR 33 #include "PPCGenSubtargetInfo.inc" 34 35 static cl::opt<bool> UseSubRegLiveness("ppc-track-subreg-liveness", 36 cl::desc("Enable subregister liveness tracking for PPC"), cl::Hidden); 37 38 static cl::opt<bool> QPXStackUnaligned("qpx-stack-unaligned", 39 cl::desc("Even when QPX is enabled the stack is not 32-byte aligned"), 40 cl::Hidden); 41 42 PPCSubtarget &PPCSubtarget::initializeSubtargetDependencies(StringRef CPU, 43 StringRef FS) { 44 initializeEnvironment(); 45 initSubtargetFeatures(CPU, FS); 46 return *this; 47 } 48 49 PPCSubtarget::PPCSubtarget(const Triple &TT, const std::string &CPU, 50 const std::string &FS, const PPCTargetMachine &TM) 51 : PPCGenSubtargetInfo(TT, CPU, FS), TargetTriple(TT), 52 IsPPC64(TargetTriple.getArch() == Triple::ppc64 || 53 TargetTriple.getArch() == Triple::ppc64le), 54 TM(TM), FrameLowering(initializeSubtargetDependencies(CPU, FS)), 55 InstrInfo(*this), TLInfo(TM, *this) {} 56 57 void PPCSubtarget::initializeEnvironment() { 58 StackAlignment = 16; 59 DarwinDirective = PPC::DIR_NONE; 60 HasMFOCRF = false; 61 Has64BitSupport = false; 62 Use64BitRegs = false; 63 UseCRBits = false; 64 HasHardFloat = false; 65 HasAltivec = false; 66 HasSPE = false; 67 HasFPU = false; 68 HasQPX = false; 69 HasVSX = false; 70 NeedsTwoConstNR = false; 71 HasP8Vector = false; 72 HasP8Altivec = false; 73 HasP8Crypto = false; 74 HasP9Vector = false; 75 HasP9Altivec = false; 76 HasFCPSGN = false; 77 HasFSQRT = false; 78 HasFRE = false; 79 HasFRES = false; 80 HasFRSQRTE = false; 81 HasFRSQRTES = false; 82 HasRecipPrec = false; 83 HasSTFIWX = false; 84 HasLFIWAX = false; 85 HasFPRND = false; 86 HasFPCVT = false; 87 HasISEL = false; 88 HasBPERMD = false; 89 HasExtDiv = false; 90 HasCMPB = false; 91 HasLDBRX = false; 92 IsBookE = false; 93 HasOnlyMSYNC = false; 94 IsPPC4xx = false; 95 IsPPC6xx = false; 96 IsE500 = false; 97 FeatureMFTB = false; 98 DeprecatedDST = false; 99 HasLazyResolverStubs = false; 100 HasICBT = false; 101 HasInvariantFunctionDescriptors = false; 102 HasPartwordAtomics = false; 103 HasDirectMove = false; 104 IsQPXStackUnaligned = false; 105 HasHTM = false; 106 HasFusion = false; 107 HasFloat128 = false; 108 IsISA3_0 = false; 109 UseLongCalls = false; 110 SecurePlt = false; 111 VectorsUseTwoUnits = false; 112 UsePPCPreRASchedStrategy = false; 113 UsePPCPostRASchedStrategy = false; 114 115 HasPOPCNTD = POPCNTD_Unavailable; 116 } 117 118 void PPCSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) { 119 // Determine default and user specified characteristics 120 std::string CPUName = CPU; 121 if (CPUName.empty() || CPU == "generic") { 122 // If cross-compiling with -march=ppc64le without -mcpu 123 if (TargetTriple.getArch() == Triple::ppc64le) 124 CPUName = "ppc64le"; 125 else 126 CPUName = "generic"; 127 } 128 129 // Initialize scheduling itinerary for the specified CPU. 130 InstrItins = getInstrItineraryForCPU(CPUName); 131 132 // Parse features string. 133 ParseSubtargetFeatures(CPUName, FS); 134 135 // If the user requested use of 64-bit regs, but the cpu selected doesn't 136 // support it, ignore. 137 if (IsPPC64 && has64BitSupport()) 138 Use64BitRegs = true; 139 140 // Set up darwin-specific properties. 141 if (isDarwin()) 142 HasLazyResolverStubs = true; 143 144 if (TargetTriple.isOSNetBSD() || TargetTriple.isOSOpenBSD()) 145 SecurePlt = true; 146 147 if (HasSPE && IsPPC64) 148 report_fatal_error( "SPE is only supported for 32-bit targets.\n", false); 149 if (HasSPE && (HasAltivec || HasQPX || HasVSX || HasFPU)) 150 report_fatal_error( 151 "SPE and traditional floating point cannot both be enabled.\n", false); 152 153 // If not SPE, set standard FPU 154 if (!HasSPE) 155 HasFPU = true; 156 157 // QPX requires a 32-byte aligned stack. Note that we need to do this if 158 // we're compiling for a BG/Q system regardless of whether or not QPX 159 // is enabled because external functions will assume this alignment. 160 IsQPXStackUnaligned = QPXStackUnaligned; 161 StackAlignment = getPlatformStackAlignment(); 162 163 // Determine endianness. 164 // FIXME: Part of the TargetMachine. 165 IsLittleEndian = (TargetTriple.getArch() == Triple::ppc64le); 166 } 167 168 /// Return true if accesses to the specified global have to go through a dyld 169 /// lazy resolution stub. This means that an extra load is required to get the 170 /// address of the global. 171 bool PPCSubtarget::hasLazyResolverStub(const GlobalValue *GV) const { 172 if (!HasLazyResolverStubs) 173 return false; 174 if (!TM.shouldAssumeDSOLocal(*GV->getParent(), GV)) 175 return true; 176 // 32 bit macho has no relocation for a-b if a is undefined, even if b is in 177 // the section that is being relocated. This means we have to use o load even 178 // for GVs that are known to be local to the dso. 179 if (GV->isDeclarationForLinker() || GV->hasCommonLinkage()) 180 return true; 181 return false; 182 } 183 184 bool PPCSubtarget::enableMachineScheduler() const { 185 return true; 186 } 187 188 // This overrides the PostRAScheduler bit in the SchedModel for each CPU. 189 bool PPCSubtarget::enablePostRAScheduler() const { return true; } 190 191 PPCGenSubtargetInfo::AntiDepBreakMode PPCSubtarget::getAntiDepBreakMode() const { 192 return TargetSubtargetInfo::ANTIDEP_ALL; 193 } 194 195 void PPCSubtarget::getCriticalPathRCs(RegClassVector &CriticalPathRCs) const { 196 CriticalPathRCs.clear(); 197 CriticalPathRCs.push_back(isPPC64() ? 198 &PPC::G8RCRegClass : &PPC::GPRCRegClass); 199 } 200 201 void PPCSubtarget::overrideSchedPolicy(MachineSchedPolicy &Policy, 202 unsigned NumRegionInstrs) const { 203 // The GenericScheduler that we use defaults to scheduling bottom up only. 204 // We want to schedule from both the top and the bottom and so we set 205 // OnlyBottomUp to false. 206 // We want to do bi-directional scheduling since it provides a more balanced 207 // schedule leading to better performance. 208 Policy.OnlyBottomUp = false; 209 // Spilling is generally expensive on all PPC cores, so always enable 210 // register-pressure tracking. 211 Policy.ShouldTrackPressure = true; 212 } 213 214 bool PPCSubtarget::useAA() const { 215 return true; 216 } 217 218 bool PPCSubtarget::enableSubRegLiveness() const { 219 return UseSubRegLiveness; 220 } 221 222 unsigned char 223 PPCSubtarget::classifyGlobalReference(const GlobalValue *GV) const { 224 // Note that currently we don't generate non-pic references. 225 // If a caller wants that, this will have to be updated. 226 227 // Large code model always uses the TOC even for local symbols. 228 if (TM.getCodeModel() == CodeModel::Large) 229 return PPCII::MO_PIC_FLAG | PPCII::MO_NLP_FLAG; 230 231 if (TM.shouldAssumeDSOLocal(*GV->getParent(), GV)) 232 return PPCII::MO_PIC_FLAG; 233 return PPCII::MO_PIC_FLAG | PPCII::MO_NLP_FLAG; 234 } 235 236 bool PPCSubtarget::isELFv2ABI() const { return TM.isELFv2ABI(); } 237 bool PPCSubtarget::isPPC64() const { return TM.isPPC64(); } 238