1 //===-- PowerPCSubtarget.cpp - PPC Subtarget Information ------------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the PPC specific subclass of TargetSubtargetInfo.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "PPCSubtarget.h"
15 #include "PPC.h"
16 #include "PPCRegisterInfo.h"
17 #include "llvm/IR/GlobalValue.h"
18 #include "llvm/Support/Host.h"
19 #include "llvm/Support/TargetRegistry.h"
20 #include "llvm/Target/TargetMachine.h"
21 #include <cstdlib>
22 
23 #define GET_SUBTARGETINFO_TARGET_DESC
24 #define GET_SUBTARGETINFO_CTOR
25 #include "PPCGenSubtargetInfo.inc"
26 
27 using namespace llvm;
28 
29 PPCSubtarget::PPCSubtarget(const std::string &TT, const std::string &CPU,
30                            const std::string &FS, bool is64Bit)
31   : PPCGenSubtargetInfo(TT, CPU, FS)
32   , StackAlignment(16)
33   , DarwinDirective(PPC::DIR_NONE)
34   , HasMFOCRF(false)
35   , Has64BitSupport(false)
36   , Use64BitRegs(false)
37   , IsPPC64(is64Bit)
38   , HasAltivec(false)
39   , HasFSQRT(false)
40   , HasSTFIWX(false)
41   , HasISEL(false)
42   , IsBookE(false)
43   , HasLazyResolverStubs(false)
44   , IsJITCodeModel(false)
45   , TargetTriple(TT) {
46 
47   // Determine default and user specified characteristics
48   std::string CPUName = CPU;
49   if (CPUName.empty())
50     CPUName = "generic";
51 #if (defined(__APPLE__) || defined(__linux__)) && \
52     (defined(__ppc__) || defined(__powerpc__))
53   if (CPUName == "generic")
54     CPUName = sys::getHostCPUName();
55 #endif
56 
57   // Initialize scheduling itinerary for the specified CPU.
58   InstrItins = getInstrItineraryForCPU(CPUName);
59 
60   // Make sure 64-bit features are available when CPUname is generic
61   std::string FullFS = FS;
62 
63   // If we are generating code for ppc64, verify that options make sense.
64   if (is64Bit) {
65     Has64BitSupport = true;
66     // Silently force 64-bit register use on ppc64.
67     Use64BitRegs = true;
68     if (!FullFS.empty())
69       FullFS = "+64bit," + FullFS;
70     else
71       FullFS = "+64bit";
72   }
73 
74   // Parse features string.
75   ParseSubtargetFeatures(CPUName, FullFS);
76 
77   // If the user requested use of 64-bit regs, but the cpu selected doesn't
78   // support it, ignore.
79   if (use64BitRegs() && !has64BitSupport())
80     Use64BitRegs = false;
81 
82   // Set up darwin-specific properties.
83   if (isDarwin())
84     HasLazyResolverStubs = true;
85 }
86 
87 /// SetJITMode - This is called to inform the subtarget info that we are
88 /// producing code for the JIT.
89 void PPCSubtarget::SetJITMode() {
90   // JIT mode doesn't want lazy resolver stubs, it knows exactly where
91   // everything is.  This matters for PPC64, which codegens in PIC mode without
92   // stubs.
93   HasLazyResolverStubs = false;
94 
95   // Calls to external functions need to use indirect calls
96   IsJITCodeModel = true;
97 }
98 
99 
100 /// hasLazyResolverStub - Return true if accesses to the specified global have
101 /// to go through a dyld lazy resolution stub.  This means that an extra load
102 /// is required to get the address of the global.
103 bool PPCSubtarget::hasLazyResolverStub(const GlobalValue *GV,
104                                        const TargetMachine &TM) const {
105   // We never have stubs if HasLazyResolverStubs=false or if in static mode.
106   if (!HasLazyResolverStubs || TM.getRelocationModel() == Reloc::Static)
107     return false;
108   // If symbol visibility is hidden, the extra load is not needed if
109   // the symbol is definitely defined in the current translation unit.
110   bool isDecl = GV->isDeclaration() && !GV->isMaterializable();
111   if (GV->hasHiddenVisibility() && !isDecl && !GV->hasCommonLinkage())
112     return false;
113   return GV->hasWeakLinkage() || GV->hasLinkOnceLinkage() ||
114          GV->hasCommonLinkage() || isDecl;
115 }
116 
117 bool PPCSubtarget::enablePostRAScheduler(
118            CodeGenOpt::Level OptLevel,
119            TargetSubtargetInfo::AntiDepBreakMode& Mode,
120            RegClassVector& CriticalPathRCs) const {
121   // FIXME: It would be best to use TargetSubtargetInfo::ANTIDEP_ALL here,
122   // but we can't because we can't reassign the cr registers. There is a
123   // dependence between the cr register and the RLWINM instruction used
124   // to extract its value which the anti-dependency breaker can't currently
125   // see. Maybe we should make a late-expanded pseudo to encode this dependency.
126   // (the relevant code is in PPCDAGToDAGISel::SelectSETCC)
127 
128   Mode = TargetSubtargetInfo::ANTIDEP_CRITICAL;
129 
130   CriticalPathRCs.clear();
131 
132   if (isPPC64())
133     CriticalPathRCs.push_back(&PPC::G8RCRegClass);
134   else
135     CriticalPathRCs.push_back(&PPC::GPRCRegClass);
136 
137   CriticalPathRCs.push_back(&PPC::F8RCRegClass);
138   CriticalPathRCs.push_back(&PPC::VRRCRegClass);
139 
140   return OptLevel >= CodeGenOpt::Default;
141 }
142 
143