1 //===-- PowerPCSubtarget.cpp - PPC Subtarget Information ------------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the PPC specific subclass of TargetSubtargetInfo.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "PPCSubtarget.h"
15 #include "PPC.h"
16 #include "PPCRegisterInfo.h"
17 #include "PPCTargetMachine.h"
18 #include "llvm/CodeGen/MachineFunction.h"
19 #include "llvm/CodeGen/MachineScheduler.h"
20 #include "llvm/IR/Attributes.h"
21 #include "llvm/IR/Function.h"
22 #include "llvm/IR/GlobalValue.h"
23 #include "llvm/Support/CommandLine.h"
24 #include "llvm/Support/TargetRegistry.h"
25 #include "llvm/Target/TargetMachine.h"
26 #include <cstdlib>
27 
28 using namespace llvm;
29 
30 #define DEBUG_TYPE "ppc-subtarget"
31 
32 #define GET_SUBTARGETINFO_TARGET_DESC
33 #define GET_SUBTARGETINFO_CTOR
34 #include "PPCGenSubtargetInfo.inc"
35 
36 static cl::opt<bool> UseSubRegLiveness("ppc-track-subreg-liveness",
37 cl::desc("Enable subregister liveness tracking for PPC"), cl::Hidden);
38 
39 static cl::opt<bool> QPXStackUnaligned("qpx-stack-unaligned",
40   cl::desc("Even when QPX is enabled the stack is not 32-byte aligned"),
41   cl::Hidden);
42 
43 PPCSubtarget &PPCSubtarget::initializeSubtargetDependencies(StringRef CPU,
44                                                             StringRef FS) {
45   initializeEnvironment();
46   initSubtargetFeatures(CPU, FS);
47   return *this;
48 }
49 
50 PPCSubtarget::PPCSubtarget(const Triple &TT, const std::string &CPU,
51                            const std::string &FS, const PPCTargetMachine &TM)
52     : PPCGenSubtargetInfo(TT, CPU, FS), TargetTriple(TT),
53       IsPPC64(TargetTriple.getArch() == Triple::ppc64 ||
54               TargetTriple.getArch() == Triple::ppc64le),
55       TM(TM), FrameLowering(initializeSubtargetDependencies(CPU, FS)),
56       InstrInfo(*this), TLInfo(TM, *this) {}
57 
58 void PPCSubtarget::initializeEnvironment() {
59   StackAlignment = 16;
60   DarwinDirective = PPC::DIR_NONE;
61   HasMFOCRF = false;
62   Has64BitSupport = false;
63   Use64BitRegs = false;
64   UseCRBits = false;
65   UseSoftFloat = false;
66   HasAltivec = false;
67   HasSPE = false;
68   HasQPX = false;
69   HasVSX = false;
70   HasP8Vector = false;
71   HasP8Altivec = false;
72   HasP8Crypto = false;
73   HasP9Vector = false;
74   HasP9Altivec = false;
75   HasFCPSGN = false;
76   HasFSQRT = false;
77   HasFRE = false;
78   HasFRES = false;
79   HasFRSQRTE = false;
80   HasFRSQRTES = false;
81   HasRecipPrec = false;
82   HasSTFIWX = false;
83   HasLFIWAX = false;
84   HasFPRND = false;
85   HasFPCVT = false;
86   HasISEL = false;
87   HasPOPCNTD = false;
88   HasBPERMD = false;
89   HasExtDiv = false;
90   HasCMPB = false;
91   HasLDBRX = false;
92   IsBookE = false;
93   HasOnlyMSYNC = false;
94   IsPPC4xx = false;
95   IsPPC6xx = false;
96   IsE500 = false;
97   FeatureMFTB = false;
98   DeprecatedDST = false;
99   HasLazyResolverStubs = false;
100   HasICBT = false;
101   HasInvariantFunctionDescriptors = false;
102   HasPartwordAtomics = false;
103   HasDirectMove = false;
104   IsQPXStackUnaligned = false;
105   HasHTM = false;
106   HasFusion = false;
107   HasFloat128 = false;
108 }
109 
110 void PPCSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) {
111   // Determine default and user specified characteristics
112   std::string CPUName = CPU;
113   if (CPUName.empty() || CPU == "generic") {
114     // If cross-compiling with -march=ppc64le without -mcpu
115     if (TargetTriple.getArch() == Triple::ppc64le)
116       CPUName = "ppc64le";
117     else
118       CPUName = "generic";
119   }
120 
121   // Initialize scheduling itinerary for the specified CPU.
122   InstrItins = getInstrItineraryForCPU(CPUName);
123 
124   // Parse features string.
125   ParseSubtargetFeatures(CPUName, FS);
126 
127   // If the user requested use of 64-bit regs, but the cpu selected doesn't
128   // support it, ignore.
129   if (IsPPC64 && has64BitSupport())
130     Use64BitRegs = true;
131 
132   // Set up darwin-specific properties.
133   if (isDarwin())
134     HasLazyResolverStubs = true;
135 
136   // QPX requires a 32-byte aligned stack. Note that we need to do this if
137   // we're compiling for a BG/Q system regardless of whether or not QPX
138   // is enabled because external functions will assume this alignment.
139   IsQPXStackUnaligned = QPXStackUnaligned;
140   StackAlignment = getPlatformStackAlignment();
141 
142   // Determine endianness.
143   // FIXME: Part of the TargetMachine.
144   IsLittleEndian = (TargetTriple.getArch() == Triple::ppc64le);
145 }
146 
147 /// hasLazyResolverStub - Return true if accesses to the specified global have
148 /// to go through a dyld lazy resolution stub.  This means that an extra load
149 /// is required to get the address of the global.
150 bool PPCSubtarget::hasLazyResolverStub(const GlobalValue *GV) const {
151   // We never have stubs if HasLazyResolverStubs=false or if in static mode.
152   if (!HasLazyResolverStubs || TM.getRelocationModel() == Reloc::Static)
153     return false;
154   bool isDecl = GV->isDeclaration();
155   if (GV->hasHiddenVisibility() && !isDecl && !GV->hasCommonLinkage())
156     return false;
157   return GV->hasWeakLinkage() || GV->hasLinkOnceLinkage() ||
158          GV->hasCommonLinkage() || isDecl;
159 }
160 
161 // Embedded cores need aggressive scheduling (and some others also benefit).
162 static bool needsAggressiveScheduling(unsigned Directive) {
163   switch (Directive) {
164   default: return false;
165   case PPC::DIR_440:
166   case PPC::DIR_A2:
167   case PPC::DIR_E500mc:
168   case PPC::DIR_E5500:
169   case PPC::DIR_PWR7:
170   case PPC::DIR_PWR8:
171     return true;
172   }
173 }
174 
175 bool PPCSubtarget::enableMachineScheduler() const {
176   // Enable MI scheduling for the embedded cores.
177   // FIXME: Enable this for all cores (some additional modeling
178   // may be necessary).
179   return needsAggressiveScheduling(DarwinDirective);
180 }
181 
182 // This overrides the PostRAScheduler bit in the SchedModel for each CPU.
183 bool PPCSubtarget::enablePostRAScheduler() const { return true; }
184 
185 PPCGenSubtargetInfo::AntiDepBreakMode PPCSubtarget::getAntiDepBreakMode() const {
186   return TargetSubtargetInfo::ANTIDEP_ALL;
187 }
188 
189 void PPCSubtarget::getCriticalPathRCs(RegClassVector &CriticalPathRCs) const {
190   CriticalPathRCs.clear();
191   CriticalPathRCs.push_back(isPPC64() ?
192                             &PPC::G8RCRegClass : &PPC::GPRCRegClass);
193 }
194 
195 void PPCSubtarget::overrideSchedPolicy(MachineSchedPolicy &Policy,
196                                        MachineInstr *begin,
197                                        MachineInstr *end,
198                                        unsigned NumRegionInstrs) const {
199   if (needsAggressiveScheduling(DarwinDirective)) {
200     Policy.OnlyTopDown = false;
201     Policy.OnlyBottomUp = false;
202   }
203 
204   // Spilling is generally expensive on all PPC cores, so always enable
205   // register-pressure tracking.
206   Policy.ShouldTrackPressure = true;
207 }
208 
209 bool PPCSubtarget::useAA() const {
210   // Use AA during code generation for the embedded cores.
211   return needsAggressiveScheduling(DarwinDirective);
212 }
213 
214 bool PPCSubtarget::enableSubRegLiveness() const {
215   return UseSubRegLiveness;
216 }
217 
218 unsigned char PPCSubtarget::classifyGlobalReference(
219     const GlobalValue *GV) const {
220   // Note that currently we don't generate non-pic references.
221   // If a caller wants that, this will have to be updated.
222 
223   // Large code model always uses the TOC even for local symbols.
224   if (TM.getCodeModel() == CodeModel::Large)
225     return PPCII::MO_PIC_FLAG | PPCII::MO_NLP_FLAG;
226 
227   unsigned char flags = PPCII::MO_PIC_FLAG;
228 
229   // Only if the relocation mode is PIC do we have to worry about
230   // interposition. In all other cases we can use a slightly looser standard to
231   // decide how to access the symbol.
232   if (TM.getRelocationModel() == Reloc::PIC_) {
233     // If it's local, or it's non-default, it can't be interposed.
234     if (!GV->hasLocalLinkage() &&
235         GV->hasDefaultVisibility()) {
236       flags |= PPCII::MO_NLP_FLAG;
237     }
238     return flags;
239   }
240 
241   if (GV->isStrongDefinitionForLinker())
242     return flags;
243   return flags | PPCII::MO_NLP_FLAG;
244 }
245 
246 bool PPCSubtarget::isELFv2ABI() const { return TM.isELFv2ABI(); }
247 bool PPCSubtarget::isPPC64() const { return TM.isPPC64(); }
248