1 //===-- PowerPCSubtarget.cpp - PPC Subtarget Information ------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements the PPC specific subclass of TargetSubtargetInfo. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "PPCSubtarget.h" 15 #include "PPC.h" 16 #include "PPCRegisterInfo.h" 17 #include "PPCTargetMachine.h" 18 #include "llvm/CodeGen/MachineFunction.h" 19 #include "llvm/CodeGen/MachineScheduler.h" 20 #include "llvm/IR/Attributes.h" 21 #include "llvm/IR/Function.h" 22 #include "llvm/IR/GlobalValue.h" 23 #include "llvm/Support/CommandLine.h" 24 #include "llvm/Support/Host.h" 25 #include "llvm/Support/TargetRegistry.h" 26 #include "llvm/Target/TargetMachine.h" 27 #include <cstdlib> 28 29 using namespace llvm; 30 31 #define DEBUG_TYPE "ppc-subtarget" 32 33 #define GET_SUBTARGETINFO_TARGET_DESC 34 #define GET_SUBTARGETINFO_CTOR 35 #include "PPCGenSubtargetInfo.inc" 36 37 static cl::opt<bool> UseSubRegLiveness("ppc-track-subreg-liveness", 38 cl::desc("Enable subregister liveness tracking for PPC"), cl::Hidden); 39 40 static cl::opt<bool> QPXStackUnaligned("qpx-stack-unaligned", 41 cl::desc("Even when QPX is enabled the stack is not 32-byte aligned"), 42 cl::Hidden); 43 44 PPCSubtarget &PPCSubtarget::initializeSubtargetDependencies(StringRef CPU, 45 StringRef FS) { 46 initializeEnvironment(); 47 initSubtargetFeatures(CPU, FS); 48 return *this; 49 } 50 51 PPCSubtarget::PPCSubtarget(const std::string &TT, const std::string &CPU, 52 const std::string &FS, const PPCTargetMachine &TM) 53 : PPCGenSubtargetInfo(TT, CPU, FS), TargetTriple(TT), 54 IsPPC64(TargetTriple.getArch() == Triple::ppc64 || 55 TargetTriple.getArch() == Triple::ppc64le), 56 TM(TM), FrameLowering(initializeSubtargetDependencies(CPU, FS)), 57 InstrInfo(*this), TLInfo(TM, *this), TSInfo(TM.getDataLayout()) {} 58 59 void PPCSubtarget::initializeEnvironment() { 60 StackAlignment = 16; 61 DarwinDirective = PPC::DIR_NONE; 62 HasMFOCRF = false; 63 Has64BitSupport = false; 64 Use64BitRegs = false; 65 UseCRBits = false; 66 HasAltivec = false; 67 HasSPE = false; 68 HasQPX = false; 69 HasVSX = false; 70 HasP8Vector = false; 71 HasP8Altivec = false; 72 HasP8Crypto = false; 73 HasFCPSGN = false; 74 HasFSQRT = false; 75 HasFRE = false; 76 HasFRES = false; 77 HasFRSQRTE = false; 78 HasFRSQRTES = false; 79 HasRecipPrec = false; 80 HasSTFIWX = false; 81 HasLFIWAX = false; 82 HasFPRND = false; 83 HasFPCVT = false; 84 HasISEL = false; 85 HasPOPCNTD = false; 86 HasCMPB = false; 87 HasLDBRX = false; 88 IsBookE = false; 89 HasOnlyMSYNC = false; 90 IsPPC4xx = false; 91 IsPPC6xx = false; 92 IsE500 = false; 93 DeprecatedMFTB = false; 94 DeprecatedDST = false; 95 HasLazyResolverStubs = false; 96 HasICBT = false; 97 HasInvariantFunctionDescriptors = false; 98 IsQPXStackUnaligned = false; 99 } 100 101 void PPCSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) { 102 // Determine default and user specified characteristics 103 std::string CPUName = CPU; 104 if (CPUName.empty()) { 105 // If cross-compiling with -march=ppc64le without -mcpu 106 if (TargetTriple.getArch() == Triple::ppc64le) 107 CPUName = "ppc64le"; 108 else 109 CPUName = "generic"; 110 } 111 #if (defined(__APPLE__) || defined(__linux__)) && \ 112 (defined(__ppc__) || defined(__powerpc__)) 113 if (CPUName == "generic") 114 CPUName = sys::getHostCPUName(); 115 #endif 116 117 // Initialize scheduling itinerary for the specified CPU. 118 InstrItins = getInstrItineraryForCPU(CPUName); 119 120 // Parse features string. 121 ParseSubtargetFeatures(CPUName, FS); 122 123 // If the user requested use of 64-bit regs, but the cpu selected doesn't 124 // support it, ignore. 125 if (IsPPC64 && has64BitSupport()) 126 Use64BitRegs = true; 127 128 // Set up darwin-specific properties. 129 if (isDarwin()) 130 HasLazyResolverStubs = true; 131 132 // QPX requires a 32-byte aligned stack. Note that we need to do this if 133 // we're compiling for a BG/Q system regardless of whether or not QPX 134 // is enabled because external functions will assume this alignment. 135 IsQPXStackUnaligned = QPXStackUnaligned; 136 StackAlignment = getPlatformStackAlignment(); 137 138 // Determine endianness. 139 // FIXME: Part of the TargetMachine. 140 IsLittleEndian = (TargetTriple.getArch() == Triple::ppc64le); 141 } 142 143 /// hasLazyResolverStub - Return true if accesses to the specified global have 144 /// to go through a dyld lazy resolution stub. This means that an extra load 145 /// is required to get the address of the global. 146 bool PPCSubtarget::hasLazyResolverStub(const GlobalValue *GV) const { 147 // We never have stubs if HasLazyResolverStubs=false or if in static mode. 148 if (!HasLazyResolverStubs || TM.getRelocationModel() == Reloc::Static) 149 return false; 150 bool isDecl = GV->isDeclaration(); 151 if (GV->hasHiddenVisibility() && !isDecl && !GV->hasCommonLinkage()) 152 return false; 153 return GV->hasWeakLinkage() || GV->hasLinkOnceLinkage() || 154 GV->hasCommonLinkage() || isDecl; 155 } 156 157 // Embedded cores need aggressive scheduling (and some others also benefit). 158 static bool needsAggressiveScheduling(unsigned Directive) { 159 switch (Directive) { 160 default: return false; 161 case PPC::DIR_440: 162 case PPC::DIR_A2: 163 case PPC::DIR_E500mc: 164 case PPC::DIR_E5500: 165 case PPC::DIR_PWR7: 166 case PPC::DIR_PWR8: 167 return true; 168 } 169 } 170 171 bool PPCSubtarget::enableMachineScheduler() const { 172 // Enable MI scheduling for the embedded cores. 173 // FIXME: Enable this for all cores (some additional modeling 174 // may be necessary). 175 return needsAggressiveScheduling(DarwinDirective); 176 } 177 178 // This overrides the PostRAScheduler bit in the SchedModel for each CPU. 179 bool PPCSubtarget::enablePostMachineScheduler() const { return true; } 180 181 PPCGenSubtargetInfo::AntiDepBreakMode PPCSubtarget::getAntiDepBreakMode() const { 182 return TargetSubtargetInfo::ANTIDEP_ALL; 183 } 184 185 void PPCSubtarget::getCriticalPathRCs(RegClassVector &CriticalPathRCs) const { 186 CriticalPathRCs.clear(); 187 CriticalPathRCs.push_back(isPPC64() ? 188 &PPC::G8RCRegClass : &PPC::GPRCRegClass); 189 } 190 191 void PPCSubtarget::overrideSchedPolicy(MachineSchedPolicy &Policy, 192 MachineInstr *begin, 193 MachineInstr *end, 194 unsigned NumRegionInstrs) const { 195 if (needsAggressiveScheduling(DarwinDirective)) { 196 Policy.OnlyTopDown = false; 197 Policy.OnlyBottomUp = false; 198 } 199 200 // Spilling is generally expensive on all PPC cores, so always enable 201 // register-pressure tracking. 202 Policy.ShouldTrackPressure = true; 203 } 204 205 bool PPCSubtarget::useAA() const { 206 // Use AA during code generation for the embedded cores. 207 return needsAggressiveScheduling(DarwinDirective); 208 } 209 210 bool PPCSubtarget::enableSubRegLiveness() const { 211 return UseSubRegLiveness; 212 } 213 214 bool PPCSubtarget::isELFv2ABI() const { return TM.isELFv2ABI(); } 215 bool PPCSubtarget::isPPC64() const { return TM.isPPC64(); } 216