1 //===-- PowerPCSubtarget.cpp - PPC Subtarget Information ------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file implements the PPC specific subclass of TargetSubtargetInfo. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "PPCSubtarget.h" 14 #include "PPC.h" 15 #include "PPCRegisterInfo.h" 16 #include "PPCTargetMachine.h" 17 #include "llvm/CodeGen/MachineFunction.h" 18 #include "llvm/CodeGen/MachineScheduler.h" 19 #include "llvm/IR/Attributes.h" 20 #include "llvm/IR/Function.h" 21 #include "llvm/IR/GlobalValue.h" 22 #include "llvm/Support/CommandLine.h" 23 #include "llvm/Support/TargetRegistry.h" 24 #include "llvm/Target/TargetMachine.h" 25 #include <cstdlib> 26 27 using namespace llvm; 28 29 #define DEBUG_TYPE "ppc-subtarget" 30 31 #define GET_SUBTARGETINFO_TARGET_DESC 32 #define GET_SUBTARGETINFO_CTOR 33 #include "PPCGenSubtargetInfo.inc" 34 35 static cl::opt<bool> UseSubRegLiveness("ppc-track-subreg-liveness", 36 cl::desc("Enable subregister liveness tracking for PPC"), cl::Hidden); 37 38 static cl::opt<bool> QPXStackUnaligned("qpx-stack-unaligned", 39 cl::desc("Even when QPX is enabled the stack is not 32-byte aligned"), 40 cl::Hidden); 41 42 static cl::opt<bool> 43 EnableMachinePipeliner("ppc-enable-pipeliner", 44 cl::desc("Enable Machine Pipeliner for PPC"), 45 cl::init(false), cl::Hidden); 46 47 PPCSubtarget &PPCSubtarget::initializeSubtargetDependencies(StringRef CPU, 48 StringRef FS) { 49 initializeEnvironment(); 50 initSubtargetFeatures(CPU, FS); 51 return *this; 52 } 53 54 PPCSubtarget::PPCSubtarget(const Triple &TT, const std::string &CPU, 55 const std::string &FS, const PPCTargetMachine &TM) 56 : PPCGenSubtargetInfo(TT, CPU, FS), TargetTriple(TT), 57 IsPPC64(TargetTriple.getArch() == Triple::ppc64 || 58 TargetTriple.getArch() == Triple::ppc64le), 59 TM(TM), FrameLowering(initializeSubtargetDependencies(CPU, FS)), 60 InstrInfo(*this), TLInfo(TM, *this) {} 61 62 void PPCSubtarget::initializeEnvironment() { 63 StackAlignment = Align(16); 64 CPUDirective = PPC::DIR_NONE; 65 HasMFOCRF = false; 66 Has64BitSupport = false; 67 Use64BitRegs = false; 68 UseCRBits = false; 69 HasHardFloat = false; 70 HasAltivec = false; 71 HasSPE = false; 72 HasFPU = false; 73 HasQPX = false; 74 HasVSX = false; 75 NeedsTwoConstNR = false; 76 HasP8Vector = false; 77 HasP8Altivec = false; 78 HasP8Crypto = false; 79 HasP9Vector = false; 80 HasP9Altivec = false; 81 HasPrefixInstrs = false; 82 HasPCRelativeMemops = false; 83 HasFCPSGN = false; 84 HasFSQRT = false; 85 HasFRE = false; 86 HasFRES = false; 87 HasFRSQRTE = false; 88 HasFRSQRTES = false; 89 HasRecipPrec = false; 90 HasSTFIWX = false; 91 HasLFIWAX = false; 92 HasFPRND = false; 93 HasFPCVT = false; 94 HasISEL = false; 95 HasBPERMD = false; 96 HasExtDiv = false; 97 HasCMPB = false; 98 HasLDBRX = false; 99 IsBookE = false; 100 HasOnlyMSYNC = false; 101 IsPPC4xx = false; 102 IsPPC6xx = false; 103 IsE500 = false; 104 FeatureMFTB = false; 105 AllowsUnalignedFPAccess = false; 106 DeprecatedDST = false; 107 HasICBT = false; 108 HasInvariantFunctionDescriptors = false; 109 HasPartwordAtomics = false; 110 HasDirectMove = false; 111 IsQPXStackUnaligned = false; 112 HasHTM = false; 113 HasFloat128 = false; 114 HasFusion = false; 115 HasAddiLoadFusion = false; 116 HasAddisLoadFusion = false; 117 IsISA3_0 = false; 118 IsISA3_1 = false; 119 UseLongCalls = false; 120 SecurePlt = false; 121 VectorsUseTwoUnits = false; 122 UsePPCPreRASchedStrategy = false; 123 UsePPCPostRASchedStrategy = false; 124 PredictableSelectIsExpensive = false; 125 126 HasPOPCNTD = POPCNTD_Unavailable; 127 } 128 129 void PPCSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) { 130 // Determine default and user specified characteristics 131 std::string CPUName = std::string(CPU); 132 if (CPUName.empty() || CPU == "generic") { 133 // If cross-compiling with -march=ppc64le without -mcpu 134 if (TargetTriple.getArch() == Triple::ppc64le) 135 CPUName = "ppc64le"; 136 else if (TargetTriple.getSubArch() == Triple::PPCSubArch_spe) 137 CPUName = "e500"; 138 else 139 CPUName = "generic"; 140 } 141 142 // Initialize scheduling itinerary for the specified CPU. 143 InstrItins = getInstrItineraryForCPU(CPUName); 144 145 // Parse features string. 146 ParseSubtargetFeatures(CPUName, FS); 147 148 // If the user requested use of 64-bit regs, but the cpu selected doesn't 149 // support it, ignore. 150 if (IsPPC64 && has64BitSupport()) 151 Use64BitRegs = true; 152 153 if ((TargetTriple.isOSFreeBSD() && TargetTriple.getOSMajorVersion() >= 13) || 154 TargetTriple.isOSNetBSD() || TargetTriple.isOSOpenBSD() || 155 TargetTriple.isMusl()) 156 SecurePlt = true; 157 158 if (HasSPE && IsPPC64) 159 report_fatal_error( "SPE is only supported for 32-bit targets.\n", false); 160 if (HasSPE && (HasAltivec || HasQPX || HasVSX || HasFPU)) 161 report_fatal_error( 162 "SPE and traditional floating point cannot both be enabled.\n", false); 163 164 // If not SPE, set standard FPU 165 if (!HasSPE) 166 HasFPU = true; 167 168 // QPX requires a 32-byte aligned stack. Note that we need to do this if 169 // we're compiling for a BG/Q system regardless of whether or not QPX 170 // is enabled because external functions will assume this alignment. 171 IsQPXStackUnaligned = QPXStackUnaligned; 172 StackAlignment = getPlatformStackAlignment(); 173 174 // Determine endianness. 175 // FIXME: Part of the TargetMachine. 176 IsLittleEndian = (TargetTriple.getArch() == Triple::ppc64le); 177 } 178 179 bool PPCSubtarget::enableMachineScheduler() const { return true; } 180 181 bool PPCSubtarget::enableMachinePipeliner() const { 182 return (CPUDirective == PPC::DIR_PWR9) && EnableMachinePipeliner; 183 } 184 185 bool PPCSubtarget::useDFAforSMS() const { return false; } 186 187 // This overrides the PostRAScheduler bit in the SchedModel for each CPU. 188 bool PPCSubtarget::enablePostRAScheduler() const { return true; } 189 190 PPCGenSubtargetInfo::AntiDepBreakMode PPCSubtarget::getAntiDepBreakMode() const { 191 return TargetSubtargetInfo::ANTIDEP_ALL; 192 } 193 194 void PPCSubtarget::getCriticalPathRCs(RegClassVector &CriticalPathRCs) const { 195 CriticalPathRCs.clear(); 196 CriticalPathRCs.push_back(isPPC64() ? 197 &PPC::G8RCRegClass : &PPC::GPRCRegClass); 198 } 199 200 void PPCSubtarget::overrideSchedPolicy(MachineSchedPolicy &Policy, 201 unsigned NumRegionInstrs) const { 202 // The GenericScheduler that we use defaults to scheduling bottom up only. 203 // We want to schedule from both the top and the bottom and so we set 204 // OnlyBottomUp to false. 205 // We want to do bi-directional scheduling since it provides a more balanced 206 // schedule leading to better performance. 207 Policy.OnlyBottomUp = false; 208 // Spilling is generally expensive on all PPC cores, so always enable 209 // register-pressure tracking. 210 Policy.ShouldTrackPressure = true; 211 } 212 213 bool PPCSubtarget::useAA() const { 214 return true; 215 } 216 217 bool PPCSubtarget::enableSubRegLiveness() const { 218 return UseSubRegLiveness; 219 } 220 221 bool PPCSubtarget::isGVIndirectSymbol(const GlobalValue *GV) const { 222 // Large code model always uses the TOC even for local symbols. 223 if (TM.getCodeModel() == CodeModel::Large) 224 return true; 225 if (TM.shouldAssumeDSOLocal(*GV->getParent(), GV)) 226 return false; 227 return true; 228 } 229 230 bool PPCSubtarget::isELFv2ABI() const { return TM.isELFv2ABI(); } 231 bool PPCSubtarget::isPPC64() const { return TM.isPPC64(); } 232 233 bool PPCSubtarget::isUsingPCRelativeCalls() const { 234 return isPPC64() && hasPCRelativeMemops() && isELFv2ABI() && 235 CodeModel::Medium == getTargetMachine().getCodeModel(); 236 } 237