1 //===-- PowerPCSubtarget.cpp - PPC Subtarget Information ------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file implements the PPC specific subclass of TargetSubtargetInfo. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "PPCSubtarget.h" 14 #include "PPC.h" 15 #include "PPCRegisterInfo.h" 16 #include "PPCTargetMachine.h" 17 #include "llvm/CodeGen/MachineFunction.h" 18 #include "llvm/CodeGen/MachineScheduler.h" 19 #include "llvm/IR/Attributes.h" 20 #include "llvm/IR/Function.h" 21 #include "llvm/IR/GlobalValue.h" 22 #include "llvm/Support/CommandLine.h" 23 #include "llvm/Support/TargetRegistry.h" 24 #include "llvm/Target/TargetMachine.h" 25 #include <cstdlib> 26 27 using namespace llvm; 28 29 #define DEBUG_TYPE "ppc-subtarget" 30 31 #define GET_SUBTARGETINFO_TARGET_DESC 32 #define GET_SUBTARGETINFO_CTOR 33 #include "PPCGenSubtargetInfo.inc" 34 35 static cl::opt<bool> UseSubRegLiveness("ppc-track-subreg-liveness", 36 cl::desc("Enable subregister liveness tracking for PPC"), cl::Hidden); 37 38 static cl::opt<bool> 39 EnableMachinePipeliner("ppc-enable-pipeliner", 40 cl::desc("Enable Machine Pipeliner for PPC"), 41 cl::init(false), cl::Hidden); 42 43 PPCSubtarget &PPCSubtarget::initializeSubtargetDependencies(StringRef CPU, 44 StringRef FS) { 45 initializeEnvironment(); 46 initSubtargetFeatures(CPU, FS); 47 return *this; 48 } 49 50 PPCSubtarget::PPCSubtarget(const Triple &TT, const std::string &CPU, 51 const std::string &FS, const PPCTargetMachine &TM) 52 : PPCGenSubtargetInfo(TT, CPU, FS), TargetTriple(TT), 53 IsPPC64(TargetTriple.getArch() == Triple::ppc64 || 54 TargetTriple.getArch() == Triple::ppc64le), 55 TM(TM), FrameLowering(initializeSubtargetDependencies(CPU, FS)), 56 InstrInfo(*this), TLInfo(TM, *this) {} 57 58 void PPCSubtarget::initializeEnvironment() { 59 StackAlignment = Align(16); 60 CPUDirective = PPC::DIR_NONE; 61 HasMFOCRF = false; 62 Has64BitSupport = false; 63 Use64BitRegs = false; 64 UseCRBits = false; 65 HasHardFloat = false; 66 HasAltivec = false; 67 HasSPE = false; 68 HasFPU = false; 69 HasVSX = false; 70 NeedsTwoConstNR = false; 71 HasP8Vector = false; 72 HasP8Altivec = false; 73 HasP8Crypto = false; 74 HasP9Vector = false; 75 HasP9Altivec = false; 76 HasP10Vector = false; 77 HasPrefixInstrs = false; 78 HasPCRelativeMemops = false; 79 HasFCPSGN = false; 80 HasFSQRT = false; 81 HasFRE = false; 82 HasFRES = false; 83 HasFRSQRTE = false; 84 HasFRSQRTES = false; 85 HasRecipPrec = false; 86 HasSTFIWX = false; 87 HasLFIWAX = false; 88 HasFPRND = false; 89 HasFPCVT = false; 90 HasISEL = false; 91 HasBPERMD = false; 92 HasExtDiv = false; 93 HasCMPB = false; 94 HasLDBRX = false; 95 IsBookE = false; 96 HasOnlyMSYNC = false; 97 IsPPC4xx = false; 98 IsPPC6xx = false; 99 IsE500 = false; 100 FeatureMFTB = false; 101 AllowsUnalignedFPAccess = false; 102 DeprecatedDST = false; 103 HasICBT = false; 104 HasInvariantFunctionDescriptors = false; 105 HasPartwordAtomics = false; 106 HasDirectMove = false; 107 HasHTM = false; 108 HasFloat128 = false; 109 HasFusion = false; 110 HasAddiLoadFusion = false; 111 HasAddisLoadFusion = false; 112 IsISA3_0 = false; 113 IsISA3_1 = false; 114 UseLongCalls = false; 115 SecurePlt = false; 116 VectorsUseTwoUnits = false; 117 UsePPCPreRASchedStrategy = false; 118 UsePPCPostRASchedStrategy = false; 119 PredictableSelectIsExpensive = false; 120 121 HasPOPCNTD = POPCNTD_Unavailable; 122 } 123 124 void PPCSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) { 125 // Determine default and user specified characteristics 126 std::string CPUName = std::string(CPU); 127 if (CPUName.empty() || CPU == "generic") { 128 // If cross-compiling with -march=ppc64le without -mcpu 129 if (TargetTriple.getArch() == Triple::ppc64le) 130 CPUName = "ppc64le"; 131 else if (TargetTriple.getSubArch() == Triple::PPCSubArch_spe) 132 CPUName = "e500"; 133 else 134 CPUName = "generic"; 135 } 136 137 // Initialize scheduling itinerary for the specified CPU. 138 InstrItins = getInstrItineraryForCPU(CPUName); 139 140 // Parse features string. 141 ParseSubtargetFeatures(CPUName, FS); 142 143 // If the user requested use of 64-bit regs, but the cpu selected doesn't 144 // support it, ignore. 145 if (IsPPC64 && has64BitSupport()) 146 Use64BitRegs = true; 147 148 if ((TargetTriple.isOSFreeBSD() && TargetTriple.getOSMajorVersion() >= 13) || 149 TargetTriple.isOSNetBSD() || TargetTriple.isOSOpenBSD() || 150 TargetTriple.isMusl()) 151 SecurePlt = true; 152 153 if (HasSPE && IsPPC64) 154 report_fatal_error( "SPE is only supported for 32-bit targets.\n", false); 155 if (HasSPE && (HasAltivec || HasVSX || HasFPU)) 156 report_fatal_error( 157 "SPE and traditional floating point cannot both be enabled.\n", false); 158 159 // If not SPE, set standard FPU 160 if (!HasSPE) 161 HasFPU = true; 162 163 StackAlignment = getPlatformStackAlignment(); 164 165 // Determine endianness. 166 // FIXME: Part of the TargetMachine. 167 IsLittleEndian = (TargetTriple.getArch() == Triple::ppc64le); 168 } 169 170 bool PPCSubtarget::enableMachineScheduler() const { return true; } 171 172 bool PPCSubtarget::enableMachinePipeliner() const { 173 return getSchedModel().hasInstrSchedModel() && EnableMachinePipeliner; 174 } 175 176 bool PPCSubtarget::useDFAforSMS() const { return false; } 177 178 // This overrides the PostRAScheduler bit in the SchedModel for each CPU. 179 bool PPCSubtarget::enablePostRAScheduler() const { return true; } 180 181 PPCGenSubtargetInfo::AntiDepBreakMode PPCSubtarget::getAntiDepBreakMode() const { 182 return TargetSubtargetInfo::ANTIDEP_ALL; 183 } 184 185 void PPCSubtarget::getCriticalPathRCs(RegClassVector &CriticalPathRCs) const { 186 CriticalPathRCs.clear(); 187 CriticalPathRCs.push_back(isPPC64() ? 188 &PPC::G8RCRegClass : &PPC::GPRCRegClass); 189 } 190 191 void PPCSubtarget::overrideSchedPolicy(MachineSchedPolicy &Policy, 192 unsigned NumRegionInstrs) const { 193 // The GenericScheduler that we use defaults to scheduling bottom up only. 194 // We want to schedule from both the top and the bottom and so we set 195 // OnlyBottomUp to false. 196 // We want to do bi-directional scheduling since it provides a more balanced 197 // schedule leading to better performance. 198 Policy.OnlyBottomUp = false; 199 // Spilling is generally expensive on all PPC cores, so always enable 200 // register-pressure tracking. 201 Policy.ShouldTrackPressure = true; 202 } 203 204 bool PPCSubtarget::useAA() const { 205 return true; 206 } 207 208 bool PPCSubtarget::enableSubRegLiveness() const { 209 return UseSubRegLiveness; 210 } 211 212 bool PPCSubtarget::isGVIndirectSymbol(const GlobalValue *GV) const { 213 // Large code model always uses the TOC even for local symbols. 214 if (TM.getCodeModel() == CodeModel::Large) 215 return true; 216 if (TM.shouldAssumeDSOLocal(*GV->getParent(), GV)) 217 return false; 218 return true; 219 } 220 221 bool PPCSubtarget::isELFv2ABI() const { return TM.isELFv2ABI(); } 222 bool PPCSubtarget::isPPC64() const { return TM.isPPC64(); } 223 224 bool PPCSubtarget::isUsingPCRelativeCalls() const { 225 return isPPC64() && hasPCRelativeMemops() && isELFv2ABI() && 226 CodeModel::Medium == getTargetMachine().getCodeModel(); 227 } 228