1 //===-- PowerPCSubtarget.cpp - PPC Subtarget Information ------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements the PPC specific subclass of TargetSubtargetInfo. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "PPCSubtarget.h" 15 #include "PPC.h" 16 #include "PPCRegisterInfo.h" 17 #include "PPCTargetMachine.h" 18 #include "llvm/CodeGen/MachineFunction.h" 19 #include "llvm/CodeGen/MachineScheduler.h" 20 #include "llvm/IR/Attributes.h" 21 #include "llvm/IR/Function.h" 22 #include "llvm/IR/GlobalValue.h" 23 #include "llvm/Support/CommandLine.h" 24 #include "llvm/Support/Host.h" 25 #include "llvm/Support/TargetRegistry.h" 26 #include "llvm/Target/TargetMachine.h" 27 #include <cstdlib> 28 29 using namespace llvm; 30 31 #define DEBUG_TYPE "ppc-subtarget" 32 33 #define GET_SUBTARGETINFO_TARGET_DESC 34 #define GET_SUBTARGETINFO_CTOR 35 #include "PPCGenSubtargetInfo.inc" 36 37 static cl::opt<bool> UseSubRegLiveness("ppc-track-subreg-liveness", 38 cl::desc("Enable subregister liveness tracking for PPC"), cl::Hidden); 39 40 PPCSubtarget &PPCSubtarget::initializeSubtargetDependencies(StringRef CPU, 41 StringRef FS) { 42 initializeEnvironment(); 43 initSubtargetFeatures(CPU, FS); 44 return *this; 45 } 46 47 PPCSubtarget::PPCSubtarget(const std::string &TT, const std::string &CPU, 48 const std::string &FS, const PPCTargetMachine &TM) 49 : PPCGenSubtargetInfo(TT, CPU, FS), TargetTriple(TT), 50 IsPPC64(TargetTriple.getArch() == Triple::ppc64 || 51 TargetTriple.getArch() == Triple::ppc64le), 52 TargetABI(PPC_ABI_UNKNOWN), 53 FrameLowering(initializeSubtargetDependencies(CPU, FS)), InstrInfo(*this), 54 TLInfo(TM), TSInfo(TM.getDataLayout()) {} 55 56 void PPCSubtarget::initializeEnvironment() { 57 StackAlignment = 16; 58 DarwinDirective = PPC::DIR_NONE; 59 HasMFOCRF = false; 60 Has64BitSupport = false; 61 Use64BitRegs = false; 62 UseCRBits = false; 63 HasAltivec = false; 64 HasSPE = false; 65 HasQPX = false; 66 HasVSX = false; 67 HasP8Vector = false; 68 HasFCPSGN = false; 69 HasFSQRT = false; 70 HasFRE = false; 71 HasFRES = false; 72 HasFRSQRTE = false; 73 HasFRSQRTES = false; 74 HasRecipPrec = false; 75 HasSTFIWX = false; 76 HasLFIWAX = false; 77 HasFPRND = false; 78 HasFPCVT = false; 79 HasISEL = false; 80 HasPOPCNTD = false; 81 HasCMPB = false; 82 HasLDBRX = false; 83 IsBookE = false; 84 HasOnlyMSYNC = false; 85 IsPPC4xx = false; 86 IsPPC6xx = false; 87 IsE500 = false; 88 DeprecatedMFTB = false; 89 DeprecatedDST = false; 90 HasLazyResolverStubs = false; 91 HasICBT = false; 92 HasInvariantFunctionDescriptors = false; 93 } 94 95 void PPCSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) { 96 // Determine default and user specified characteristics 97 std::string CPUName = CPU; 98 if (CPUName.empty()) 99 CPUName = "generic"; 100 #if (defined(__APPLE__) || defined(__linux__)) && \ 101 (defined(__ppc__) || defined(__powerpc__)) 102 if (CPUName == "generic") 103 CPUName = sys::getHostCPUName(); 104 #endif 105 106 // Initialize scheduling itinerary for the specified CPU. 107 InstrItins = getInstrItineraryForCPU(CPUName); 108 109 // Parse features string. 110 ParseSubtargetFeatures(CPUName, FS); 111 112 // If the user requested use of 64-bit regs, but the cpu selected doesn't 113 // support it, ignore. 114 if (IsPPC64 && has64BitSupport()) 115 Use64BitRegs = true; 116 117 // Set up darwin-specific properties. 118 if (isDarwin()) 119 HasLazyResolverStubs = true; 120 121 // QPX requires a 32-byte aligned stack. Note that we need to do this if 122 // we're compiling for a BG/Q system regardless of whether or not QPX 123 // is enabled because external functions will assume this alignment. 124 if (hasQPX() || isBGQ()) 125 StackAlignment = 32; 126 127 // Determine endianness. 128 IsLittleEndian = (TargetTriple.getArch() == Triple::ppc64le); 129 130 // Determine default ABI. 131 if (TargetABI == PPC_ABI_UNKNOWN) { 132 if (!isDarwin() && IsPPC64) { 133 if (IsLittleEndian) 134 TargetABI = PPC_ABI_ELFv2; 135 else 136 TargetABI = PPC_ABI_ELFv1; 137 } 138 } 139 } 140 141 /// hasLazyResolverStub - Return true if accesses to the specified global have 142 /// to go through a dyld lazy resolution stub. This means that an extra load 143 /// is required to get the address of the global. 144 bool PPCSubtarget::hasLazyResolverStub(const GlobalValue *GV, 145 const TargetMachine &TM) const { 146 // We never have stubs if HasLazyResolverStubs=false or if in static mode. 147 if (!HasLazyResolverStubs || TM.getRelocationModel() == Reloc::Static) 148 return false; 149 bool isDecl = GV->isDeclaration(); 150 if (GV->hasHiddenVisibility() && !isDecl && !GV->hasCommonLinkage()) 151 return false; 152 return GV->hasWeakLinkage() || GV->hasLinkOnceLinkage() || 153 GV->hasCommonLinkage() || isDecl; 154 } 155 156 // Embedded cores need aggressive scheduling (and some others also benefit). 157 static bool needsAggressiveScheduling(unsigned Directive) { 158 switch (Directive) { 159 default: return false; 160 case PPC::DIR_440: 161 case PPC::DIR_A2: 162 case PPC::DIR_E500mc: 163 case PPC::DIR_E5500: 164 case PPC::DIR_PWR7: 165 case PPC::DIR_PWR8: 166 return true; 167 } 168 } 169 170 bool PPCSubtarget::enableMachineScheduler() const { 171 // Enable MI scheduling for the embedded cores. 172 // FIXME: Enable this for all cores (some additional modeling 173 // may be necessary). 174 return needsAggressiveScheduling(DarwinDirective); 175 } 176 177 // This overrides the PostRAScheduler bit in the SchedModel for each CPU. 178 bool PPCSubtarget::enablePostMachineScheduler() const { return true; } 179 180 PPCGenSubtargetInfo::AntiDepBreakMode PPCSubtarget::getAntiDepBreakMode() const { 181 return TargetSubtargetInfo::ANTIDEP_ALL; 182 } 183 184 void PPCSubtarget::getCriticalPathRCs(RegClassVector &CriticalPathRCs) const { 185 CriticalPathRCs.clear(); 186 CriticalPathRCs.push_back(isPPC64() ? 187 &PPC::G8RCRegClass : &PPC::GPRCRegClass); 188 } 189 190 void PPCSubtarget::overrideSchedPolicy(MachineSchedPolicy &Policy, 191 MachineInstr *begin, 192 MachineInstr *end, 193 unsigned NumRegionInstrs) const { 194 if (needsAggressiveScheduling(DarwinDirective)) { 195 Policy.OnlyTopDown = false; 196 Policy.OnlyBottomUp = false; 197 } 198 199 // Spilling is generally expensive on all PPC cores, so always enable 200 // register-pressure tracking. 201 Policy.ShouldTrackPressure = true; 202 } 203 204 bool PPCSubtarget::useAA() const { 205 // Use AA during code generation for the embedded cores. 206 return needsAggressiveScheduling(DarwinDirective); 207 } 208 209 bool PPCSubtarget::enableSubRegLiveness() const { 210 return UseSubRegLiveness; 211 } 212 213