1 //===-- PowerPCSubtarget.cpp - PPC Subtarget Information ------------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the PPC specific subclass of TargetSubtargetInfo.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "PPCSubtarget.h"
15 #include "PPCRegisterInfo.h"
16 #include "PPC.h"
17 #include "llvm/GlobalValue.h"
18 #include "llvm/Target/TargetMachine.h"
19 #include "llvm/Support/Host.h"
20 #include "llvm/Support/TargetRegistry.h"
21 #include <cstdlib>
22 
23 #define GET_SUBTARGETINFO_TARGET_DESC
24 #define GET_SUBTARGETINFO_CTOR
25 #include "PPCGenSubtargetInfo.inc"
26 
27 using namespace llvm;
28 
29 PPCSubtarget::PPCSubtarget(const std::string &TT, const std::string &CPU,
30                            const std::string &FS, bool is64Bit)
31   : PPCGenSubtargetInfo(TT, CPU, FS)
32   , StackAlignment(16)
33   , DarwinDirective(PPC::DIR_NONE)
34   , HasMFOCRF(false)
35   , Has64BitSupport(false)
36   , Use64BitRegs(false)
37   , IsPPC64(is64Bit)
38   , HasAltivec(false)
39   , HasFSQRT(false)
40   , HasSTFIWX(false)
41   , IsBookE(false)
42   , HasLazyResolverStubs(false)
43   , IsJITCodeModel(false)
44   , TargetTriple(TT) {
45 
46   // Determine default and user specified characteristics
47   std::string CPUName = CPU;
48   if (CPUName.empty())
49     CPUName = "generic";
50 #if (defined(__APPLE__) || defined(__linux__)) && \
51     (defined(__ppc__) || defined(__powerpc__))
52   if (CPUName == "generic")
53     CPUName = sys::getHostCPUName();
54 #endif
55 
56   // Parse features string.
57   ParseSubtargetFeatures(CPUName, FS);
58 
59   // Initialize scheduling itinerary for the specified CPU.
60   InstrItins = getInstrItineraryForCPU(CPUName);
61 
62   // If we are generating code for ppc64, verify that options make sense.
63   if (is64Bit) {
64     Has64BitSupport = true;
65     // Silently force 64-bit register use on ppc64.
66     Use64BitRegs = true;
67   }
68 
69   // If the user requested use of 64-bit regs, but the cpu selected doesn't
70   // support it, ignore.
71   if (use64BitRegs() && !has64BitSupport())
72     Use64BitRegs = false;
73 
74   // Set up darwin-specific properties.
75   if (isDarwin())
76     HasLazyResolverStubs = true;
77 }
78 
79 /// SetJITMode - This is called to inform the subtarget info that we are
80 /// producing code for the JIT.
81 void PPCSubtarget::SetJITMode() {
82   // JIT mode doesn't want lazy resolver stubs, it knows exactly where
83   // everything is.  This matters for PPC64, which codegens in PIC mode without
84   // stubs.
85   HasLazyResolverStubs = false;
86 
87   // Calls to external functions need to use indirect calls
88   IsJITCodeModel = true;
89 }
90 
91 
92 /// hasLazyResolverStub - Return true if accesses to the specified global have
93 /// to go through a dyld lazy resolution stub.  This means that an extra load
94 /// is required to get the address of the global.
95 bool PPCSubtarget::hasLazyResolverStub(const GlobalValue *GV,
96                                        const TargetMachine &TM) const {
97   // We never have stubs if HasLazyResolverStubs=false or if in static mode.
98   if (!HasLazyResolverStubs || TM.getRelocationModel() == Reloc::Static)
99     return false;
100   // If symbol visibility is hidden, the extra load is not needed if
101   // the symbol is definitely defined in the current translation unit.
102   bool isDecl = GV->isDeclaration() && !GV->isMaterializable();
103   if (GV->hasHiddenVisibility() && !isDecl && !GV->hasCommonLinkage())
104     return false;
105   return GV->hasWeakLinkage() || GV->hasLinkOnceLinkage() ||
106          GV->hasCommonLinkage() || isDecl;
107 }
108 
109 bool PPCSubtarget::enablePostRAScheduler(
110            CodeGenOpt::Level OptLevel,
111            TargetSubtargetInfo::AntiDepBreakMode& Mode,
112            RegClassVector& CriticalPathRCs) const {
113   // FIXME: It would be best to use TargetSubtargetInfo::ANTIDEP_ALL here,
114   // but we can't because we can't reassign the cr registers. There is a
115   // dependence between the cr register and the RLWINM instruction used
116   // to extract its value which the anti-dependency breaker can't currently
117   // see. Maybe we should make a late-expanded pseudo to encode this dependency.
118   // (the relevant code is in PPCDAGToDAGISel::SelectSETCC)
119 
120   Mode = TargetSubtargetInfo::ANTIDEP_CRITICAL;
121 
122   CriticalPathRCs.clear();
123 
124   if (isPPC64())
125     CriticalPathRCs.push_back(&PPC::G8RCRegClass);
126   else
127     CriticalPathRCs.push_back(&PPC::GPRCRegClass);
128 
129   CriticalPathRCs.push_back(&PPC::F8RCRegClass);
130   CriticalPathRCs.push_back(&PPC::VRRCRegClass);
131 
132   return OptLevel >= CodeGenOpt::Default;
133 }
134 
135