1 //===-- PowerPCSubtarget.cpp - PPC Subtarget Information ------------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the PPC specific subclass of TargetSubtargetInfo.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "PPCSubtarget.h"
15 #include "PPC.h"
16 #include "PPCRegisterInfo.h"
17 #include "PPCTargetMachine.h"
18 #include "llvm/CodeGen/Analysis.h"
19 #include "llvm/CodeGen/MachineFunction.h"
20 #include "llvm/CodeGen/MachineScheduler.h"
21 #include "llvm/IR/Attributes.h"
22 #include "llvm/IR/Function.h"
23 #include "llvm/IR/GlobalValue.h"
24 #include "llvm/Support/CommandLine.h"
25 #include "llvm/Support/TargetRegistry.h"
26 #include "llvm/Target/TargetMachine.h"
27 #include <cstdlib>
28 
29 using namespace llvm;
30 
31 #define DEBUG_TYPE "ppc-subtarget"
32 
33 #define GET_SUBTARGETINFO_TARGET_DESC
34 #define GET_SUBTARGETINFO_CTOR
35 #include "PPCGenSubtargetInfo.inc"
36 
37 static cl::opt<bool> UseSubRegLiveness("ppc-track-subreg-liveness",
38 cl::desc("Enable subregister liveness tracking for PPC"), cl::Hidden);
39 
40 static cl::opt<bool> QPXStackUnaligned("qpx-stack-unaligned",
41   cl::desc("Even when QPX is enabled the stack is not 32-byte aligned"),
42   cl::Hidden);
43 
44 PPCSubtarget &PPCSubtarget::initializeSubtargetDependencies(StringRef CPU,
45                                                             StringRef FS) {
46   initializeEnvironment();
47   initSubtargetFeatures(CPU, FS);
48   return *this;
49 }
50 
51 PPCSubtarget::PPCSubtarget(const Triple &TT, const std::string &CPU,
52                            const std::string &FS, const PPCTargetMachine &TM)
53     : PPCGenSubtargetInfo(TT, CPU, FS), TargetTriple(TT),
54       IsPPC64(TargetTriple.getArch() == Triple::ppc64 ||
55               TargetTriple.getArch() == Triple::ppc64le),
56       TM(TM), FrameLowering(initializeSubtargetDependencies(CPU, FS)),
57       InstrInfo(*this), TLInfo(TM, *this) {}
58 
59 void PPCSubtarget::initializeEnvironment() {
60   StackAlignment = 16;
61   DarwinDirective = PPC::DIR_NONE;
62   HasMFOCRF = false;
63   Has64BitSupport = false;
64   Use64BitRegs = false;
65   UseCRBits = false;
66   UseSoftFloat = false;
67   HasAltivec = false;
68   HasSPE = false;
69   HasQPX = false;
70   HasVSX = false;
71   HasP8Vector = false;
72   HasP8Altivec = false;
73   HasP8Crypto = false;
74   HasP9Vector = false;
75   HasP9Altivec = false;
76   HasFCPSGN = false;
77   HasFSQRT = false;
78   HasFRE = false;
79   HasFRES = false;
80   HasFRSQRTE = false;
81   HasFRSQRTES = false;
82   HasRecipPrec = false;
83   HasSTFIWX = false;
84   HasLFIWAX = false;
85   HasFPRND = false;
86   HasFPCVT = false;
87   HasISEL = false;
88   HasBPERMD = false;
89   HasExtDiv = false;
90   HasCMPB = false;
91   HasLDBRX = false;
92   IsBookE = false;
93   HasOnlyMSYNC = false;
94   IsPPC4xx = false;
95   IsPPC6xx = false;
96   IsE500 = false;
97   FeatureMFTB = false;
98   DeprecatedDST = false;
99   HasLazyResolverStubs = false;
100   HasICBT = false;
101   HasInvariantFunctionDescriptors = false;
102   HasPartwordAtomics = false;
103   HasDirectMove = false;
104   IsQPXStackUnaligned = false;
105   HasHTM = false;
106   HasFusion = false;
107   HasFloat128 = false;
108   IsISA3_0 = false;
109 
110   HasPOPCNTD = POPCNTD_Unavailable;
111 }
112 
113 void PPCSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) {
114   // Determine default and user specified characteristics
115   std::string CPUName = CPU;
116   if (CPUName.empty() || CPU == "generic") {
117     // If cross-compiling with -march=ppc64le without -mcpu
118     if (TargetTriple.getArch() == Triple::ppc64le)
119       CPUName = "ppc64le";
120     else
121       CPUName = "generic";
122   }
123 
124   // Initialize scheduling itinerary for the specified CPU.
125   InstrItins = getInstrItineraryForCPU(CPUName);
126 
127   // Parse features string.
128   ParseSubtargetFeatures(CPUName, FS);
129 
130   // If the user requested use of 64-bit regs, but the cpu selected doesn't
131   // support it, ignore.
132   if (IsPPC64 && has64BitSupport())
133     Use64BitRegs = true;
134 
135   // Set up darwin-specific properties.
136   if (isDarwin())
137     HasLazyResolverStubs = true;
138 
139   // QPX requires a 32-byte aligned stack. Note that we need to do this if
140   // we're compiling for a BG/Q system regardless of whether or not QPX
141   // is enabled because external functions will assume this alignment.
142   IsQPXStackUnaligned = QPXStackUnaligned;
143   StackAlignment = getPlatformStackAlignment();
144 
145   // Determine endianness.
146   // FIXME: Part of the TargetMachine.
147   IsLittleEndian = (TargetTriple.getArch() == Triple::ppc64le);
148 }
149 
150 /// Return true if accesses to the specified global have to go through a dyld
151 /// lazy resolution stub.  This means that an extra load is required to get the
152 /// address of the global.
153 bool PPCSubtarget::hasLazyResolverStub(const GlobalValue *GV) const {
154   if (!HasLazyResolverStubs)
155     return false;
156   if (!TM.shouldAssumeDSOLocal(*GV->getParent(), GV))
157     return true;
158   // 32 bit macho has no relocation for a-b if a is undefined, even if b is in
159   // the section that is being relocated. This means we have to use o load even
160   // for GVs that are known to be local to the dso.
161   if (GV->isDeclarationForLinker() || GV->hasCommonLinkage())
162     return true;
163   return false;
164 }
165 
166 // Embedded cores need aggressive scheduling (and some others also benefit).
167 static bool needsAggressiveScheduling(unsigned Directive) {
168   switch (Directive) {
169   default: return false;
170   case PPC::DIR_440:
171   case PPC::DIR_A2:
172   case PPC::DIR_E500mc:
173   case PPC::DIR_E5500:
174   case PPC::DIR_PWR7:
175   case PPC::DIR_PWR8:
176   // FIXME: Same as P8 until POWER9 scheduling info is available
177   case PPC::DIR_PWR9:
178     return true;
179   }
180 }
181 
182 bool PPCSubtarget::enableMachineScheduler() const {
183   // Enable MI scheduling for the embedded cores.
184   // FIXME: Enable this for all cores (some additional modeling
185   // may be necessary).
186   return needsAggressiveScheduling(DarwinDirective);
187 }
188 
189 // This overrides the PostRAScheduler bit in the SchedModel for each CPU.
190 bool PPCSubtarget::enablePostRAScheduler() const { return true; }
191 
192 PPCGenSubtargetInfo::AntiDepBreakMode PPCSubtarget::getAntiDepBreakMode() const {
193   return TargetSubtargetInfo::ANTIDEP_ALL;
194 }
195 
196 void PPCSubtarget::getCriticalPathRCs(RegClassVector &CriticalPathRCs) const {
197   CriticalPathRCs.clear();
198   CriticalPathRCs.push_back(isPPC64() ?
199                             &PPC::G8RCRegClass : &PPC::GPRCRegClass);
200 }
201 
202 void PPCSubtarget::overrideSchedPolicy(MachineSchedPolicy &Policy,
203                                        MachineInstr *begin,
204                                        MachineInstr *end,
205                                        unsigned NumRegionInstrs) const {
206   if (needsAggressiveScheduling(DarwinDirective)) {
207     Policy.OnlyTopDown = false;
208     Policy.OnlyBottomUp = false;
209   }
210 
211   // Spilling is generally expensive on all PPC cores, so always enable
212   // register-pressure tracking.
213   Policy.ShouldTrackPressure = true;
214 }
215 
216 bool PPCSubtarget::useAA() const {
217   // Use AA during code generation for the embedded cores.
218   return needsAggressiveScheduling(DarwinDirective);
219 }
220 
221 bool PPCSubtarget::enableSubRegLiveness() const {
222   return UseSubRegLiveness;
223 }
224 
225 unsigned char PPCSubtarget::classifyGlobalReference(
226     const GlobalValue *GV) const {
227   // Note that currently we don't generate non-pic references.
228   // If a caller wants that, this will have to be updated.
229 
230   // Large code model always uses the TOC even for local symbols.
231   if (TM.getCodeModel() == CodeModel::Large)
232     return PPCII::MO_PIC_FLAG | PPCII::MO_NLP_FLAG;
233 
234   unsigned char flags = PPCII::MO_PIC_FLAG;
235 
236   // Only if the relocation mode is PIC do we have to worry about
237   // interposition. In all other cases we can use a slightly looser standard to
238   // decide how to access the symbol.
239   if (TM.getRelocationModel() == Reloc::PIC_) {
240     // If it's local, or it's non-default, it can't be interposed.
241     if (!GV->hasLocalLinkage() &&
242         GV->hasDefaultVisibility()) {
243       flags |= PPCII::MO_NLP_FLAG;
244     }
245     return flags;
246   }
247 
248   if (GV->isStrongDefinitionForLinker())
249     return flags;
250   return flags | PPCII::MO_NLP_FLAG;
251 }
252 
253 bool PPCSubtarget::isELFv2ABI() const { return TM.isELFv2ABI(); }
254 bool PPCSubtarget::isPPC64() const { return TM.isPPC64(); }
255