1 //===-- PowerPCSubtarget.cpp - PPC Subtarget Information ------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements the PPC specific subclass of TargetSubtargetInfo.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "PPCSubtarget.h"
14 #include "PPC.h"
15 #include "PPCRegisterInfo.h"
16 #include "PPCTargetMachine.h"
17 #include "llvm/CodeGen/MachineFunction.h"
18 #include "llvm/CodeGen/MachineScheduler.h"
19 #include "llvm/IR/Attributes.h"
20 #include "llvm/IR/Function.h"
21 #include "llvm/IR/GlobalValue.h"
22 #include "llvm/Support/CommandLine.h"
23 #include "llvm/Support/TargetRegistry.h"
24 #include "llvm/Target/TargetMachine.h"
25 #include <cstdlib>
26 
27 using namespace llvm;
28 
29 #define DEBUG_TYPE "ppc-subtarget"
30 
31 #define GET_SUBTARGETINFO_TARGET_DESC
32 #define GET_SUBTARGETINFO_CTOR
33 #include "PPCGenSubtargetInfo.inc"
34 
35 static cl::opt<bool> UseSubRegLiveness("ppc-track-subreg-liveness",
36 cl::desc("Enable subregister liveness tracking for PPC"), cl::Hidden);
37 
38 static cl::opt<bool> QPXStackUnaligned("qpx-stack-unaligned",
39   cl::desc("Even when QPX is enabled the stack is not 32-byte aligned"),
40   cl::Hidden);
41 
42 static cl::opt<bool>
43     EnableMachinePipeliner("ppc-enable-pipeliner",
44                            cl::desc("Enable Machine Pipeliner for PPC"),
45                            cl::init(false), cl::Hidden);
46 
47 PPCSubtarget &PPCSubtarget::initializeSubtargetDependencies(StringRef CPU,
48                                                             StringRef FS) {
49   initializeEnvironment();
50   initSubtargetFeatures(CPU, FS);
51   return *this;
52 }
53 
54 PPCSubtarget::PPCSubtarget(const Triple &TT, const std::string &CPU,
55                            const std::string &FS, const PPCTargetMachine &TM)
56     : PPCGenSubtargetInfo(TT, CPU, FS), TargetTriple(TT),
57       IsPPC64(TargetTriple.getArch() == Triple::ppc64 ||
58               TargetTriple.getArch() == Triple::ppc64le),
59       TM(TM), FrameLowering(initializeSubtargetDependencies(CPU, FS)),
60       InstrInfo(*this), TLInfo(TM, *this) {}
61 
62 void PPCSubtarget::initializeEnvironment() {
63   StackAlignment = Align(16);
64   CPUDirective = PPC::DIR_NONE;
65   HasMFOCRF = false;
66   Has64BitSupport = false;
67   Use64BitRegs = false;
68   UseCRBits = false;
69   HasHardFloat = false;
70   HasAltivec = false;
71   HasSPE = false;
72   HasFPU = false;
73   HasQPX = false;
74   HasVSX = false;
75   NeedsTwoConstNR = false;
76   HasP8Vector = false;
77   HasP8Altivec = false;
78   HasP8Crypto = false;
79   HasP9Vector = false;
80   HasP9Altivec = false;
81   HasFCPSGN = false;
82   HasFSQRT = false;
83   HasFRE = false;
84   HasFRES = false;
85   HasFRSQRTE = false;
86   HasFRSQRTES = false;
87   HasRecipPrec = false;
88   HasSTFIWX = false;
89   HasLFIWAX = false;
90   HasFPRND = false;
91   HasFPCVT = false;
92   HasISEL = false;
93   HasBPERMD = false;
94   HasExtDiv = false;
95   HasCMPB = false;
96   HasLDBRX = false;
97   IsBookE = false;
98   HasOnlyMSYNC = false;
99   IsPPC4xx = false;
100   IsPPC6xx = false;
101   IsE500 = false;
102   FeatureMFTB = false;
103   AllowsUnalignedFPAccess = false;
104   DeprecatedDST = false;
105   HasLazyResolverStubs = false;
106   HasICBT = false;
107   HasInvariantFunctionDescriptors = false;
108   HasPartwordAtomics = false;
109   HasDirectMove = false;
110   IsQPXStackUnaligned = false;
111   HasHTM = false;
112   HasFloat128 = false;
113   IsISA3_0 = false;
114   UseLongCalls = false;
115   SecurePlt = false;
116   VectorsUseTwoUnits = false;
117   UsePPCPreRASchedStrategy = false;
118   UsePPCPostRASchedStrategy = false;
119 
120   HasPOPCNTD = POPCNTD_Unavailable;
121 }
122 
123 void PPCSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) {
124   // Determine default and user specified characteristics
125   std::string CPUName = CPU;
126   if (CPUName.empty() || CPU == "generic") {
127     // If cross-compiling with -march=ppc64le without -mcpu
128     if (TargetTriple.getArch() == Triple::ppc64le)
129       CPUName = "ppc64le";
130     else
131       CPUName = "generic";
132   }
133 
134   // Initialize scheduling itinerary for the specified CPU.
135   InstrItins = getInstrItineraryForCPU(CPUName);
136 
137   // Parse features string.
138   ParseSubtargetFeatures(CPUName, FS);
139 
140   // If the user requested use of 64-bit regs, but the cpu selected doesn't
141   // support it, ignore.
142   if (IsPPC64 && has64BitSupport())
143     Use64BitRegs = true;
144 
145   // Set up darwin-specific properties.
146   if (isDarwin())
147     HasLazyResolverStubs = true;
148 
149   if ((TargetTriple.isOSFreeBSD() && TargetTriple.getOSMajorVersion() >= 13) ||
150       TargetTriple.isOSNetBSD() || TargetTriple.isOSOpenBSD() ||
151       TargetTriple.isMusl())
152     SecurePlt = true;
153 
154   if (TargetTriple.getSubArch() == Triple::PPCSubArch_spe)
155     HasSPE = true;
156 
157   if (HasSPE && IsPPC64)
158     report_fatal_error( "SPE is only supported for 32-bit targets.\n", false);
159   if (HasSPE && (HasAltivec || HasQPX || HasVSX || HasFPU))
160     report_fatal_error(
161         "SPE and traditional floating point cannot both be enabled.\n", false);
162 
163   // If not SPE, set standard FPU
164   if (!HasSPE)
165     HasFPU = true;
166 
167   // QPX requires a 32-byte aligned stack. Note that we need to do this if
168   // we're compiling for a BG/Q system regardless of whether or not QPX
169   // is enabled because external functions will assume this alignment.
170   IsQPXStackUnaligned = QPXStackUnaligned;
171   StackAlignment = getPlatformStackAlignment();
172 
173   // Determine endianness.
174   // FIXME: Part of the TargetMachine.
175   IsLittleEndian = (TargetTriple.getArch() == Triple::ppc64le);
176 }
177 
178 /// Return true if accesses to the specified global have to go through a dyld
179 /// lazy resolution stub.  This means that an extra load is required to get the
180 /// address of the global.
181 bool PPCSubtarget::hasLazyResolverStub(const GlobalValue *GV) const {
182   if (!HasLazyResolverStubs)
183     return false;
184   if (!TM.shouldAssumeDSOLocal(*GV->getParent(), GV))
185     return true;
186   // 32 bit macho has no relocation for a-b if a is undefined, even if b is in
187   // the section that is being relocated. This means we have to use o load even
188   // for GVs that are known to be local to the dso.
189   if (GV->isDeclarationForLinker() || GV->hasCommonLinkage())
190     return true;
191   return false;
192 }
193 
194 bool PPCSubtarget::enableMachineScheduler() const { return true; }
195 
196 bool PPCSubtarget::enableMachinePipeliner() const {
197   return (CPUDirective == PPC::DIR_PWR9) && EnableMachinePipeliner;
198 }
199 
200 bool PPCSubtarget::useDFAforSMS() const { return false; }
201 
202 // This overrides the PostRAScheduler bit in the SchedModel for each CPU.
203 bool PPCSubtarget::enablePostRAScheduler() const { return true; }
204 
205 PPCGenSubtargetInfo::AntiDepBreakMode PPCSubtarget::getAntiDepBreakMode() const {
206   return TargetSubtargetInfo::ANTIDEP_ALL;
207 }
208 
209 void PPCSubtarget::getCriticalPathRCs(RegClassVector &CriticalPathRCs) const {
210   CriticalPathRCs.clear();
211   CriticalPathRCs.push_back(isPPC64() ?
212                             &PPC::G8RCRegClass : &PPC::GPRCRegClass);
213 }
214 
215 void PPCSubtarget::overrideSchedPolicy(MachineSchedPolicy &Policy,
216                                        unsigned NumRegionInstrs) const {
217   // The GenericScheduler that we use defaults to scheduling bottom up only.
218   // We want to schedule from both the top and the bottom and so we set
219   // OnlyBottomUp to false.
220   // We want to do bi-directional scheduling since it provides a more balanced
221   // schedule leading to better performance.
222   Policy.OnlyBottomUp = false;
223   // Spilling is generally expensive on all PPC cores, so always enable
224   // register-pressure tracking.
225   Policy.ShouldTrackPressure = true;
226 }
227 
228 bool PPCSubtarget::useAA() const {
229   return true;
230 }
231 
232 bool PPCSubtarget::enableSubRegLiveness() const {
233   return UseSubRegLiveness;
234 }
235 
236 bool PPCSubtarget::isGVIndirectSymbol(const GlobalValue *GV) const {
237   // Large code model always uses the TOC even for local symbols.
238   if (TM.getCodeModel() == CodeModel::Large)
239     return true;
240   if (TM.shouldAssumeDSOLocal(*GV->getParent(), GV))
241     return false;
242   return true;
243 }
244 
245 bool PPCSubtarget::isELFv2ABI() const { return TM.isELFv2ABI(); }
246 bool PPCSubtarget::isPPC64() const { return TM.isPPC64(); }
247