1 //===-- PowerPCSubtarget.cpp - PPC Subtarget Information ------------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the PPC specific subclass of TargetSubtargetInfo.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "PPCSubtarget.h"
15 #include "PPC.h"
16 #include "PPCRegisterInfo.h"
17 #include "llvm/CodeGen/MachineFunction.h"
18 #include "llvm/CodeGen/MachineScheduler.h"
19 #include "llvm/IR/Attributes.h"
20 #include "llvm/IR/Function.h"
21 #include "llvm/IR/GlobalValue.h"
22 #include "llvm/Support/Host.h"
23 #include "llvm/Support/TargetRegistry.h"
24 #include "llvm/Target/TargetMachine.h"
25 #include <cstdlib>
26 
27 using namespace llvm;
28 
29 #define DEBUG_TYPE "ppc-subtarget"
30 
31 #define GET_SUBTARGETINFO_TARGET_DESC
32 #define GET_SUBTARGETINFO_CTOR
33 #include "PPCGenSubtargetInfo.inc"
34 
35 /// Return the datalayout string of a subtarget.
36 static std::string getDataLayoutString(const Triple &T) {
37   bool is64Bit = T.getArch() == Triple::ppc64 || T.getArch() == Triple::ppc64le;
38   std::string Ret;
39 
40   // Most PPC* platforms are big endian, PPC64LE is little endian.
41   if (T.getArch() == Triple::ppc64le)
42     Ret = "e";
43   else
44     Ret = "E";
45 
46   Ret += DataLayout::getManglingComponent(T);
47 
48   // PPC32 has 32 bit pointers. The PS3 (OS Lv2) is a PPC64 machine with 32 bit
49   // pointers.
50   if (!is64Bit || T.getOS() == Triple::Lv2)
51     Ret += "-p:32:32";
52 
53   // Note, the alignment values for f64 and i64 on ppc64 in Darwin
54   // documentation are wrong; these are correct (i.e. "what gcc does").
55   if (is64Bit || !T.isOSDarwin())
56     Ret += "-i64:64";
57   else
58     Ret += "-f64:32:64";
59 
60   // PPC64 has 32 and 64 bit registers, PPC32 has only 32 bit ones.
61   if (is64Bit)
62     Ret += "-n32:64";
63   else
64     Ret += "-n32";
65 
66   return Ret;
67 }
68 
69 PPCSubtarget &PPCSubtarget::initializeSubtargetDependencies(StringRef CPU,
70                                                             StringRef FS) {
71   initializeEnvironment();
72   resetSubtargetFeatures(CPU, FS);
73   return *this;
74 }
75 
76 PPCSubtarget::PPCSubtarget(const std::string &TT, const std::string &CPU,
77                            const std::string &FS, PPCTargetMachine &TM,
78                            CodeGenOpt::Level OptLevel)
79     : PPCGenSubtargetInfo(TT, CPU, FS), TargetTriple(TT),
80       DL(getDataLayoutString(TargetTriple)),
81       IsPPC64(TargetTriple.getArch() == Triple::ppc64 ||
82               TargetTriple.getArch() == Triple::ppc64le),
83       OptLevel(OptLevel), TargetABI(PPC_ABI_UNKNOWN),
84       FrameLowering(initializeSubtargetDependencies(CPU, FS)), InstrInfo(*this),
85       JITInfo(*this), TLInfo(TM), TSInfo(&DL) {}
86 
87 /// SetJITMode - This is called to inform the subtarget info that we are
88 /// producing code for the JIT.
89 void PPCSubtarget::SetJITMode() {
90   // JIT mode doesn't want lazy resolver stubs, it knows exactly where
91   // everything is.  This matters for PPC64, which codegens in PIC mode without
92   // stubs.
93   HasLazyResolverStubs = false;
94 
95   // Calls to external functions need to use indirect calls
96   IsJITCodeModel = true;
97 }
98 
99 void PPCSubtarget::resetSubtargetFeatures(const MachineFunction *MF) {
100   AttributeSet FnAttrs = MF->getFunction()->getAttributes();
101   Attribute CPUAttr = FnAttrs.getAttribute(AttributeSet::FunctionIndex,
102                                            "target-cpu");
103   Attribute FSAttr = FnAttrs.getAttribute(AttributeSet::FunctionIndex,
104                                           "target-features");
105   std::string CPU =
106     !CPUAttr.hasAttribute(Attribute::None) ? CPUAttr.getValueAsString() : "";
107   std::string FS =
108     !FSAttr.hasAttribute(Attribute::None) ? FSAttr.getValueAsString() : "";
109   if (!FS.empty()) {
110     initializeEnvironment();
111     resetSubtargetFeatures(CPU, FS);
112   }
113 }
114 
115 void PPCSubtarget::initializeEnvironment() {
116   StackAlignment = 16;
117   DarwinDirective = PPC::DIR_NONE;
118   HasMFOCRF = false;
119   Has64BitSupport = false;
120   Use64BitRegs = false;
121   UseCRBits = false;
122   HasAltivec = false;
123   HasSPE = false;
124   HasQPX = false;
125   HasVSX = false;
126   HasFCPSGN = false;
127   HasFSQRT = false;
128   HasFRE = false;
129   HasFRES = false;
130   HasFRSQRTE = false;
131   HasFRSQRTES = false;
132   HasRecipPrec = false;
133   HasSTFIWX = false;
134   HasLFIWAX = false;
135   HasFPRND = false;
136   HasFPCVT = false;
137   HasISEL = false;
138   HasPOPCNTD = false;
139   HasLDBRX = false;
140   IsBookE = false;
141   IsPPC4xx = false;
142   IsPPC6xx = false;
143   IsE500 = false;
144   DeprecatedMFTB = false;
145   DeprecatedDST = false;
146   HasLazyResolverStubs = false;
147   IsJITCodeModel = false;
148 }
149 
150 void PPCSubtarget::resetSubtargetFeatures(StringRef CPU, StringRef FS) {
151   // Determine default and user specified characteristics
152   std::string CPUName = CPU;
153   if (CPUName.empty())
154     CPUName = "generic";
155 #if (defined(__APPLE__) || defined(__linux__)) && \
156     (defined(__ppc__) || defined(__powerpc__))
157   if (CPUName == "generic")
158     CPUName = sys::getHostCPUName();
159 #endif
160 
161   // Initialize scheduling itinerary for the specified CPU.
162   InstrItins = getInstrItineraryForCPU(CPUName);
163 
164   // Make sure 64-bit features are available when CPUname is generic
165   std::string FullFS = FS;
166 
167   // If we are generating code for ppc64, verify that options make sense.
168   if (IsPPC64) {
169     Has64BitSupport = true;
170     // Silently force 64-bit register use on ppc64.
171     Use64BitRegs = true;
172     if (!FullFS.empty())
173       FullFS = "+64bit," + FullFS;
174     else
175       FullFS = "+64bit";
176   }
177 
178   // At -O2 and above, track CR bits as individual registers.
179   if (OptLevel >= CodeGenOpt::Default) {
180     if (!FullFS.empty())
181       FullFS = "+crbits," + FullFS;
182     else
183       FullFS = "+crbits";
184   }
185 
186   // Parse features string.
187   ParseSubtargetFeatures(CPUName, FullFS);
188 
189   // If the user requested use of 64-bit regs, but the cpu selected doesn't
190   // support it, ignore.
191   if (use64BitRegs() && !has64BitSupport())
192     Use64BitRegs = false;
193 
194   // Set up darwin-specific properties.
195   if (isDarwin())
196     HasLazyResolverStubs = true;
197 
198   // QPX requires a 32-byte aligned stack. Note that we need to do this if
199   // we're compiling for a BG/Q system regardless of whether or not QPX
200   // is enabled because external functions will assume this alignment.
201   if (hasQPX() || isBGQ())
202     StackAlignment = 32;
203 
204   // Determine endianness.
205   IsLittleEndian = (TargetTriple.getArch() == Triple::ppc64le);
206 
207   // FIXME: For now, we disable VSX in little-endian mode until endian
208   // issues in those instructions can be addressed.
209   if (IsLittleEndian)
210     HasVSX = false;
211 
212   // Determine default ABI.
213   if (TargetABI == PPC_ABI_UNKNOWN) {
214     if (!isDarwin() && IsPPC64) {
215       if (IsLittleEndian)
216         TargetABI = PPC_ABI_ELFv2;
217       else
218         TargetABI = PPC_ABI_ELFv1;
219     }
220   }
221 }
222 
223 /// hasLazyResolverStub - Return true if accesses to the specified global have
224 /// to go through a dyld lazy resolution stub.  This means that an extra load
225 /// is required to get the address of the global.
226 bool PPCSubtarget::hasLazyResolverStub(const GlobalValue *GV,
227                                        const TargetMachine &TM) const {
228   // We never have stubs if HasLazyResolverStubs=false or if in static mode.
229   if (!HasLazyResolverStubs || TM.getRelocationModel() == Reloc::Static)
230     return false;
231   // If symbol visibility is hidden, the extra load is not needed if
232   // the symbol is definitely defined in the current translation unit.
233   bool isDecl = GV->isDeclaration() && !GV->isMaterializable();
234   if (GV->hasHiddenVisibility() && !isDecl && !GV->hasCommonLinkage())
235     return false;
236   return GV->hasWeakLinkage() || GV->hasLinkOnceLinkage() ||
237          GV->hasCommonLinkage() || isDecl;
238 }
239 
240 // Embedded cores need aggressive scheduling (and some others also benefit).
241 static bool needsAggressiveScheduling(unsigned Directive) {
242   switch (Directive) {
243   default: return false;
244   case PPC::DIR_440:
245   case PPC::DIR_A2:
246   case PPC::DIR_E500mc:
247   case PPC::DIR_E5500:
248   case PPC::DIR_PWR7:
249   case PPC::DIR_PWR8:
250     return true;
251   }
252 }
253 
254 bool PPCSubtarget::enableMachineScheduler() const {
255   // Enable MI scheduling for the embedded cores.
256   // FIXME: Enable this for all cores (some additional modeling
257   // may be necessary).
258   return needsAggressiveScheduling(DarwinDirective);
259 }
260 
261 // This overrides the PostRAScheduler bit in the SchedModel for each CPU.
262 bool PPCSubtarget::enablePostMachineScheduler() const { return true; }
263 
264 PPCGenSubtargetInfo::AntiDepBreakMode PPCSubtarget::getAntiDepBreakMode() const {
265   return TargetSubtargetInfo::ANTIDEP_ALL;
266 }
267 
268 void PPCSubtarget::getCriticalPathRCs(RegClassVector &CriticalPathRCs) const {
269   CriticalPathRCs.clear();
270   CriticalPathRCs.push_back(isPPC64() ?
271                             &PPC::G8RCRegClass : &PPC::GPRCRegClass);
272 }
273 
274 void PPCSubtarget::overrideSchedPolicy(MachineSchedPolicy &Policy,
275                                        MachineInstr *begin,
276                                        MachineInstr *end,
277                                        unsigned NumRegionInstrs) const {
278   if (needsAggressiveScheduling(DarwinDirective)) {
279     Policy.OnlyTopDown = false;
280     Policy.OnlyBottomUp = false;
281   }
282 
283   // Spilling is generally expensive on all PPC cores, so always enable
284   // register-pressure tracking.
285   Policy.ShouldTrackPressure = true;
286 }
287 
288 bool PPCSubtarget::useAA() const {
289   // Use AA during code generation for the embedded cores.
290   return needsAggressiveScheduling(DarwinDirective);
291 }
292 
293