1 //===-- PowerPCSubtarget.cpp - PPC Subtarget Information ------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements the PPC specific subclass of TargetSubtargetInfo. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "PPCSubtarget.h" 15 #include "PPC.h" 16 #include "PPCRegisterInfo.h" 17 #include "PPCTargetMachine.h" 18 #include "llvm/CodeGen/MachineFunction.h" 19 #include "llvm/CodeGen/MachineScheduler.h" 20 #include "llvm/IR/Attributes.h" 21 #include "llvm/IR/Function.h" 22 #include "llvm/IR/GlobalValue.h" 23 #include "llvm/Support/CommandLine.h" 24 #include "llvm/Support/Host.h" 25 #include "llvm/Support/TargetRegistry.h" 26 #include "llvm/Target/TargetMachine.h" 27 #include <cstdlib> 28 29 using namespace llvm; 30 31 #define DEBUG_TYPE "ppc-subtarget" 32 33 #define GET_SUBTARGETINFO_TARGET_DESC 34 #define GET_SUBTARGETINFO_CTOR 35 #include "PPCGenSubtargetInfo.inc" 36 37 static cl::opt<bool> UseSubRegLiveness("ppc-track-subreg-liveness", 38 cl::desc("Enable subregister liveness tracking for PPC"), cl::Hidden); 39 40 PPCSubtarget &PPCSubtarget::initializeSubtargetDependencies(StringRef CPU, 41 StringRef FS) { 42 initializeEnvironment(); 43 initSubtargetFeatures(CPU, FS); 44 return *this; 45 } 46 47 PPCSubtarget::PPCSubtarget(const std::string &TT, const std::string &CPU, 48 const std::string &FS, const PPCTargetMachine &TM) 49 : PPCGenSubtargetInfo(TT, CPU, FS), TargetTriple(TT), 50 IsPPC64(TargetTriple.getArch() == Triple::ppc64 || 51 TargetTriple.getArch() == Triple::ppc64le), 52 TargetABI(PPC_ABI_UNKNOWN), 53 FrameLowering(initializeSubtargetDependencies(CPU, FS)), InstrInfo(*this), 54 TLInfo(TM, *this), TSInfo(TM.getDataLayout()) {} 55 56 void PPCSubtarget::initializeEnvironment() { 57 StackAlignment = 16; 58 DarwinDirective = PPC::DIR_NONE; 59 HasMFOCRF = false; 60 Has64BitSupport = false; 61 Use64BitRegs = false; 62 UseCRBits = false; 63 HasAltivec = false; 64 HasSPE = false; 65 HasQPX = false; 66 HasVSX = false; 67 HasP8Vector = false; 68 HasP8Altivec = false; 69 HasFCPSGN = false; 70 HasFSQRT = false; 71 HasFRE = false; 72 HasFRES = false; 73 HasFRSQRTE = false; 74 HasFRSQRTES = false; 75 HasRecipPrec = false; 76 HasSTFIWX = false; 77 HasLFIWAX = false; 78 HasFPRND = false; 79 HasFPCVT = false; 80 HasISEL = false; 81 HasPOPCNTD = false; 82 HasCMPB = false; 83 HasLDBRX = false; 84 IsBookE = false; 85 HasOnlyMSYNC = false; 86 IsPPC4xx = false; 87 IsPPC6xx = false; 88 IsE500 = false; 89 DeprecatedMFTB = false; 90 DeprecatedDST = false; 91 HasLazyResolverStubs = false; 92 HasICBT = false; 93 HasInvariantFunctionDescriptors = false; 94 } 95 96 void PPCSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) { 97 // Determine default and user specified characteristics 98 std::string CPUName = CPU; 99 if (CPUName.empty()) { 100 // If cross-compiling with -march=ppc64le without -mcpu 101 if (TargetTriple.getArch() == Triple::ppc64le) 102 CPUName = "ppc64le"; 103 else 104 CPUName = "generic"; 105 } 106 #if (defined(__APPLE__) || defined(__linux__)) && \ 107 (defined(__ppc__) || defined(__powerpc__)) 108 if (CPUName == "generic") 109 CPUName = sys::getHostCPUName(); 110 #endif 111 112 // Initialize scheduling itinerary for the specified CPU. 113 InstrItins = getInstrItineraryForCPU(CPUName); 114 115 // Parse features string. 116 ParseSubtargetFeatures(CPUName, FS); 117 118 // If the user requested use of 64-bit regs, but the cpu selected doesn't 119 // support it, ignore. 120 if (IsPPC64 && has64BitSupport()) 121 Use64BitRegs = true; 122 123 // Set up darwin-specific properties. 124 if (isDarwin()) 125 HasLazyResolverStubs = true; 126 127 // QPX requires a 32-byte aligned stack. Note that we need to do this if 128 // we're compiling for a BG/Q system regardless of whether or not QPX 129 // is enabled because external functions will assume this alignment. 130 if (hasQPX() || isBGQ()) 131 StackAlignment = 32; 132 133 // Determine endianness. 134 IsLittleEndian = (TargetTriple.getArch() == Triple::ppc64le); 135 136 // Determine default ABI. 137 if (TargetABI == PPC_ABI_UNKNOWN) { 138 if (!isDarwin() && IsPPC64) { 139 if (IsLittleEndian) 140 TargetABI = PPC_ABI_ELFv2; 141 else 142 TargetABI = PPC_ABI_ELFv1; 143 } 144 } 145 } 146 147 /// hasLazyResolverStub - Return true if accesses to the specified global have 148 /// to go through a dyld lazy resolution stub. This means that an extra load 149 /// is required to get the address of the global. 150 bool PPCSubtarget::hasLazyResolverStub(const GlobalValue *GV, 151 const TargetMachine &TM) const { 152 // We never have stubs if HasLazyResolverStubs=false or if in static mode. 153 if (!HasLazyResolverStubs || TM.getRelocationModel() == Reloc::Static) 154 return false; 155 bool isDecl = GV->isDeclaration(); 156 if (GV->hasHiddenVisibility() && !isDecl && !GV->hasCommonLinkage()) 157 return false; 158 return GV->hasWeakLinkage() || GV->hasLinkOnceLinkage() || 159 GV->hasCommonLinkage() || isDecl; 160 } 161 162 // Embedded cores need aggressive scheduling (and some others also benefit). 163 static bool needsAggressiveScheduling(unsigned Directive) { 164 switch (Directive) { 165 default: return false; 166 case PPC::DIR_440: 167 case PPC::DIR_A2: 168 case PPC::DIR_E500mc: 169 case PPC::DIR_E5500: 170 case PPC::DIR_PWR7: 171 case PPC::DIR_PWR8: 172 return true; 173 } 174 } 175 176 bool PPCSubtarget::enableMachineScheduler() const { 177 // Enable MI scheduling for the embedded cores. 178 // FIXME: Enable this for all cores (some additional modeling 179 // may be necessary). 180 return needsAggressiveScheduling(DarwinDirective); 181 } 182 183 // This overrides the PostRAScheduler bit in the SchedModel for each CPU. 184 bool PPCSubtarget::enablePostMachineScheduler() const { return true; } 185 186 PPCGenSubtargetInfo::AntiDepBreakMode PPCSubtarget::getAntiDepBreakMode() const { 187 return TargetSubtargetInfo::ANTIDEP_ALL; 188 } 189 190 void PPCSubtarget::getCriticalPathRCs(RegClassVector &CriticalPathRCs) const { 191 CriticalPathRCs.clear(); 192 CriticalPathRCs.push_back(isPPC64() ? 193 &PPC::G8RCRegClass : &PPC::GPRCRegClass); 194 } 195 196 void PPCSubtarget::overrideSchedPolicy(MachineSchedPolicy &Policy, 197 MachineInstr *begin, 198 MachineInstr *end, 199 unsigned NumRegionInstrs) const { 200 if (needsAggressiveScheduling(DarwinDirective)) { 201 Policy.OnlyTopDown = false; 202 Policy.OnlyBottomUp = false; 203 } 204 205 // Spilling is generally expensive on all PPC cores, so always enable 206 // register-pressure tracking. 207 Policy.ShouldTrackPressure = true; 208 } 209 210 bool PPCSubtarget::useAA() const { 211 // Use AA during code generation for the embedded cores. 212 return needsAggressiveScheduling(DarwinDirective); 213 } 214 215 bool PPCSubtarget::enableSubRegLiveness() const { 216 return UseSubRegLiveness; 217 } 218 219