1 //===-- PowerPCSubtarget.cpp - PPC Subtarget Information ------------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the PPC specific subclass of TargetSubtargetInfo.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "PPCSubtarget.h"
15 #include "PPC.h"
16 #include "PPCRegisterInfo.h"
17 #include "PPCTargetMachine.h"
18 #include "llvm/CodeGen/MachineFunction.h"
19 #include "llvm/CodeGen/MachineScheduler.h"
20 #include "llvm/IR/Attributes.h"
21 #include "llvm/IR/Function.h"
22 #include "llvm/IR/GlobalValue.h"
23 #include "llvm/Support/CommandLine.h"
24 #include "llvm/Support/Host.h"
25 #include "llvm/Support/TargetRegistry.h"
26 #include "llvm/Target/TargetMachine.h"
27 #include <cstdlib>
28 
29 using namespace llvm;
30 
31 #define DEBUG_TYPE "ppc-subtarget"
32 
33 #define GET_SUBTARGETINFO_TARGET_DESC
34 #define GET_SUBTARGETINFO_CTOR
35 #include "PPCGenSubtargetInfo.inc"
36 
37 static cl::opt<bool> UseSubRegLiveness("ppc-track-subreg-liveness",
38 cl::desc("Enable subregister liveness tracking for PPC"), cl::Hidden);
39 
40 PPCSubtarget &PPCSubtarget::initializeSubtargetDependencies(StringRef CPU,
41                                                             StringRef FS) {
42   initializeEnvironment();
43   initSubtargetFeatures(CPU, FS);
44   return *this;
45 }
46 
47 PPCSubtarget::PPCSubtarget(const std::string &TT, const std::string &CPU,
48                            const std::string &FS, const PPCTargetMachine &TM)
49     : PPCGenSubtargetInfo(TT, CPU, FS), TargetTriple(TT),
50       IsPPC64(TargetTriple.getArch() == Triple::ppc64 ||
51               TargetTriple.getArch() == Triple::ppc64le),
52       TargetABI(PPC_ABI_UNKNOWN),
53       FrameLowering(initializeSubtargetDependencies(CPU, FS)), InstrInfo(*this),
54       TLInfo(TM, *this), TSInfo(TM.getDataLayout()) {}
55 
56 void PPCSubtarget::initializeEnvironment() {
57   StackAlignment = 16;
58   DarwinDirective = PPC::DIR_NONE;
59   HasMFOCRF = false;
60   Has64BitSupport = false;
61   Use64BitRegs = false;
62   UseCRBits = false;
63   HasAltivec = false;
64   HasSPE = false;
65   HasQPX = false;
66   HasVSX = false;
67   HasP8Vector = false;
68   HasFCPSGN = false;
69   HasFSQRT = false;
70   HasFRE = false;
71   HasFRES = false;
72   HasFRSQRTE = false;
73   HasFRSQRTES = false;
74   HasRecipPrec = false;
75   HasSTFIWX = false;
76   HasLFIWAX = false;
77   HasFPRND = false;
78   HasFPCVT = false;
79   HasISEL = false;
80   HasPOPCNTD = false;
81   HasCMPB = false;
82   HasLDBRX = false;
83   IsBookE = false;
84   HasOnlyMSYNC = false;
85   IsPPC4xx = false;
86   IsPPC6xx = false;
87   IsE500 = false;
88   DeprecatedMFTB = false;
89   DeprecatedDST = false;
90   HasLazyResolverStubs = false;
91   HasICBT = false;
92   HasInvariantFunctionDescriptors = false;
93 }
94 
95 void PPCSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) {
96   // Determine default and user specified characteristics
97   std::string CPUName = CPU;
98   if (CPUName.empty()) {
99     // If cross-compiling with -march=ppc64le without -mcpu
100     if (TargetTriple.getArch() == Triple::ppc64le)
101       CPUName = "ppc64le";
102     else
103       CPUName = "generic";
104   }
105 #if (defined(__APPLE__) || defined(__linux__)) && \
106     (defined(__ppc__) || defined(__powerpc__))
107   if (CPUName == "generic")
108     CPUName = sys::getHostCPUName();
109 #endif
110 
111   // Initialize scheduling itinerary for the specified CPU.
112   InstrItins = getInstrItineraryForCPU(CPUName);
113 
114   // Parse features string.
115   ParseSubtargetFeatures(CPUName, FS);
116 
117   // If the user requested use of 64-bit regs, but the cpu selected doesn't
118   // support it, ignore.
119   if (IsPPC64 && has64BitSupport())
120     Use64BitRegs = true;
121 
122   // Set up darwin-specific properties.
123   if (isDarwin())
124     HasLazyResolverStubs = true;
125 
126   // QPX requires a 32-byte aligned stack. Note that we need to do this if
127   // we're compiling for a BG/Q system regardless of whether or not QPX
128   // is enabled because external functions will assume this alignment.
129   if (hasQPX() || isBGQ())
130     StackAlignment = 32;
131 
132   // Determine endianness.
133   IsLittleEndian = (TargetTriple.getArch() == Triple::ppc64le);
134 
135   // Determine default ABI.
136   if (TargetABI == PPC_ABI_UNKNOWN) {
137     if (!isDarwin() && IsPPC64) {
138       if (IsLittleEndian)
139         TargetABI = PPC_ABI_ELFv2;
140       else
141         TargetABI = PPC_ABI_ELFv1;
142     }
143   }
144 }
145 
146 /// hasLazyResolverStub - Return true if accesses to the specified global have
147 /// to go through a dyld lazy resolution stub.  This means that an extra load
148 /// is required to get the address of the global.
149 bool PPCSubtarget::hasLazyResolverStub(const GlobalValue *GV,
150                                        const TargetMachine &TM) const {
151   // We never have stubs if HasLazyResolverStubs=false or if in static mode.
152   if (!HasLazyResolverStubs || TM.getRelocationModel() == Reloc::Static)
153     return false;
154   bool isDecl = GV->isDeclaration();
155   if (GV->hasHiddenVisibility() && !isDecl && !GV->hasCommonLinkage())
156     return false;
157   return GV->hasWeakLinkage() || GV->hasLinkOnceLinkage() ||
158          GV->hasCommonLinkage() || isDecl;
159 }
160 
161 // Embedded cores need aggressive scheduling (and some others also benefit).
162 static bool needsAggressiveScheduling(unsigned Directive) {
163   switch (Directive) {
164   default: return false;
165   case PPC::DIR_440:
166   case PPC::DIR_A2:
167   case PPC::DIR_E500mc:
168   case PPC::DIR_E5500:
169   case PPC::DIR_PWR7:
170   case PPC::DIR_PWR8:
171     return true;
172   }
173 }
174 
175 bool PPCSubtarget::enableMachineScheduler() const {
176   // Enable MI scheduling for the embedded cores.
177   // FIXME: Enable this for all cores (some additional modeling
178   // may be necessary).
179   return needsAggressiveScheduling(DarwinDirective);
180 }
181 
182 // This overrides the PostRAScheduler bit in the SchedModel for each CPU.
183 bool PPCSubtarget::enablePostMachineScheduler() const { return true; }
184 
185 PPCGenSubtargetInfo::AntiDepBreakMode PPCSubtarget::getAntiDepBreakMode() const {
186   return TargetSubtargetInfo::ANTIDEP_ALL;
187 }
188 
189 void PPCSubtarget::getCriticalPathRCs(RegClassVector &CriticalPathRCs) const {
190   CriticalPathRCs.clear();
191   CriticalPathRCs.push_back(isPPC64() ?
192                             &PPC::G8RCRegClass : &PPC::GPRCRegClass);
193 }
194 
195 void PPCSubtarget::overrideSchedPolicy(MachineSchedPolicy &Policy,
196                                        MachineInstr *begin,
197                                        MachineInstr *end,
198                                        unsigned NumRegionInstrs) const {
199   if (needsAggressiveScheduling(DarwinDirective)) {
200     Policy.OnlyTopDown = false;
201     Policy.OnlyBottomUp = false;
202   }
203 
204   // Spilling is generally expensive on all PPC cores, so always enable
205   // register-pressure tracking.
206   Policy.ShouldTrackPressure = true;
207 }
208 
209 bool PPCSubtarget::useAA() const {
210   // Use AA during code generation for the embedded cores.
211   return needsAggressiveScheduling(DarwinDirective);
212 }
213 
214 bool PPCSubtarget::enableSubRegLiveness() const {
215   return UseSubRegLiveness;
216 }
217 
218