1 //===-- PowerPCSubtarget.cpp - PPC Subtarget Information ------------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the PPC specific subclass of TargetSubtargetInfo.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "PPCSubtarget.h"
15 #include "PPC.h"
16 #include "PPCRegisterInfo.h"
17 #include "PPCTargetMachine.h"
18 #include "llvm/CodeGen/MachineFunction.h"
19 #include "llvm/CodeGen/MachineScheduler.h"
20 #include "llvm/IR/Attributes.h"
21 #include "llvm/IR/Function.h"
22 #include "llvm/IR/GlobalValue.h"
23 #include "llvm/Support/CommandLine.h"
24 #include "llvm/Support/TargetRegistry.h"
25 #include "llvm/Target/TargetMachine.h"
26 #include <cstdlib>
27 
28 using namespace llvm;
29 
30 #define DEBUG_TYPE "ppc-subtarget"
31 
32 #define GET_SUBTARGETINFO_TARGET_DESC
33 #define GET_SUBTARGETINFO_CTOR
34 #include "PPCGenSubtargetInfo.inc"
35 
36 static cl::opt<bool> UseSubRegLiveness("ppc-track-subreg-liveness",
37 cl::desc("Enable subregister liveness tracking for PPC"), cl::Hidden);
38 
39 static cl::opt<bool> QPXStackUnaligned("qpx-stack-unaligned",
40   cl::desc("Even when QPX is enabled the stack is not 32-byte aligned"),
41   cl::Hidden);
42 
43 PPCSubtarget &PPCSubtarget::initializeSubtargetDependencies(StringRef CPU,
44                                                             StringRef FS) {
45   initializeEnvironment();
46   initSubtargetFeatures(CPU, FS);
47   return *this;
48 }
49 
50 PPCSubtarget::PPCSubtarget(const Triple &TT, const std::string &CPU,
51                            const std::string &FS, const PPCTargetMachine &TM)
52     : PPCGenSubtargetInfo(TT, CPU, FS), TargetTriple(TT),
53       IsPPC64(TargetTriple.getArch() == Triple::ppc64 ||
54               TargetTriple.getArch() == Triple::ppc64le),
55       TM(TM), FrameLowering(initializeSubtargetDependencies(CPU, FS)),
56       InstrInfo(*this), TLInfo(TM, *this) {}
57 
58 void PPCSubtarget::initializeEnvironment() {
59   StackAlignment = 16;
60   DarwinDirective = PPC::DIR_NONE;
61   HasMFOCRF = false;
62   Has64BitSupport = false;
63   Use64BitRegs = false;
64   UseCRBits = false;
65   HasHardFloat = false;
66   HasAltivec = false;
67   HasSPE = false;
68   HasFPU = false;
69   HasQPX = false;
70   HasVSX = false;
71   HasP8Vector = false;
72   HasP8Altivec = false;
73   HasP8Crypto = false;
74   HasP9Vector = false;
75   HasP9Altivec = false;
76   HasFCPSGN = false;
77   HasFSQRT = false;
78   HasFRE = false;
79   HasFRES = false;
80   HasFRSQRTE = false;
81   HasFRSQRTES = false;
82   HasRecipPrec = false;
83   HasSTFIWX = false;
84   HasLFIWAX = false;
85   HasFPRND = false;
86   HasFPCVT = false;
87   HasISEL = false;
88   HasBPERMD = false;
89   HasExtDiv = false;
90   HasCMPB = false;
91   HasLDBRX = false;
92   IsBookE = false;
93   HasOnlyMSYNC = false;
94   IsPPC4xx = false;
95   IsPPC6xx = false;
96   IsE500 = false;
97   FeatureMFTB = false;
98   DeprecatedDST = false;
99   HasLazyResolverStubs = false;
100   HasICBT = false;
101   HasInvariantFunctionDescriptors = false;
102   HasPartwordAtomics = false;
103   HasDirectMove = false;
104   IsQPXStackUnaligned = false;
105   HasHTM = false;
106   HasFusion = false;
107   HasFloat128 = false;
108   IsISA3_0 = false;
109   UseLongCalls = false;
110   SecurePlt = false;
111 
112   HasPOPCNTD = POPCNTD_Unavailable;
113 }
114 
115 void PPCSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) {
116   // Determine default and user specified characteristics
117   std::string CPUName = CPU;
118   if (CPUName.empty() || CPU == "generic") {
119     // If cross-compiling with -march=ppc64le without -mcpu
120     if (TargetTriple.getArch() == Triple::ppc64le)
121       CPUName = "ppc64le";
122     else
123       CPUName = "generic";
124   }
125 
126   // Initialize scheduling itinerary for the specified CPU.
127   InstrItins = getInstrItineraryForCPU(CPUName);
128 
129   // Parse features string.
130   ParseSubtargetFeatures(CPUName, FS);
131 
132   // If the user requested use of 64-bit regs, but the cpu selected doesn't
133   // support it, ignore.
134   if (IsPPC64 && has64BitSupport())
135     Use64BitRegs = true;
136 
137   // Set up darwin-specific properties.
138   if (isDarwin())
139     HasLazyResolverStubs = true;
140 
141   if (HasSPE && IsPPC64)
142     report_fatal_error( "SPE is only supported for 32-bit targets.\n", false);
143   if (HasSPE && (HasAltivec || HasQPX || HasVSX || HasFPU))
144     report_fatal_error(
145         "SPE and traditional floating point cannot both be enabled.\n", false);
146 
147   // If not SPE, set standard FPU
148   if (!HasSPE)
149     HasFPU = true;
150 
151   // QPX requires a 32-byte aligned stack. Note that we need to do this if
152   // we're compiling for a BG/Q system regardless of whether or not QPX
153   // is enabled because external functions will assume this alignment.
154   IsQPXStackUnaligned = QPXStackUnaligned;
155   StackAlignment = getPlatformStackAlignment();
156 
157   // Determine endianness.
158   // FIXME: Part of the TargetMachine.
159   IsLittleEndian = (TargetTriple.getArch() == Triple::ppc64le);
160 }
161 
162 /// Return true if accesses to the specified global have to go through a dyld
163 /// lazy resolution stub.  This means that an extra load is required to get the
164 /// address of the global.
165 bool PPCSubtarget::hasLazyResolverStub(const GlobalValue *GV) const {
166   if (!HasLazyResolverStubs)
167     return false;
168   if (!TM.shouldAssumeDSOLocal(*GV->getParent(), GV))
169     return true;
170   // 32 bit macho has no relocation for a-b if a is undefined, even if b is in
171   // the section that is being relocated. This means we have to use o load even
172   // for GVs that are known to be local to the dso.
173   if (GV->isDeclarationForLinker() || GV->hasCommonLinkage())
174     return true;
175   return false;
176 }
177 
178 // Embedded cores need aggressive scheduling (and some others also benefit).
179 static bool needsAggressiveScheduling(unsigned Directive) {
180   switch (Directive) {
181   default: return false;
182   case PPC::DIR_440:
183   case PPC::DIR_A2:
184   case PPC::DIR_E500mc:
185   case PPC::DIR_E5500:
186   case PPC::DIR_PWR7:
187   case PPC::DIR_PWR8:
188   // FIXME: Same as P8 until POWER9 scheduling info is available
189   case PPC::DIR_PWR9:
190     return true;
191   }
192 }
193 
194 bool PPCSubtarget::enableMachineScheduler() const {
195   // Enable MI scheduling for the embedded cores.
196   // FIXME: Enable this for all cores (some additional modeling
197   // may be necessary).
198   return needsAggressiveScheduling(DarwinDirective);
199 }
200 
201 // This overrides the PostRAScheduler bit in the SchedModel for each CPU.
202 bool PPCSubtarget::enablePostRAScheduler() const { return true; }
203 
204 PPCGenSubtargetInfo::AntiDepBreakMode PPCSubtarget::getAntiDepBreakMode() const {
205   return TargetSubtargetInfo::ANTIDEP_ALL;
206 }
207 
208 void PPCSubtarget::getCriticalPathRCs(RegClassVector &CriticalPathRCs) const {
209   CriticalPathRCs.clear();
210   CriticalPathRCs.push_back(isPPC64() ?
211                             &PPC::G8RCRegClass : &PPC::GPRCRegClass);
212 }
213 
214 void PPCSubtarget::overrideSchedPolicy(MachineSchedPolicy &Policy,
215                                        unsigned NumRegionInstrs) const {
216   if (needsAggressiveScheduling(DarwinDirective)) {
217     Policy.OnlyTopDown = false;
218     Policy.OnlyBottomUp = false;
219   }
220 
221   // Spilling is generally expensive on all PPC cores, so always enable
222   // register-pressure tracking.
223   Policy.ShouldTrackPressure = true;
224 }
225 
226 bool PPCSubtarget::useAA() const {
227   // Use AA during code generation for the embedded cores.
228   return needsAggressiveScheduling(DarwinDirective);
229 }
230 
231 bool PPCSubtarget::enableSubRegLiveness() const {
232   return UseSubRegLiveness;
233 }
234 
235 unsigned char
236 PPCSubtarget::classifyGlobalReference(const GlobalValue *GV) const {
237   // Note that currently we don't generate non-pic references.
238   // If a caller wants that, this will have to be updated.
239 
240   // Large code model always uses the TOC even for local symbols.
241   if (TM.getCodeModel() == CodeModel::Large)
242     return PPCII::MO_PIC_FLAG | PPCII::MO_NLP_FLAG;
243 
244   if (TM.shouldAssumeDSOLocal(*GV->getParent(), GV))
245     return PPCII::MO_PIC_FLAG;
246   return PPCII::MO_PIC_FLAG | PPCII::MO_NLP_FLAG;
247 }
248 
249 bool PPCSubtarget::isELFv2ABI() const { return TM.isELFv2ABI(); }
250 bool PPCSubtarget::isPPC64() const { return TM.isPPC64(); }
251